Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26081

1

T1

2

T2

159

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20751

1

T2

159

T5

1

T8

125

auto[ADC_CTRL_FILTER_COND_OUT]

5330

1

T1

2

T3

1

T4

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20451

1

T2

159

T4

13

T8

125

auto[1]

5630

1

T1

2

T3

1

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21936

1

T1

2

T2

159

T3

1

auto[1]

4145

1

T4

7

T6

15

T9

30

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	96	1			T237	8		T197	11		T238	14
values[1]	603	1			T239	1		T13	2		T142	1
values[2]	681	1			T4	13		T9	2		T154	7
values[3]	553	1			T9	29		T15	10		T239	1
values[4]	563	1			T18	35		T141	1		T240	11
values[5]	748	1			T9	13		T14	33		T111	23
values[6]	738	1			T5	1		T12	17		T15	21
values[7]	795	1			T10	13		T122	23		T143	22
values[8]	621	1			T239	1		T13	31		T123	21
values[9]	3155	1			T1	2		T3	1		T6	17
minimum	17528	1			T2	159		T8	125		T9	173

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	865	1			T239	1		T154	7		T13	2
values[1]	2712	1			T1	2		T3	1		T4	13
values[2]	497	1			T9	2		T18	15		T239	1
values[3]	652	1			T14	33		T18	20		T135	1
values[4]	651	1			T9	13		T111	23		T135	1
values[5]	786	1			T5	1		T12	17		T15	21
values[6]	596	1			T10	13		T13	1		T191	11
values[7]	742	1			T239	1		T139	1		T13	30
values[8]	792	1			T16	4		T19	25		T139	1
values[9]	218	1			T125	9		T141	1		T145	1
minimum	17570	1			T2	159		T8	125		T9	173

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

3481

1

T4

5

T7

8

T9

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T113	1		T128	10		T146	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T239	1		T154	7		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T9	14		T15	1		T123	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1230	1			T1	2		T3	1		T4	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	1		T111	10		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T18	6		T239	1		T156	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T124	1		T141	1		T240	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	14		T18	6		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T111	10		T139	19		T114	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T9	5		T135	1		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	1		T15	12		T31	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	5		T122	13		T143	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T218	3		T241	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T10	1		T13	1		T191	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	14		T123	13		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T239	1		T139	1		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T16	2		T139	1		T122	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T19	13		T122	1		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T171	1		T173	5		T242	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T125	9		T141	1		T145	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17370	1			T2	159		T8	125		T9	167
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T243	1		T244	9		T245	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T113	18		T128	8		T246	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	1		T151	12		T143	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T9	15		T15	9		T123	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1047	1			T4	7		T6	15		T132	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T9	1		T115	11		T247	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T18	9		T116	5		T147	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T124	9		T240	10		T248	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	19		T18	14		T112	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T111	13		T139	2		T127	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T9	8		T113	14		T249	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	9		T31	2		T118	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	12		T122	10		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T218	1		T130	2		T246	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T10	12		T191	7		T250	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	16		T123	8		T113	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T127	6		T250	10		T251	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T16	2		T122	6		T144	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T19	12		T122	17		T252	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T171	1		T173	10		T253	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T254	8		T255	13		T211	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	6		T10	1		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T244	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T197	1		T256	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T237	5		T238	14		T257	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T258	7		T113	1		T128	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T239	1		T13	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	1		T123	3		T112	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	6		T154	7		T151	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	14		T15	1		T111	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T239	1		T135	1		T203	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T141	1		T240	1		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T18	12		T116	12		T118	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T111	10		T139	19		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	5		T14	14		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	1		T15	12		T31	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	5		T237	10		T258	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T218	3		T241	1		T116	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	1		T122	13		T143	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	14		T123	13		T259	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T239	1		T13	1		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T16	2		T139	1		T122	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1373	1			T1	2		T3	1		T6	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17367	1			T2	159		T8	125		T9	167
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T197	10		T256	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T237	3		T260	10		T261	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T258	7		T113	18		T128	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	1		T143	9		T54	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	1		T123	12		T116	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T4	7		T151	12		T251	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	15		T15	9		T123	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T203	1		T147	6		T262	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T240	10		T263	10		T195	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T18	23		T116	5		T118	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T111	13		T139	2		T124	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T9	8		T14	19		T112	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	9		T31	2		T128	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	12		T237	11		T258	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T218	1		T116	8		T130	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T10	12		T122	10		T143	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	16		T123	8		T240	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T127	6		T264	13		T265	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T16	2		T122	6		T144	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1188	1			T6	15		T19	12		T132	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T10	1		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T113	19		T128	9		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T239	1		T154	1		T13	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T9	17		T15	10		T123	26
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1371	1			T1	2		T3	1		T4	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	2		T111	1		T115	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T18	10		T239	1		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T124	10		T141	1		T240	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T14	25		T18	15		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T111	14		T139	3		T114	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T9	11		T135	1		T113	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	1		T15	10		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T12	13		T122	11		T143	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T218	4		T241	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	13		T13	1		T191	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T13	17		T123	9		T113	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T239	1		T139	1		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T16	4		T139	1		T122	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T19	13		T122	18		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T171	2		T173	11		T242	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T125	1		T141	1		T145	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17531	1			T2	159		T8	125		T9	173
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T243	1		T244	13		T245	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T128	9		T146	10		T266	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T154	6		T151	9		T143	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	12		T123	2		T112	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	906	1			T4	5		T7	8		T17	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T111	9		T247	11		T246	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T18	5		T156	14		T116	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T267	2		T248	13		T268	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	8		T18	5		T258	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T111	9		T139	18		T114	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T9	2		T172	16		T249	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T15	11		T31	5		T126	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	4		T122	12		T143	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T146	10		T269	12		T130	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T191	3		T126	12		T250	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	13		T123	12		T259	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T127	7		T250	2		T251	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T122	9		T144	2		T218	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T19	12		T252	12		T117	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T173	4		T242	9		T150	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T125	8		T120	4		T254	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T256	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T244	8		T181	13		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T197	11		T256	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T237	4		T238	1		T257	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T258	8		T113	19		T128	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T239	1		T13	2		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	2		T123	13		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T4	8		T154	1		T151	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T9	17		T15	10		T111	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T239	1		T135	1		T203	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T141	1		T240	11		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T18	25		T116	6		T118	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T111	14		T139	3		T124	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T9	11		T14	25		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	1		T15	10		T31	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	13		T237	12		T258	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T218	4		T241	1		T116	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T10	13		T122	11		T143	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	17		T123	9		T259	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T239	1		T13	1		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T16	4		T139	1		T122	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1551	1			T1	2		T3	1		T6	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T2	159		T8	125		T9	173
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T256	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T237	4		T238	13		T260	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T258	6		T128	9		T266	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T143	9		T267	13		T270	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T123	2		T112	9		T116	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T4	5		T154	6		T151	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	12		T111	9		T173	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T156	14		T262	5		T271	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T268	14		T272	10		T273	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T18	10		T116	11		T118	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T111	9		T139	18		T114	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T9	2		T14	8		T258	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	11		T31	5		T126	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	4		T237	9		T258	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T116	9		T146	10		T269	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T122	12		T143	9		T191	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	13		T123	12		T259	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T127	7		T264	9		T274	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T122	9		T144	2		T218	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1010	1			T7	8		T17	8		T19	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

auto[0]

3481

1

T4

5

T7

8

T9

14

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26081

1

T1

2

T2

159

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23022

1

T1

2

T2

159

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3059

1

T5

1

T14

33

T15

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20459

1

T2

159

T5

1

T8

125

auto[1]

5622

1

T1

2

T3

1

T4

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21936

1

T1

2

T2

159

T3

1

auto[1]

4145

1

T4

7

T6

15

T9

30

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	34	1			T221	4		T163	30		-	-
values[0]	12	1			T159	1		T275	11		-	-
values[1]	606	1			T5	1		T9	2		T141	1
values[2]	738	1			T14	33		T239	1		T135	1
values[3]	680	1			T18	15		T239	1		T111	23
values[4]	593	1			T12	17		T16	2		T239	1
values[5]	2719	1			T1	2		T3	1		T6	17
values[6]	780	1			T15	10		T139	21		T123	15
values[7]	583	1			T111	10		T156	10		T259	5
values[8]	698	1			T4	13		T9	13		T15	21
values[9]	1110	1			T10	13		T154	7		T139	1
minimum	17528	1			T2	159		T8	125		T9	173

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	828	1			T5	1		T9	2		T14	33
values[1]	637	1			T18	15		T239	1		T139	1
values[2]	582	1			T12	17		T239	1		T111	23
values[3]	2601	1			T1	2		T3	1		T6	17
values[4]	828	1			T9	29		T16	2		T19	25
values[5]	673	1			T15	10		T139	21		T123	15
values[6]	712	1			T111	10		T113	14		T156	10
values[7]	603	1			T4	13		T9	13		T10	13
values[8]	740	1			T139	1		T122	18		T123	21
values[9]	257	1			T154	7		T13	2		T115	8
minimum	17620	1			T2	159		T8	125		T9	173

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

3481

1

T4

5

T7

8

T9

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T9	1		T135	1		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	1		T14	14		T125	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T18	6		T239	1		T13	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T139	1		T13	1		T151	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	5		T124	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T239	1		T111	10		T122	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T1	2		T3	1		T6	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T16	1		T141	1		T156	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T9	14		T16	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T19	13		T123	1		T31	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T139	19		T144	1		T259	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	1		T123	3		T203	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T111	10		T156	10		T114	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T113	1		T259	5		T193	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T4	6		T9	5		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T112	10		T172	12		T119	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T123	13		T252	13		T237	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T139	1		T122	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T13	1		T173	1		T192	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T154	7		T115	1		T266	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17406	1			T2	159		T8	125		T9	167
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T272	12		T275	11		T276	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T9	1		T143	9		T144	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	19		T115	11		T240	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T18	9		T13	16		T113	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T151	12		T218	2		T240	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T12	12		T117	1		T127	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T111	13		T122	10		T258	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T6	15		T132	15		T122	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T16	1		T24	4		T277	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	15		T16	1		T112	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T19	12		T123	12		T31	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T139	2		T117	5		T173	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T15	9		T123	12		T203	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T246	2		T264	2		T265	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T113	13		T193	11		T248	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	7		T9	8		T10	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T119	10		T130	13		T278	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T123	8		T252	14		T237	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T122	17		T237	3		T128	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T13	1		T192	4		T279	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T115	7		T280	12		T257	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	6		T10	1		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T272	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T221	3		T163	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T159	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T275	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T9	1		T141	1		T144	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T5	1		T115	1		T240	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T239	1		T135	1		T13	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	14		T125	9		T151	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T18	6		T124	1		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T239	1		T111	10		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	5		T239	1		T122	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T16	1		T141	1		T156	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T1	2		T3	1		T6	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T19	13		T123	1		T31	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T139	19		T112	1		T114	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	1		T123	3		T203	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T111	10		T156	10		T173	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T259	5		T127	7		T242	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T4	6		T9	5		T15	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T112	10		T113	1		T119	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T10	1		T13	1		T123	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T154	7		T139	1		T122	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17367	1			T2	159		T8	125		T9	167
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T221	1		T163	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	1		T144	2		T116	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T115	11		T240	11		T116	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	16		T143	9		T191	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	19		T151	12		T218	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T18	9		T117	1		T281	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T111	13		T122	10		T258	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	12		T122	6		T127	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T16	1		T282	5		T24	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1068	1			T6	15		T9	15		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T19	12		T123	12		T31	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T139	2		T112	9		T116	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T15	9		T123	12		T203	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T173	10		T265	1		T263	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T127	10		T248	12		T283	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T4	7		T9	8		T15	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T113	13		T119	10		T130	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T10	12		T13	1		T123	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T122	17		T237	3		T115	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T10	1		T14	2