Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26081

1

T1

2

T2

159

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22874

1

T1

2

T2

159

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3207

1

T5

1

T9

31

T15

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20434

1

T2

159

T8

125

T9

173

auto[1]

5647

1

T1

2

T3

1

T4

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21936

1

T1

2

T2

159

T3

1

auto[1]

4145

1

T4

7

T6

15

T9

30

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	34	1			T251	20		T330	1		T331	9
values[0]	81	1			T9	13		T240	12		T74	6
values[1]	708	1			T16	2		T239	1		T111	10
values[2]	2680	1			T1	2		T3	1		T6	17
values[3]	600	1			T122	23		T112	10		T144	5
values[4]	488	1			T9	29		T15	10		T16	2
values[5]	864	1			T10	13		T18	20		T154	7
values[6]	705	1			T12	17		T14	33		T15	21
values[7]	454	1			T5	1		T111	23		T139	22
values[8]	654	1			T4	13		T13	30		T123	13
values[9]	1285	1			T9	2		T239	1		T203	2
minimum	17528	1			T2	159		T8	125		T9	173

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	874	1			T9	13		T239	1		T111	10
values[1]	2796	1			T1	2		T3	1		T6	17
values[2]	501	1			T117	11		T129	1		T242	10
values[3]	642	1			T9	29		T15	10		T16	2
values[4]	787	1			T10	13		T14	33		T18	20
values[5]	641	1			T5	1		T12	17		T15	21
values[6]	484	1			T111	23		T139	22		T13	30
values[7]	697	1			T4	13		T239	1		T13	1
values[8]	906	1			T9	2		T155	1		T156	10
values[9]	216	1			T203	2		T259	5		T116	22
minimum	17537	1			T2	159		T8	125		T9	173

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

3481

1

T4

5

T7

8

T9

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T9	5		T239	1		T111	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T135	1		T122	1		T31	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T1	2		T3	1		T6	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	1		T122	13		T112	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T129	1		T246	3		T24	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T117	7		T242	10		T332	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T16	1		T139	1		T144	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	14		T15	1		T122	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T10	1		T14	14		T125	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T18	6		T154	7		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	5		T15	12		T18	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	1		T19	13		T123	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T111	10		T139	20		T112	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	14		T123	1		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	6		T141	1		T259	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T239	1		T13	1		T151	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T126	3		T115	1		T240	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T9	1		T155	1		T156	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T203	1		T259	5		T247	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T116	12		T119	9		T333	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17368	1			T2	159		T8	125		T9	167
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T74	6		T334	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T9	8		T124	9		T143	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T122	17		T31	2		T258	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1143	1			T6	15		T132	15		T207	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T13	1		T122	10		T128	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T246	2		T24	4		T272	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T117	4		T217	5		T283	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T16	1		T144	2		T237	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T9	15		T15	9		T122	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	12		T14	19		T115	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T18	14		T251	2		T279	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	12		T15	9		T18	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T19	12		T123	12		T63	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T111	13		T139	2		T112	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	16		T123	12		T171	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T4	7		T262	4		T255	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T151	12		T192	4		T287	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T115	11		T240	9		T153	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	1		T128	8		T173	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T203	1		T247	14		T251	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T116	10		T119	2		T333	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	6		T10	1		T14	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T251	10		T330	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T331	4		T276	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T9	5		T240	1		T335	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T74	6		T336	1		T158	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T16	1		T239	1		T111	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T135	1		T122	1		T31	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T1	2		T3	1		T6	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T13	1		T144	1		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T144	3		T113	1		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T122	13		T112	10		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T16	1		T237	5		T258	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	14		T15	1		T122	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T10	1		T139	1		T125	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T18	6		T154	7		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	5		T14	14		T15	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T19	13		T123	3		T156	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T111	10		T139	20		T123	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T5	1		T13	1		T171	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T4	6		T141	1		T126	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	14		T123	1		T151	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T203	1		T115	1		T259	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T9	1		T239	1		T155	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17367	1			T2	159		T8	125		T9	167
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T251	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T331	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T9	8		T240	11		T335	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T336	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T16	1		T124	9		T143	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T122	17		T31	2		T258	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1097	1			T6	15		T132	15		T207	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	1		T113	14		T128	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T144	2		T113	13		T127	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T122	10		T117	4		T265	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T16	1		T237	3		T258	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T9	15		T15	9		T122	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T10	12		T115	7		T240	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T18	14		T143	9		T252	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	12		T14	19		T15	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T19	12		T123	12		T251	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T111	13		T139	2		T123	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T171	1		T250	9		T282	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T4	7		T173	10		T255	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	16		T123	12		T151	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T203	1		T115	11		T240	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T9	1		T116	10		T128	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T10	1		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T9	11		T239	1		T111	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T135	1		T122	18		T31	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1491	1			T1	2		T3	1		T6	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	2		T122	11		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T129	1		T246	3		T24	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T117	5		T242	1		T332	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T16	2		T139	1		T144	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	17		T15	10		T122	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T10	13		T14	25		T125	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T18	15		T154	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	13		T15	10		T18	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	1		T19	13		T123	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T111	14		T139	4		T112	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	17		T123	13		T171	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	8		T141	1		T259	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T239	1		T13	1		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T126	1		T115	12		T240	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T9	2		T155	1		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T203	2		T259	1		T247	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T116	11		T119	3		T333	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17530	1			T2	159		T8	125		T9	173
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T74	4		T334	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	2		T111	9		T143	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T31	5		T258	15		T116	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T7	8		T17	8		T134	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T122	12		T112	9		T128	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T246	2		T24	2		T272	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T117	6		T242	9		T217	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T144	2		T237	4		T258	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	12		T122	9		T143	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	8		T125	8		T127	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T18	5		T154	6		T172	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	4		T15	11		T18	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T19	12		T123	2		T156	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T111	9		T139	18		T191	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T13	13		T148	3		T250	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T4	5		T259	10		T262	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T151	9		T126	12		T267	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T126	2		T153	2		T173	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T156	9		T114	16		T128	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T259	4		T251	9		T337	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T116	11		T119	8		T333	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T74	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T251	11		T330	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T331	6		T276	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T9	11		T240	12		T335	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T74	4		T336	12		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T16	2		T239	1		T111	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T135	1		T122	18		T31	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T1	2		T3	1		T6	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T13	2		T144	1		T113	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T144	3		T113	14		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T122	11		T112	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T16	2		T237	4		T258	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	17		T15	10		T122	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T10	13		T139	1		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T18	15		T154	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T12	13		T14	25		T15	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T19	13		T123	13		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T111	14		T139	4		T123	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	1		T13	1		T171	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T4	8		T141	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	17		T123	13		T151	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	388	1			T203	2		T115	12		T259	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T9	2		T239	1		T155	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T2	159		T8	125		T9	173
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T251	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T331	3		T276	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T9	2		T335	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T74	2		T158	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T111	9		T143	9		T116	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T31	5		T258	15		T116	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	979	1			T7	8		T17	8		T134	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T128	8		T148	15		T246	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T144	2		T127	6		T247	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T122	12		T112	9		T117	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T237	4		T258	20		T279	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T9	12		T122	9		T237	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T125	8		T127	7		T172	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T18	5		T154	6		T143	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	4		T14	8		T15	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T19	12		T123	2		T156	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T111	9		T139	18		T123	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T250	8		T269	12		T248	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T4	5		T126	2		T259	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	13		T151	9		T126	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T259	4		T153	2		T118	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T156	9		T114	16		T116	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

auto[0]

3481

1

T4

5

T7

8

T9

14