Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26081

1

T1

2

T2

159

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22735

1

T1

2

T2

159

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3346

1

T4

13

T5

1

T9

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20718

1

T2

159

T5

1

T8

125

auto[1]

5363

1

T1

2

T3

1

T4

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21936

1

T1

2

T2

159

T3

1

auto[1]

4145

1

T4

7

T6

15

T9

30

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	37	1			T281	10		T251	13		T338	1
values[0]	96	1			T125	9		T118	21		T339	1
values[1]	538	1			T9	13		T111	10		T13	3
values[2]	642	1			T16	2		T135	1		T151	22
values[3]	611	1			T5	1		T16	2		T13	30
values[4]	683	1			T9	29		T122	16		T142	1
values[5]	721	1			T4	13		T9	2		T10	13
values[6]	719	1			T14	33		T239	1		T139	1
values[7]	777	1			T154	7		T111	23		T141	1
values[8]	2598	1			T1	2		T3	1		T6	17
values[9]	1131	1			T15	21		T18	15		T239	1
minimum	17528	1			T2	159		T8	125		T9	173

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	727	1			T9	13		T111	10		T13	3
values[1]	737	1			T135	1		T13	30		T112	10
values[2]	530	1			T5	1		T9	29		T16	4
values[3]	683	1			T9	2		T12	17		T15	10
values[4]	707	1			T10	13		T14	33		T135	1
values[5]	855	1			T4	13		T239	1		T111	23
values[6]	2602	1			T1	2		T3	1		T6	17
values[7]	730	1			T18	20		T139	21		T122	23
values[8]	695	1			T18	15		T239	1		T122	18
values[9]	253	1			T15	21		T19	25		T144	5
minimum	17562	1			T2	159		T8	125		T9	173

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

3481

1

T4

5

T7

8

T9

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T111	10		T151	10		T124	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T9	5		T13	2		T123	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T135	1		T13	14		T112	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T218	3		T240	1		T116	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	14		T16	1		T112	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	1		T16	1		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	1		T239	1		T31	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	5		T15	1		T122	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T14	14		T135	1		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T10	1		T139	1		T156	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T239	1		T111	10		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T4	6		T203	1		T252	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1220	1			T1	2		T3	1		T6	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T139	1		T123	13		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T139	19		T122	13		T258	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T18	6		T123	1		T143	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T18	6		T239	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T141	1		T143	10		T113	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T144	3		T116	12		T332	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T15	12		T19	13		T251	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17372	1			T2	159		T8	125		T9	167
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T309	1		T340	1		T341	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T151	12		T116	8		T117	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	8		T13	1		T123	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T13	16		T112	9		T237	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T218	1		T240	10		T116	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T9	15		T16	1		T258	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T16	1		T113	18		T117	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	1		T31	2		T237	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	12		T15	9		T122	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	19		T147	6		T250	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	12		T117	4		T250	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T111	13		T115	7		T240	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T4	7		T203	1		T252	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T6	15		T132	15		T207	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T123	8		T124	9		T128	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T139	2		T122	10		T258	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T18	14		T123	12		T143	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T18	9		T122	17		T153	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T143	9		T113	27		T127	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T144	2		T116	5		T255	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T15	9		T19	12		T251	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	6		T10	1		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T341	3		T342	1		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T338	1		T343	1		T344	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T281	1		T251	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T339	1		T257	3		T345	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T125	9		T118	11		T346	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T111	10		T124	1		T116	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T9	5		T13	2		T123	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T16	1		T135	1		T151	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T146	14		T129	1		T266	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	14		T126	13		T240	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	1		T16	1		T113	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	14		T112	10		T218	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T122	10		T142	1		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T9	1		T239	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T4	6		T10	1		T12	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T14	14		T239	1		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T139	1		T155	1		T114	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T154	7		T111	10		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T252	13		T144	1		T258	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T1	2		T3	1		T6	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T18	6		T139	1		T123	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T18	6		T239	1		T139	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T15	12		T19	13		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17367	1			T2	159		T8	125		T9	167
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T281	9		T251	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T257	8		T345	2		T35	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T118	10		T346	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T116	8		T117	1		T153	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T9	8		T13	1		T123	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T16	1		T151	12		T112	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T264	2		T271	2		T279	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	16		T240	11		T119	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T16	1		T113	18		T218	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	15		T218	1		T153	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T122	6		T247	14		T281	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T9	1		T31	2		T237	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	7		T10	12		T12	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	19		T115	7		T128	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T117	4		T119	10		T250	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T111	13		T258	7		T240	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T252	14		T258	6		T128	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T6	15		T132	15		T122	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T18	14		T123	20		T124	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T18	9		T139	2		T122	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T15	9		T19	12		T143	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T10	1		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T111	1		T151	13		T124	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	11		T13	3		T123	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T135	1		T13	17		T112	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T218	4		T240	11		T116	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	17		T16	2		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T5	1		T16	2		T113	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	2		T239	1		T31	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	13		T15	10		T122	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	25		T135	1		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	13		T139	1		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T239	1		T111	14		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T4	8		T203	2		T252	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T1	2		T3	1		T6	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T139	1		T123	9		T124	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T139	3		T122	11		T258	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T18	15		T123	13		T143	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T18	10		T239	1		T122	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T141	1		T143	10		T113	29
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T144	3		T116	6		T332	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T15	10		T19	13		T251	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17549	1			T2	159		T8	125		T9	173
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T309	1		T340	1		T341	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T111	9		T151	9		T116	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	2		T123	2		T125	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	13		T237	9		T247	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T116	11		T146	13		T266	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	12		T112	9		T258	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T156	14		T259	10		T117	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T31	5		T237	4		T126	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T12	4		T122	9		T347	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T14	8		T267	2		T250	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T156	9		T114	3		T117	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T111	9		T128	12		T120	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	5		T252	12		T118	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	893	1			T7	8		T17	8		T154	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T123	12		T128	9		T246	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T139	18		T122	12		T258	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T18	5		T143	9		T258	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T18	5		T119	7		T266	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T143	9		T127	7		T148	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T144	2		T116	11		T255	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T15	11		T19	12		T251	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T257	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T342	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T338	1		T343	1		T344	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T281	10		T251	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T339	1		T257	9		T345	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T125	1		T118	11		T346	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T111	1		T124	1		T116	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	11		T13	3		T123	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T16	2		T135	1		T151	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T146	1		T129	1		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	17		T126	1		T240	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	1		T16	2		T113	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T9	17		T112	1		T218	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T122	7		T142	1		T247	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	2		T239	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T4	8		T10	13		T12	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T14	25		T239	1		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T139	1		T155	1		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T154	1		T111	14		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T252	15		T144	1		T258	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T1	2		T3	1		T6	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T18	15		T139	1		T123	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T18	10		T239	1		T139	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T15	10		T19	13		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T2	159		T8	125		T9	173
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T344	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T251	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T257	2		T345	11		T35	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T125	8		T118	10		T346	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T111	9		T116	9		T153	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T9	2		T123	2		T126	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T151	9		T237	9		T258	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T146	13		T266	1		T264	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	13		T126	12		T119	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T156	14		T259	10		T116	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	12		T112	9		T218	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T122	9		T347	9		T74	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T31	5		T237	4		T128	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T4	5		T12	4		T156	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T14	8		T128	12		T267	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T114	3		T117	6		T119	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T154	6		T111	9		T258	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T252	12		T258	15		T128	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	910	1			T7	8		T17	8		T134	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T18	5		T123	12		T114	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T18	5		T139	18		T144	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T15	11		T19	12		T143	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

auto[0]

3481

1

T4

5

T7

8

T9

14