Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26081

1

T1

2

T2

159

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22660

1

T1

2

T2

159

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3421

1

T5

1

T9

44

T10

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20046

1

T2

157

T8

124

T9

172

auto[1]

6035

1

T1

2

T2

2

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21936

1

T1

2

T2

159

T3

1

auto[1]

4145

1

T4

7

T6

15

T9

30

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	608	1			T2	2		T8	1		T9	3
values[0]	83	1			T135	1		T123	21		T297	10
values[1]	548	1			T111	23		T139	1		T13	1
values[2]	2624	1			T1	2		T3	1		T5	1
values[3]	664	1			T19	25		T154	7		T125	9
values[4]	792	1			T18	15		T111	10		T122	41
values[5]	742	1			T15	10		T239	1		T139	21
values[6]	574	1			T9	13		T14	33		T13	30
values[7]	746	1			T4	13		T12	17		T239	1
values[8]	501	1			T16	4		T135	1		T31	9
values[9]	1102	1			T9	31		T10	13		T18	20
minimum	17097	1			T2	157		T8	124		T9	170

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	557	1			T5	1		T139	1		T144	1
values[1]	2638	1			T1	2		T3	1		T6	17
values[2]	626	1			T125	9		T151	22		T143	19
values[3]	817	1			T15	10		T18	15		T111	10
values[4]	782	1			T239	1		T139	21		T141	1
values[5]	624	1			T9	13		T14	33		T13	30
values[6]	624	1			T4	13		T12	17		T239	1
values[7]	600	1			T16	4		T203	2		T31	9
values[8]	956	1			T9	2		T18	20		T13	2
values[9]	110	1			T9	29		T10	13		T287	14
minimum	17747	1			T2	159		T8	125		T9	173

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

3481

1

T4

5

T7

8

T9

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T139	1		T115	1		T267	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	1		T144	1		T240	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T1	2		T3	1		T6	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	12		T19	13		T154	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T125	9		T143	10		T112	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T151	10		T240	1		T148	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T111	10		T122	1		T258	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T15	1		T18	6		T122	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T239	1		T139	19		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T113	1		T218	3		T116	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	14		T13	14		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T9	5		T123	3		T241	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T4	6		T12	5		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T124	1		T237	10		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T16	1		T203	1		T144	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T16	1		T31	7		T258	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T18	6		T123	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T9	1		T13	1		T122	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T287	1		T195	1		T288	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T9	14		T10	1		T304	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17423	1			T2	159		T8	125		T9	167
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T111	10		T135	1		T139	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T115	7		T282	3		T294	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T240	9		T173	10		T247	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1048	1			T6	15		T132	15		T207	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T15	9		T19	12		T118	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T143	9		T218	1		T290	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T151	12		T240	10		T282	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T122	17		T258	6		T116	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T15	9		T18	9		T122	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T139	2		T112	9		T116	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T113	13		T218	1		T116	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	19		T13	16		T124	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T9	8		T123	12		T171	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T4	7		T12	12		T252	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T237	11		T113	14		T115	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T16	1		T203	1		T144	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T16	1		T31	2		T258	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T18	14		T123	12		T143	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T9	1		T13	1		T122	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T287	13		T195	7		T292	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T9	15		T10	12		T56	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	6		T10	1		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T111	13		T123	8		T71	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	473	1			T2	2		T8	1		T9	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T122	10		T248	14		T347	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T310	16		T166	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T135	1		T123	13		T297	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T153	1		T267	14		T294	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T111	10		T139	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T1	2		T3	1		T6	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	1		T15	12		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T125	9		T143	10		T112	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T19	13		T154	7		T151	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T111	10		T122	1		T145	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T18	6		T122	13		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T239	1		T139	19		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T15	1		T113	1		T218	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T14	14		T13	14		T191	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	5		T123	3		T241	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T4	6		T12	5		T239	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T124	1		T237	10		T113	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T16	1		T135	1		T117	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T16	1		T31	7		T118	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T18	6		T123	1		T203	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T9	15		T10	1		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16936	1			T2	157		T8	124		T9	164
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T287	13		T265	1		T290	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T122	6		T248	12		T347	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T310	14		T166	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T123	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T153	1		T294	4		T295	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T111	13		T173	10		T247	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1019	1			T6	15		T132	15		T207	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	9		T240	9		T118	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T143	9		T218	1		T131	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T19	12		T151	12		T240	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T122	17		T117	1		T153	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T18	9		T122	10		T237	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T139	2		T112	9		T258	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T15	9		T113	13		T218	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	19		T13	16		T191	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T9	8		T123	12		T130	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	7		T12	12		T124	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T237	11		T113	14		T115	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T16	1		T117	9		T173	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T16	1		T31	2		T118	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T18	14		T123	12		T203	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T9	16		T10	12		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T10	1		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T139	1		T115	8		T267	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T5	1		T144	1		T240	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T1	2		T3	1		T6	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	10		T19	13		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T125	1		T143	10		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T151	13		T240	11		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T111	1		T122	18		T258	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T15	10		T18	10		T122	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T239	1		T139	3		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T113	14		T218	2		T116	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T14	25		T13	17		T124	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	11		T123	13		T241	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T4	8		T12	13		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T124	1		T237	12		T113	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T16	2		T203	2		T144	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T16	2		T31	4		T258	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T18	15		T123	13		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T9	2		T13	2		T122	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T287	14		T195	8		T288	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T9	17		T10	13		T304	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17591	1			T2	159		T8	125		T9	173
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T111	14		T135	1		T139	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T267	13		T294	5		T295	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T173	4		T148	15		T269	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	940	1			T7	8		T17	8		T134	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T15	11		T19	12		T154	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T125	8		T143	9		T112	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T151	9		T148	3		T274	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T111	9		T258	15		T126	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T18	5		T122	12		T237	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T139	18		T116	11		T127	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T218	2		T116	9		T127	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	8		T13	13		T258	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T9	2		T123	2		T130	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T4	5		T12	4		T252	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T237	9		T128	8		T247	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T144	2		T117	8		T173	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T31	5		T258	6		T156	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T18	5		T143	9		T156	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T122	9		T128	12		T251	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T198	9		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T9	12		T304	2		T56	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T301	12		T310	15		T348	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T111	9		T123	12		T297	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	478	1			T2	2		T8	1		T9	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T122	7		T248	13		T347	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T310	15		T166	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T135	1		T123	9		T297	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T153	2		T267	1		T294	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T111	14		T139	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T1	2		T3	1		T6	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	1		T15	10		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T125	1		T143	10		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T19	13		T154	1		T151	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T111	1		T122	18		T145	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T18	10		T122	11		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T239	1		T139	3		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T15	10		T113	14		T218	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	25		T13	17		T191	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	11		T123	13		T241	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T4	8		T12	13		T239	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T124	1		T237	12		T113	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T16	2		T135	1		T117	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T16	2		T31	4		T118	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T18	15		T123	13		T203	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T9	19		T10	13		T13	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17097	1			T2	157		T8	124		T9	170
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T290	10		T349	11		T350	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T122	9		T248	13		T347	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T310	15		T166	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T123	12		T297	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T267	13		T294	5		T295	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T111	9		T173	4		T148	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	924	1			T7	8		T17	8		T134	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T15	11		T118	5		T217	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T125	8		T143	9		T112	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T19	12		T154	6		T151	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T111	9		T114	3		T153	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T18	5		T122	12		T237	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T139	18		T258	15		T126	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T218	2		T116	9		T127	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	8		T13	13		T191	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T9	2		T123	2		T130	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T4	5		T12	4		T252	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T237	9		T128	8		T119	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T117	8		T173	4		T150	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T31	5		T118	10		T247	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T18	5		T143	9		T144	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T9	12		T258	6		T156	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

auto[0]

3481

1

T4

5

T7

8

T9

14