Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26081

1

T1

2

T2

159

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22932

1

T1

2

T2

159

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3149

1

T9

13

T10

13

T15

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20837

1

T2

159

T4

13

T5

1

auto[1]

5244

1

T1

2

T3

1

T6

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21936

1

T1

2

T2

159

T3

1

auto[1]

4145

1

T4

7

T6

15

T9

30

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	309	1			T4	13		T5	1		T154	7
values[0]	30	1			T203	2		T127	14		T301	9
values[1]	597	1			T15	10		T135	2		T139	21
values[2]	649	1			T9	29		T141	2		T156	10
values[3]	695	1			T13	30		T122	16		T31	9
values[4]	760	1			T15	21		T16	4		T18	15
values[5]	507	1			T19	25		T124	10		T252	27
values[6]	641	1			T9	13		T139	2		T123	28
values[7]	560	1			T9	2		T18	20		T142	1
values[8]	613	1			T239	1		T111	10		T123	21
values[9]	3192	1			T1	2		T3	1		T6	17
minimum	17528	1			T2	159		T8	125		T9	173

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	709	1			T9	29		T15	10		T135	1
values[1]	437	1			T112	10		T114	14		T127	17
values[2]	774	1			T16	2		T13	30		T122	16
values[3]	677	1			T15	21		T16	2		T18	15
values[4]	597	1			T9	13		T19	25		T139	1
values[5]	582	1			T9	2		T139	1		T123	28
values[6]	2566	1			T1	2		T3	1		T6	17
values[7]	780	1			T239	1		T111	23		T113	34
values[8]	995	1			T4	13		T5	1		T10	13
values[9]	197	1			T12	17		T259	5		T281	3
minimum	17767	1			T2	159		T8	125		T9	173

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

3481

1

T4

5

T7

8

T9

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	14		T122	1		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T15	1		T135	1		T141	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T112	10		T114	14		T119	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T127	7		T128	13		T118	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T16	1		T31	7		T258	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	14		T122	10		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T15	12		T16	1		T18	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T112	1		T237	10		T218	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T19	13		T139	1		T252	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T9	5		T125	9		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	1		T123	3		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T139	1		T123	1		T172	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T1	2		T3	1		T6	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T18	6		T123	13		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T111	10		T113	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T239	1		T113	1		T114	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T4	6		T5	1		T14	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T10	1		T154	7		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T12	5		T259	5		T300	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T281	1		T246	3		T24	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17456	1			T2	159		T8	125		T9	167
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T139	19		T203	1		T127	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	15		T122	17		T173	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T15	9		T258	7		T240	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T119	3		T130	2		T176	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T127	10		T128	10		T118	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T16	1		T31	2		T258	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	16		T122	6		T144	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	9		T16	1		T18	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T112	9		T237	11		T218	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T19	12		T252	14		T258	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	8		T124	9		T118	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	1		T123	12		T247	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T123	12		T130	13		T279	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1089	1			T6	15		T132	15		T207	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T18	14		T123	8		T209	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T111	13		T113	18		T287	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T113	14		T240	20		T194	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	7		T14	19		T218	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T10	12		T13	1		T122	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T12	12		T300	10		T53	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T281	2		T246	2		T24	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T9	6		T10	1		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T139	2		T203	1		T127	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T4	6		T5	1		T259	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T154	7		T128	10		T281	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T301	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T203	1		T127	8		T308	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T135	1		T122	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T15	1		T135	1		T139	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T9	14		T156	10		T114	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T141	2		T240	1		T127	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T31	7		T112	10		T258	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	14		T122	10		T144	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T15	12		T16	2		T18	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T124	1		T237	10		T218	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T19	13		T252	13		T191	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T124	1		T112	1		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T139	1		T123	3		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T9	5		T139	1		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	1		T143	10		T156	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T18	6		T142	1		T172	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T239	1		T111	10		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T123	13		T114	4		T240	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T1	2		T3	1		T6	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T10	1		T239	1		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17367	1			T2	159		T8	125		T9	167
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T4	7		T153	1		T282	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T128	8		T281	2		T246	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T301	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T203	1		T127	6		T313	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T122	17		T173	10		T264	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T15	9		T139	2		T258	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T9	15		T119	3		T130	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T240	10		T127	10		T128	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T31	2		T258	6		T147	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	16		T122	6		T144	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T15	9		T16	2		T18	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T237	11		T218	1		T119	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T19	12		T252	14		T191	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T124	9		T112	9		T115	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T123	12		T258	6		T113	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T9	8		T123	12		T279	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	1		T143	9		T117	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T18	14		T130	13		T209	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T115	11		T250	25		T287	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T123	8		T240	11		T194	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1168	1			T6	15		T12	12		T14	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T10	12		T13	1		T122	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T10	1		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	17		T122	18		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T15	10		T135	1		T141	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T112	1		T114	1		T119	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T127	11		T128	11		T118	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T16	2		T31	4		T258	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	17		T122	7		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T15	10		T16	2		T18	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T112	10		T237	12		T218	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T19	13		T139	1		T252	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	11		T125	1		T124	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	2		T123	13		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T139	1		T123	13		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1427	1			T1	2		T3	1		T6	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T18	15		T123	9		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T111	14		T113	19		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T239	1		T113	15		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T4	8		T5	1		T14	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T10	13		T154	1		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T12	13		T259	1		T300	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T281	3		T246	3		T24	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17595	1			T2	159		T8	125		T9	173
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T139	3		T203	2		T127	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	12		T156	9		T173	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T258	6		T148	15		T269	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T112	9		T114	13		T119	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T127	6		T128	12		T118	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T31	5		T258	15		T271	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	13		T122	9		T144	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T15	11		T18	5		T151	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T237	9		T218	2		T119	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T19	12		T252	12		T258	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T9	2		T125	8		T118	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T123	2		T126	2		T247	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T172	16		T146	23		T120	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	934	1			T7	8		T17	8		T111	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T18	5		T123	12		T295	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T111	9		T120	4		T270	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T114	3		T267	13		T194	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	5		T14	8		T267	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T154	6		T122	12		T143	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T12	4		T259	4		T210	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T246	2		T24	2		T351	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T264	9		T274	8		T306	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T139	18		T127	7		T172	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T4	8		T5	1		T259	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T154	1		T128	9		T281	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T301	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T203	2		T127	7		T308	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T135	1		T122	18		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T15	10		T135	1		T139	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T9	17		T156	1		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T141	2		T240	11		T127	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T31	4		T112	1		T258	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	17		T122	7		T144	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T15	10		T16	4		T18	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T124	1		T237	12		T218	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T19	13		T252	15		T191	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T124	10		T112	10		T115	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T139	1		T123	13		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	11		T139	1		T123	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T9	2		T143	10		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T18	15		T142	1		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T239	1		T111	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T123	9		T114	1		T240	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1531	1			T1	2		T3	1		T6	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	404	1			T10	13		T239	1		T13	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T2	159		T8	125		T9	173
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T4	5		T259	4		T347	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T154	6		T128	9		T246	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T301	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T127	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T173	4		T266	1		T264	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T139	18		T258	6		T172	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	12		T156	9		T114	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T127	6		T128	12		T118	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T31	5		T112	9		T258	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	13		T122	9		T144	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T15	11		T18	5		T151	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T237	9		T218	2		T119	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T19	12		T252	12		T191	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T118	5		T255	16		T297	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T123	2		T258	14		T126	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T9	2		T125	8		T146	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T143	9		T156	14		T117	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T18	5		T172	16		T120	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T111	9		T250	21		T270	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T123	12		T114	3		T194	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T7	8		T12	4		T14	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T122	12		T143	9		T117	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

auto[0]

3481

1

T4

5

T7

8

T9

14