Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26081

1

T1

2

T2

159

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22758

1

T1

2

T2

159

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3323

1

T4

13

T9

13

T10

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20618

1

T2

159

T5

1

T8

125

auto[1]

5463

1

T1

2

T3

1

T4

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21936

1

T1

2

T2

159

T3

1

auto[1]

4145

1

T4

7

T6

15

T9

30

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	239	1			T113	15		T167	1		T281	10
values[0]	96	1			T125	9		T173	10		T118	21
values[1]	545	1			T9	13		T111	10		T13	3
values[2]	607	1			T135	1		T112	10		T237	21
values[3]	627	1			T5	1		T16	4		T13	30
values[4]	710	1			T9	29		T12	17		T15	10
values[5]	637	1			T4	13		T9	2		T10	13
values[6]	774	1			T14	33		T239	1		T139	1
values[7]	811	1			T154	7		T111	23		T139	1
values[8]	2567	1			T1	2		T3	1		T6	17
values[9]	940	1			T15	21		T18	15		T239	1
minimum	17528	1			T2	159		T8	125		T9	173

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	535	1			T9	13		T13	2		T123	15
values[1]	781	1			T135	1		T13	30		T112	10
values[2]	501	1			T5	1		T9	29		T16	4
values[3]	723	1			T9	2		T12	17		T15	10
values[4]	645	1			T4	13		T10	13		T14	33
values[5]	866	1			T239	1		T111	23		T203	2
values[6]	2653	1			T1	2		T3	1		T6	17
values[7]	646	1			T18	20		T139	21		T123	13
values[8]	814	1			T15	21		T18	15		T239	1
values[9]	152	1			T116	17		T251	13		T332	1
minimum	17765	1			T2	159		T8	125		T9	173

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

3481

1

T4

5

T7

8

T9

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T151	10		T116	10		T117	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	5		T13	1		T123	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T135	1		T13	14		T112	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T113	1		T116	12		T146	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	1		T9	14		T16	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T16	1		T156	15		T259	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T9	1		T239	1		T31	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	5		T15	1		T122	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T14	14		T135	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T4	6		T10	1		T156	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T239	1		T111	10		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T203	1		T252	13		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1229	1			T1	2		T3	1		T6	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T154	7		T139	1		T123	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T139	19		T127	7		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T18	6		T123	1		T143	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T18	6		T239	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T15	12		T19	13		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T116	12		T332	1		T255	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T251	11		T48	1		T317	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17466	1			T2	159		T8	125		T9	167
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T13	1		T125	9		T218	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T151	12		T116	8		T117	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	8		T13	1		T123	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T13	16		T112	9		T237	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T113	18		T116	10		T282	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T9	15		T16	1		T218	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T16	1		T117	5		T194	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T9	1		T31	2		T237	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	12		T15	9		T122	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	19		T147	6		T246	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T4	7		T10	12		T117	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T111	13		T115	7		T240	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T203	1		T252	14		T118	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T6	15		T132	15		T122	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T123	8		T124	9		T128	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T139	2		T127	10		T247	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T18	14		T123	12		T143	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T18	9		T122	17		T144	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T15	9		T19	12		T143	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T116	5		T255	13		T352	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T251	2		T317	10		T305	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T9	6		T10	1		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T218	1		T173	5		T118	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T266	5		T255	17		T338	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T113	1		T167	1		T281	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T257	3		T346	18		T275	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T125	9		T173	5		T118	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T111	10		T151	10		T124	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T9	5		T13	2		T123	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T135	1		T112	1		T237	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T146	14		T129	1		T266	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	1		T16	1		T13	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	1		T113	1		T156	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T9	14		T112	10		T218	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	5		T15	1		T122	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T9	1		T239	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T4	6		T10	1		T156	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T14	14		T239	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T203	1		T155	1		T117	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T111	10		T141	1		T258	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T154	7		T139	1		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T1	2		T3	1		T6	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T18	6		T123	14		T258	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T18	6		T239	1		T139	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T15	12		T19	13		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17367	1			T2	159		T8	125		T9	167
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T255	13		T303	11		T280	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T113	14		T281	9		T251	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T257	8		T346	2		T324	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T173	5		T118	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T151	12		T116	8		T117	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T9	8		T13	1		T123	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T112	9		T237	11		T258	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T271	2		T279	13		T278	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T16	1		T13	16		T218	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T16	1		T113	18		T116	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	15		T218	1		T153	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	12		T15	9		T122	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T9	1		T31	2		T237	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T4	7		T10	12		T250	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	19		T115	7		T128	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T203	1		T117	4		T119	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T111	13		T258	7		T240	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T124	9		T252	14		T128	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T6	15		T132	15		T122	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T18	14		T123	20		T258	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T18	9		T139	2		T122	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T15	9		T19	12		T143	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T10	1		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T151	13		T116	9		T117	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	11		T13	2		T123	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T135	1		T13	17		T112	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T113	19		T116	11		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	1		T9	17		T16	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T16	2		T156	1		T259	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	2		T239	1		T31	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	13		T15	10		T122	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	25		T135	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T4	8		T10	13		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T239	1		T111	14		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T203	2		T252	15		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T1	2		T3	1		T6	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T154	1		T139	1		T123	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T139	3		T127	11		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T18	15		T123	13		T143	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T18	10		T239	1		T122	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T15	10		T19	13		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T116	6		T332	1		T255	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T251	3		T48	1		T317	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17619	1			T2	159		T8	125		T9	173
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T13	1		T125	1		T218	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T151	9		T116	9		T172	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T9	2		T123	2		T126	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	13		T237	9		T258	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T116	11		T146	13		T266	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T9	12		T112	9		T218	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T156	14		T259	10		T117	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T31	5		T237	4		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T12	4		T122	9		T347	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T14	8		T267	2		T246	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	5		T156	9		T114	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T111	9		T128	12		T120	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T252	12		T118	15		T119	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	904	1			T7	8		T17	8		T134	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T154	6		T123	12		T128	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T139	18		T127	6		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T18	5		T143	9		T258	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T18	5		T144	2		T119	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	11		T19	12		T143	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T116	11		T255	16		T212	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T251	10		T305	11		T353	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T111	9		T153	7		T270	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T125	8		T173	4		T118	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T266	1		T255	14		T338	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T113	15		T167	1		T281	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T257	9		T346	3		T275	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T125	1		T173	6		T118	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T111	1		T151	13		T124	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T9	11		T13	3		T123	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T135	1		T112	10		T237	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T146	1		T129	1		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	1		T16	2		T13	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	2		T113	19		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	17		T112	1		T218	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	13		T15	10		T122	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	2		T239	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	8		T10	13		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T14	25		T239	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T203	2		T155	1		T117	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T111	14		T141	1		T258	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T154	1		T139	1		T124	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T1	2		T3	1		T6	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T18	15		T123	22		T258	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T18	10		T239	1		T139	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T15	10		T19	13		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T2	159		T8	125		T9	173
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T266	4		T255	16		T303	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T251	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T257	2		T346	17		T275	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T125	8		T173	4		T118	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T111	9		T151	9		T116	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T9	2		T123	2		T126	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T237	9		T258	14		T247	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T146	13		T266	1		T271	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T13	13		T126	12		T119	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T156	14		T259	10		T116	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	12		T112	9		T218	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T12	4		T122	9		T347	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T31	5		T237	4		T128	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	5		T156	9		T114	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	8		T128	12		T267	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T117	6		T119	11		T148	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T111	9		T258	6		T120	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T154	6		T252	12		T128	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	891	1			T7	8		T17	8		T134	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T18	5		T123	12		T258	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T18	5		T139	18		T144	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T15	11		T19	12		T143	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

auto[0]

3481

1

T4

5

T7

8

T9

14