Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26081

1

T1

2

T2

159

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22681

1

T1

2

T2

159

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3400

1

T9

2

T12

17

T15

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20523

1

T2

159

T5

1

T8

125

auto[1]

5558

1

T1

2

T3

1

T4

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21936

1

T1

2

T2

159

T3

1

auto[1]

4145

1

T4

7

T6

15

T9

30

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	199	1			T154	7		T124	1		T143	22
values[0]	67	1			T4	13		T262	2		T46	3
values[1]	670	1			T239	1		T19	25		T13	30
values[2]	560	1			T9	29		T16	2		T13	2
values[3]	834	1			T9	13		T14	33		T15	10
values[4]	2663	1			T1	2		T3	1		T6	17
values[5]	721	1			T12	17		T111	33		T31	9
values[6]	680	1			T9	2		T15	21		T239	1
values[7]	687	1			T123	28		T258	22		T218	4
values[8]	610	1			T5	1		T18	35		T122	23
values[9]	862	1			T239	1		T139	1		T123	21
minimum	17528	1			T2	159		T8	125		T9	173

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	622	1			T239	1		T19	25		T13	30
values[1]	666	1			T9	29		T16	2		T135	1
values[2]	924	1			T9	13		T14	33		T15	10
values[3]	2456	1			T1	2		T3	1		T6	17
values[4]	700	1			T12	17		T111	33		T31	9
values[5]	706	1			T9	2		T15	21		T239	1
values[6]	742	1			T123	28		T258	22		T113	15
values[7]	566	1			T5	1		T18	35		T239	1
values[8]	778	1			T154	7		T139	1		T125	9
values[9]	157	1			T143	22		T258	21		T148	15
minimum	17764	1			T2	159		T4	13		T8	125

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

3481

1

T4

5

T7

8

T9

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T115	1		T153	1		T146	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T239	1		T19	13		T13	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	14		T16	1		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T135	1		T126	3		T240	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T9	5		T14	14		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T16	1		T135	1		T151	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1243	1			T1	2		T3	1		T6	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T218	3		T173	1		T242	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T111	20		T237	15		T145	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	5		T31	7		T282	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T191	4		T127	8		T172	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	1		T15	12		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T123	4		T115	1		T146	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T258	16		T113	1		T218	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T5	1		T18	6		T123	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T18	6		T239	1		T122	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T154	7		T203	1		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T139	1		T125	9		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T143	10		T326	1		T208	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T258	15		T148	15		T250	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17445	1			T2	159		T4	6		T8	125
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T112	10		T116	12		T129	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T115	11		T153	1		T250	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T19	12		T13	16		T112	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T9	15		T16	1		T13	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T240	10		T153	9		T247	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T9	8		T14	19		T15	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T16	1		T151	12		T113	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T6	15		T10	12		T132	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T218	1		T263	10		T327	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T111	13		T237	14		T116	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	12		T31	2		T282	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T191	7		T127	6		T250	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	1		T15	9		T265	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T123	24		T115	7		T251	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T258	6		T113	14		T218	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T18	9		T123	8		T124	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T18	14		T122	10		T143	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T203	1		T117	4		T247	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T128	8		T192	4		T246	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T143	12		T208	2		T74	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T258	6		T250	10		T163	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	7		T9	6		T10	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T116	5		T55	7		T220	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T154	7		T124	1		T143	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T258	15		T146	11		T250	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T4	6		T262	1		T46	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T55	1		T319	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T122	1		T144	1		T258	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T239	1		T19	13		T13	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T9	14		T16	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T141	1		T112	1		T126	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T9	5		T14	14		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T135	2		T113	1		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T1	2		T3	1		T6	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T16	1		T151	10		T218	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T111	20		T237	15		T145	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	5		T31	7		T242	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T191	4		T172	17		T173	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T9	1		T15	12		T239	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T123	4		T115	1		T127	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T258	16		T218	3		T128	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T5	1		T18	6		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T18	6		T122	13		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T123	13		T203	1		T117	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T239	1		T139	1		T125	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17367	1			T2	159		T8	125		T9	167
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T143	12		T208	2		T195	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T258	6		T250	10		T163	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T4	7		T262	1		T46	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T55	7		T319	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T122	17		T258	7		T113	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T19	12		T13	16		T116	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T9	15		T16	1		T13	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T112	9		T240	10		T153	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T9	8		T14	19		T15	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T113	13		T117	1		T119	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1070	1			T6	15		T10	12		T132	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T16	1		T151	12		T218	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T111	13		T237	14		T116	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	12		T31	2		T282	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T191	7		T173	5		T250	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	1		T15	9		T265	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T123	24		T115	7		T127	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T258	6		T218	1		T128	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T18	9		T124	9		T328	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T18	14		T122	10		T143	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T123	8		T203	1		T117	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T128	8		T192	4		T246	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T10	1		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T115	12		T153	2		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T239	1		T19	13		T13	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	17		T16	2		T13	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T135	1		T126	1		T240	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T9	11		T14	25		T15	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T16	2		T135	1		T151	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T1	2		T3	1		T6	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T218	4		T173	1		T242	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T111	15		T237	16		T145	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	13		T31	4		T282	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T191	8		T127	7		T172	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	2		T15	10		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T123	26		T115	8		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T258	7		T113	15		T218	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	1		T18	10		T123	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T18	15		T239	1		T122	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T154	1		T203	2		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T139	1		T125	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T143	13		T326	1		T208	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T258	7		T148	1		T250	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17622	1			T2	159		T4	8		T8	125
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T112	1		T116	6		T129	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T146	10		T250	8		T354	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T19	12		T13	13		T116	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T9	12		T144	2		T118	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T126	2		T153	2		T249	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T9	2		T14	8		T139	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T151	9		T126	12		T127	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	923	1			T7	8		T17	8		T134	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T242	8		T150	6		T327	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T111	18		T237	13		T116	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	4		T31	5		T248	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T191	3		T127	7		T172	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T15	11		T156	14		T114	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T123	2		T146	13		T120	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T258	15		T218	2		T128	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T18	5		T123	12		T117	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T18	5		T122	12		T143	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T154	6		T117	6		T247	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T125	8		T114	13		T128	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T143	9		T208	3		T74	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T258	14		T148	14		T250	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T4	5		T258	6		T259	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T112	9		T116	11		T220	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T154	1		T124	1		T143	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T258	7		T146	1		T250	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T4	8		T262	2		T46	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T55	8		T319	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T122	18		T144	1		T258	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T239	1		T19	13		T13	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	17		T16	2		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T141	1		T112	10		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T9	11		T14	25		T15	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T135	2		T113	14		T117	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T1	2		T3	1		T6	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T16	2		T151	13		T218	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T111	15		T237	16		T145	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	13		T31	4		T242	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T191	8		T172	1		T173	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	2		T15	10		T239	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T123	26		T115	8		T127	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T258	7		T218	2		T128	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T5	1		T18	10		T124	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T18	15		T122	11		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T123	9		T203	2		T117	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T239	1		T139	1		T125	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T2	159		T8	125		T9	173
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T154	6		T143	9		T208	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T258	14		T146	10		T250	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T4	5		T183	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T319	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T258	6		T259	10		T146	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T19	12		T13	13		T112	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T9	12		T144	2		T118	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T126	2		T153	2		T269	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	2		T14	8		T139	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T172	11		T119	8		T249	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T7	8		T17	8		T134	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T151	9		T126	12		T127	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T111	18		T237	13		T116	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	4		T31	5		T242	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T191	3		T172	16		T173	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T15	11		T156	14		T114	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T123	2		T127	7		T146	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T258	15		T218	2		T128	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T18	5		T120	5		T267	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T18	5		T122	12		T143	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T123	12		T117	8		T247	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T125	8		T114	13		T128	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

auto[0]

3481

1

T4

5

T7

8

T9

14