Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26081

1

T1

2

T2

159

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22801

1

T1

2

T2

159

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3280

1

T5

1

T9

31

T12

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20494

1

T2

159

T8

125

T9

173

auto[1]

5587

1

T1

2

T3

1

T4

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21936

1

T1

2

T2

159

T3

1

auto[1]

4145

1

T4

7

T6

15

T9

30

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	299	1			T118	21		T119	11		T120	6
values[0]	97	1			T9	13		T240	12		T277	15
values[1]	663	1			T16	2		T239	2		T111	10
values[2]	2707	1			T1	2		T3	1		T6	17
values[3]	595	1			T122	23		T112	10		T113	14
values[4]	528	1			T9	29		T15	10		T16	2
values[5]	897	1			T10	13		T14	33		T18	20
values[6]	661	1			T5	1		T12	17		T15	21
values[7]	468	1			T111	23		T139	22		T123	21
values[8]	607	1			T4	13		T13	31		T123	13
values[9]	1031	1			T9	2		T239	1		T203	2
minimum	17528	1			T2	159		T8	125		T9	173

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	673	1			T9	13		T16	2		T239	2
values[1]	2871	1			T1	2		T3	1		T6	17
values[2]	463	1			T145	1		T117	11		T127	17
values[3]	553	1			T9	29		T15	10		T16	2
values[4]	870	1			T10	13		T14	33		T18	20
values[5]	632	1			T5	1		T12	17		T15	21
values[6]	503	1			T111	23		T139	22		T13	30
values[7]	642	1			T4	13		T239	1		T13	1
values[8]	998	1			T9	2		T155	1		T156	10
values[9]	146	1			T203	2		T116	22		T128	18
minimum	17730	1			T2	159		T8	125		T9	173

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

3481

1

T4

5

T7

8

T9

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	5		T16	1		T239	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T135	1		T122	1		T258	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T1	2		T3	1		T6	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	1		T122	13		T112	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T145	1		T127	7		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T117	7		T242	10		T332	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T16	1		T139	1		T144	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	14		T15	1		T122	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T10	1		T14	14		T125	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T18	6		T154	7		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T15	12		T18	6		T123	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	1		T12	5		T19	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T111	10		T139	20		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T13	14		T123	1		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	6		T141	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T239	1		T13	1		T151	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T126	3		T115	1		T259	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T9	1		T155	1		T156	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T203	1		T120	6		T251	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T116	12		T128	10		T355	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17420	1			T2	159		T8	125		T9	167
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T31	7		T277	1		T334	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	8		T16	1		T116	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T122	17		T258	6		T113	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1140	1			T6	15		T132	15		T207	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	1		T122	10		T128	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T127	10		T246	2		T24	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T117	4		T217	5		T283	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T16	1		T144	2		T237	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T9	15		T15	9		T122	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T10	12		T14	19		T115	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T18	14		T251	2		T262	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T15	9		T18	9		T123	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	12		T19	12		T123	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T111	13		T139	2		T112	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	16		T123	12		T171	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T4	7		T262	4		T55	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T151	12		T192	4		T287	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T115	11		T240	9		T153	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T9	1		T173	5		T119	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T203	1		T251	10		T356	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T116	10		T128	8		T180	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T9	6		T10	1		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T31	2		T277	14		T357	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T118	11		T120	6		T251	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T119	9		T254	9		T295	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T9	5		T240	1		T306	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T277	1		T74	6		T336	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T16	1		T239	2		T111	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T135	1		T122	1		T31	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T1	2		T3	1		T6	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	1		T144	1		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T113	1		T145	1		T127	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T122	13		T112	10		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T16	1		T139	1		T144	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	14		T15	1		T122	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T10	1		T14	14		T125	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T18	6		T154	7		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	12		T18	6		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	1		T12	5		T19	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T111	10		T139	20		T123	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T171	1		T148	4		T250	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	6		T141	1		T150	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	15		T123	1		T151	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T203	1		T126	3		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T9	1		T239	1		T155	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17367	1			T2	159		T8	125		T9	167
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T118	10		T251	10		T279	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T119	2		T254	8		T295	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T9	8		T240	11		T306	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T277	14		T336	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T16	1		T124	9		T143	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T122	17		T31	2		T258	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1087	1			T6	15		T132	15		T207	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	1		T113	14		T218	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T113	13		T127	10		T247	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T122	10		T117	4		T265	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T16	1		T144	2		T237	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	15		T15	9		T122	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T10	12		T14	19		T258	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T18	14		T143	9		T252	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T15	9		T18	9		T117	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	12		T19	12		T123	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T111	13		T139	2		T123	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T171	1		T250	9		T282	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T4	7		T255	13		T55	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	16		T123	12		T151	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T203	1		T115	11		T240	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T9	1		T116	10		T128	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T10	1		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T9	11		T16	2		T239	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T135	1		T122	18		T258	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1488	1			T1	2		T3	1		T6	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T13	2		T122	11		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T145	1		T127	11		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T117	5		T242	1		T332	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T16	2		T139	1		T144	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T9	17		T15	10		T122	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T10	13		T14	25		T125	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T18	15		T154	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T15	10		T18	10		T123	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	1		T12	13		T19	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T111	14		T139	4		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	17		T123	13		T171	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T4	8		T141	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T239	1		T13	1		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T126	1		T115	12		T259	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T9	2		T155	1		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T203	2		T120	1		T251	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T116	11		T128	9		T355	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17614	1			T2	159		T8	125		T9	173
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T31	4		T277	15		T334	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T9	2		T116	11		T274	23
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T258	15		T116	9		T128	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T7	8		T17	8		T134	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T122	12		T112	9		T128	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T127	6		T246	2		T24	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T117	6		T242	9		T217	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T144	2		T237	4		T258	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	12		T122	9		T143	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T14	8		T125	8		T127	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T18	5		T154	6		T172	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T15	11		T18	5		T123	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	4		T19	12		T123	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T111	9		T139	18		T191	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T13	13		T148	3		T250	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T4	5		T262	5		T150	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T151	9		T126	12		T259	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T126	2		T259	4		T153	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T156	9		T114	16		T173	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T120	5		T251	9		T337	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T116	11		T128	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T111	9		T143	9		T301	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T31	5		T357	8		T275	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T118	11		T120	1		T251	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T119	3		T254	9		T295	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T9	11		T240	12		T306	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T277	15		T74	4		T336	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T16	2		T239	2		T111	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T135	1		T122	18		T31	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1426	1			T1	2		T3	1		T6	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	2		T144	1		T113	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T113	14		T145	1		T127	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T122	11		T112	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T16	2		T139	1		T144	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	17		T15	10		T122	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T10	13		T14	25		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T18	15		T154	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	10		T18	10		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	1		T12	13		T19	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T111	14		T139	4		T123	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T171	2		T148	1		T250	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T4	8		T141	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	18		T123	13		T151	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T203	2		T126	1		T115	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T9	2		T239	1		T155	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T2	159		T8	125		T9	173
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T118	10		T120	5		T251	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T119	8		T254	8		T295	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T9	2		T335	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T74	2		T158	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T111	9		T143	9		T116	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T31	5		T258	15		T116	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T7	8		T17	8		T134	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T128	8		T148	15		T246	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T127	6		T247	11		T249	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T122	12		T112	9		T117	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T144	2		T237	4		T258	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T9	12		T122	9		T237	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T14	8		T125	8		T258	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T18	5		T154	6		T143	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T15	11		T18	5		T118	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	4		T19	12		T123	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T111	9		T139	18		T123	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T148	3		T250	8		T269	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T4	5		T150	6		T62	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	13		T151	9		T126	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T126	2		T259	4		T153	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T156	9		T114	16		T116	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

auto[0]

3481

1

T4

5

T7

8

T9

14