Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T9	2		T135	1		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	1		T14	25		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T18	10		T239	1		T13	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T139	1		T13	1		T151	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	13		T124	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T239	1		T111	14		T122	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T1	2		T3	1		T6	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T16	2		T141	1		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T9	17		T16	2		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T19	13		T123	13		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T139	3		T144	1		T259	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T15	10		T123	13		T203	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T111	1		T156	1		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T113	14		T259	1		T193	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T4	8		T9	11		T10	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T112	1		T172	1		T119	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T123	9		T252	15		T237	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T139	1		T122	18		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T13	2		T173	1		T192	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T154	1		T115	8		T266	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17538	1			T2	159		T8	125		T9	173
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T272	13		T275	1		T276	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T143	9		T144	2		T191	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T14	8		T125	8		T116	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T18	5		T13	13		T153	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T151	9		T218	2		T118	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T12	4		T127	7		T284	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T111	9		T122	12		T258	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	893	1			T7	8		T17	8		T134	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T156	14		T24	2		T268	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	12		T258	15		T116	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T19	12		T31	5		T172	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T139	18		T259	10		T117	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T123	2		T143	9		T258	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T111	9		T156	9		T114	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T259	4		T193	9		T270	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T4	5		T9	2		T15	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T112	9		T172	11		T119	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T123	12		T252	12		T237	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T237	4		T128	8		T250	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T279	4		T272	12		T285	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T154	6		T266	1		T257	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T114	13		T286	23		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T272	11		T275	10		T276	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T221	4		T163	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T159	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T275	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	2		T141	1		T144	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	1		T115	12		T240	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T239	1		T135	1		T13	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	25		T125	1		T151	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T18	10		T124	1		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T239	1		T111	14		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	13		T239	1		T122	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T16	2		T141	1		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T1	2		T3	1		T6	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T19	13		T123	13		T31	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T139	3		T112	10		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T15	10		T123	13		T203	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T111	1		T156	1		T173	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T259	1		T127	11		T242	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	8		T9	11		T15	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T112	1		T113	14		T119	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	379	1			T10	13		T13	2		T123	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T154	1		T139	1		T122	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T2	159		T8	125		T9	173
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T163	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T275	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T144	2		T114	13		T116	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T116	11		T279	3		T272	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	13		T143	9		T191	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	8		T125	8		T151	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T18	5		T148	15		T284	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T111	9		T122	12		T258	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	4		T122	9		T127	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T156	14		T24	2		T268	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T7	8		T9	12		T17	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T19	12		T31	5		T128	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T139	18		T114	3		T259	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T123	2		T143	9		T258	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T111	9		T156	9		T173	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T259	4		T127	6		T242	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	5		T9	2		T15	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T112	9		T119	11		T120	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T123	12		T252	12		T237	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T154	6		T237	4		T172	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

auto[0]

3481

1

T4

5

T7

8

T9

14