Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26081

1

T1

2

T2

159

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22810

1

T1

2

T2

159

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3271

1

T5

1

T9

44

T10

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20072

1

T2

157

T8

124

T9

185

auto[1]

6009

1

T1

2

T2

2

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21936

1

T1

2

T2

159

T3

1

auto[1]

4145

1

T4

7

T6

15

T9

30

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	441	1			T2	2		T8	1		T9	3
values[0]	45	1			T135	1		T123	21		T165	23
values[1]	604	1			T15	21		T111	23		T139	1
values[2]	2633	1			T1	2		T3	1		T5	1
values[3]	667	1			T19	25		T154	7		T122	18
values[4]	777	1			T18	15		T111	10		T122	23
values[5]	749	1			T15	10		T239	1		T139	21
values[6]	593	1			T9	13		T14	33		T13	30
values[7]	688	1			T4	13		T12	17		T239	1
values[8]	540	1			T16	4		T18	20		T135	1
values[9]	1247	1			T9	31		T10	13		T13	2
minimum	17097	1			T2	157		T8	124		T9	170

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	773	1			T5	1		T111	23		T135	1
values[1]	2601	1			T1	2		T3	1		T6	17
values[2]	613	1			T125	9		T151	22		T143	19
values[3]	810	1			T15	10		T18	15		T111	10
values[4]	816	1			T239	1		T139	21		T141	1
values[5]	605	1			T9	13		T14	33		T13	30
values[6]	608	1			T4	13		T12	17		T239	1
values[7]	671	1			T16	4		T203	2		T31	9
values[8]	855	1			T9	2		T18	20		T13	2
values[9]	186	1			T9	29		T10	13		T287	14
minimum	17543	1			T2	159		T8	125		T9	173

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

3481

1

T4

5

T7

8

T9

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T115	1		T240	1		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	1		T111	10		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T1	2		T3	1		T6	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T15	12		T239	1		T154	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T125	9		T143	10		T112	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T151	10		T114	4		T240	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T18	6		T111	10		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T15	1		T122	13		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T239	1		T139	19		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T112	1		T258	16		T116	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	14		T124	1		T258	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T9	5		T13	14		T123	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	6		T12	5		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T239	1		T124	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T16	1		T203	1		T144	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	1		T31	7		T258	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T122	10		T123	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T9	1		T18	6		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T56	4		T288	1		T198	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T9	14		T10	1		T287	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17367	1			T2	159		T8	125		T9	167
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T289	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T115	7		T240	9		T153	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T111	13		T123	8		T173	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T6	15		T19	12		T132	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T15	9		T118	6		T268	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T143	9		T218	1		T290	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T151	12		T240	10		T282	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T18	9		T122	17		T237	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T15	9		T122	10		T113	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T139	2		T113	13		T218	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T112	9		T258	6		T116	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	19		T124	9		T258	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T9	8		T13	16		T123	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	7		T12	12		T252	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T113	14		T115	11		T247	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T16	1		T203	1		T144	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T16	1		T31	2		T258	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T122	6		T123	12		T143	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T9	1		T18	14		T13	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T56	1		T291	14		T292	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T9	15		T10	12		T287	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T10	1		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T289	3		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	437	1			T2	2		T8	1		T9	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T293	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T135	1		T123	13		T165	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T153	1		T173	1		T269	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T15	12		T111	10		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T1	2		T3	1		T6	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	1		T239	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T19	13		T122	1		T125	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T154	7		T151	10		T126	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T18	6		T111	10		T237	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T122	13		T142	1		T258	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T239	1		T139	19		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	1		T112	1		T116	34
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T14	14		T191	4		T128	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	5		T13	14		T123	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T4	6		T12	5		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T239	1		T124	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T16	1		T135	1		T117	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T16	1		T18	6		T31	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T122	10		T123	1		T203	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	419	1			T9	15		T10	1		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16936	1			T2	157		T8	124		T9	164
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T265	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T123	8		T165	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T153	1		T294	4		T295	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T15	9		T111	13		T173	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1054	1			T6	15		T132	15		T207	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T118	6		T263	10		T217	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T19	12		T122	17		T143	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T151	12		T240	10		T282	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T18	9		T237	3		T218	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T122	10		T258	6		T113	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T139	2		T113	13		T218	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T15	9		T112	9		T116	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T14	19		T191	7		T128	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T9	8		T13	16		T123	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T4	7		T12	12		T124	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T113	14		T115	11		T247	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T16	1		T117	9		T173	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T16	1		T18	14		T31	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T122	6		T123	12		T203	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T9	16		T10	12		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T10	1		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T115	8		T240	10		T153	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T5	1		T111	14		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T1	2		T3	1		T6	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T15	10		T239	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T125	1		T143	10		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T151	13		T114	1		T240	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T18	10		T111	1		T122	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T15	10		T122	11		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T239	1		T139	3		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T112	10		T258	7		T116	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T14	25		T124	10		T258	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T9	11		T13	17		T123	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T4	8		T12	13		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T239	1		T124	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T16	2		T203	2		T144	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T16	2		T31	4		T258	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T122	7		T123	13		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T9	2		T18	15		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T56	4		T288	1		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T9	17		T10	13		T287	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T2	159		T8	125		T9	173
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T289	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T119	7		T269	11		T294	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T111	9		T123	12		T173	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T7	8		T17	8		T19	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T15	11		T154	6		T126	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T125	8		T143	9		T112	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T151	9		T114	3		T279	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T18	5		T111	9		T237	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T122	12		T116	11		T146	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T139	18		T218	2		T128	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T258	15		T116	20		T127	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T14	8		T258	14		T191	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T9	2		T13	13		T123	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T4	5		T12	4		T252	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T247	19		T266	1		T270	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T144	2		T117	8		T173	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T31	5		T258	6		T156	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T122	9		T143	9		T156	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T18	5		T172	11		T128	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T56	1		T198	9		T291	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T9	12		T286	12		T296	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T289	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	434	1			T2	2		T8	1		T9	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T293	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T135	1		T123	9		T165	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T153	2		T173	1		T269	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T15	10		T111	14		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T1	2		T3	1		T6	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	1		T239	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T19	13		T122	18		T125	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T154	1		T151	13		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T18	10		T111	1		T237	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T122	11		T142	1		T258	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T239	1		T139	3		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T15	10		T112	10		T116	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T14	25		T191	8		T128	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T9	11		T13	17		T123	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	8		T12	13		T124	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T239	1		T124	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T16	2		T135	1		T117	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T16	2		T18	15		T31	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T122	7		T123	13		T203	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	377	1			T9	19		T10	13		T13	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17097	1			T2	157		T8	124		T9	170
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T297	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T293	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T123	12		T165	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T269	11		T294	5		T295	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T15	11		T111	9		T173	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	959	1			T7	8		T17	8		T134	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T118	5		T217	5		T298	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T19	12		T125	8		T143	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T154	6		T151	9		T126	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T18	5		T111	9		T237	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T122	12		T258	15		T114	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T139	18		T218	2		T126	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T116	31		T127	6		T146	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	8		T191	3		T128	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T9	2		T13	13		T123	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	5		T12	4		T252	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T247	11		T266	1		T268	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T117	8		T173	4		T118	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T18	5		T31	5		T247	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T122	9		T143	9		T144	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T9	12		T258	6		T156	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

auto[0]

3481

1

T4

5

T7

8

T9

14