Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26081

1

T1

2

T2

159

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22570

1

T1

2

T2

159

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3511

1

T5

1

T9

31

T15

31

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20409

1

T2

159

T8

125

T9

188

auto[1]

5672

1

T1

2

T3

1

T4

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21936

1

T1

2

T2

159

T3

1

auto[1]

4145

1

T4

7

T6

15

T9

30

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	8	1			T117	8		-	-		-	-
values[0]	36	1			T218	4		T299	1		T217	23
values[1]	626	1			T111	10		T135	1		T203	2
values[2]	723	1			T139	21		T141	1		T112	10
values[3]	524	1			T15	10		T13	1		T31	9
values[4]	988	1			T14	33		T18	15		T19	25
values[5]	2659	1			T1	2		T3	1		T6	17
values[6]	531	1			T4	13		T16	2		T139	1
values[7]	739	1			T9	2		T111	23		T122	41
values[8]	629	1			T10	13		T12	17		T239	1
values[9]	1090	1			T5	1		T9	13		T15	21
minimum	17528	1			T2	159		T8	125		T9	173

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	770	1			T111	10		T135	1		T203	2
values[1]	781	1			T15	10		T141	1		T112	10
values[2]	583	1			T18	15		T139	21		T13	1
values[3]	2960	1			T1	2		T3	1		T6	17
values[4]	565	1			T9	29		T16	2		T18	20
values[5]	515	1			T4	13		T9	2		T16	2
values[6]	743	1			T111	23		T122	41		T237	21
values[7]	613	1			T10	13		T12	17		T239	1
values[8]	700	1			T5	1		T15	21		T239	2
values[9]	304	1			T9	13		T124	10		T113	15
minimum	17547	1			T2	159		T8	125		T9	173

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

3481

1

T4

5

T7

8

T9

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T111	10		T203	1		T173	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T135	1		T191	4		T218	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T141	1		T127	8		T269	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T15	1		T112	10		T259	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T18	6		T31	7		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T139	19		T13	1		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T1	2		T3	1		T6	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T19	13		T125	9		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	1		T112	1		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	14		T16	1		T18	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T4	6		T139	1		T143	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T9	1		T16	1		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T122	1		T113	1		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T111	10		T122	13		T237	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	1		T12	5		T123	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T239	1		T252	13		T156	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T239	1		T154	7		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T5	1		T15	12		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T9	5		T124	1		T156	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T113	1		T169	1		T283	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17368	1			T2	159		T8	125		T9	167
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T295	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T203	1		T173	10		T192	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T191	7		T218	1		T240	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T127	6		T251	2		T279	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T15	9		T118	10		T283	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T18	9		T31	2		T147	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T139	2		T123	12		T247	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1139	1			T6	15		T14	19		T132	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T19	12		T115	11		T117	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T13	1		T112	9		T115	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	15		T16	1		T18	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T4	7		T143	9		T116	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	1		T16	1		T250	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T122	17		T113	13		T282	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T111	13		T122	10		T237	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	12		T12	12		T123	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T252	14		T240	9		T116	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T122	6		T144	2		T218	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	9		T13	16		T258	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T9	8		T124	9		T300	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T113	14		T283	1		T301	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T10	1		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T295	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T117	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T299	1		T197	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T218	3		T217	11		T302	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T111	10		T203	1		T127	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T135	1		T191	4		T241	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T141	1		T192	1		T250	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T139	19		T112	10		T259	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T31	7		T269	12		T251	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T15	1		T13	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T14	14		T18	6		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T19	13		T123	1		T259	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T1	2		T3	1		T6	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	14		T16	1		T18	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	6		T139	1		T143	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T16	1		T151	10		T250	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T122	1		T123	3		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	1		T111	10		T122	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T10	1		T12	5		T154	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T239	1		T252	13		T156	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T9	5		T239	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T5	1		T15	12		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17367	1			T2	159		T8	125		T9	167
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T117	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T197	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T218	1		T217	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T203	1		T127	6		T173	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T191	7		T240	11		T249	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T192	4		T250	10		T281	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T139	2		T117	1		T171	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T31	2		T251	2		T279	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T15	9		T247	14		T119	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T14	19		T18	9		T173	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T19	12		T123	12		T247	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T6	15		T132	15		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T9	15		T16	1		T18	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T4	7		T143	9		T116	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T16	1		T151	12		T250	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T122	17		T123	12		T113	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	1		T111	13		T122	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T10	12		T12	12		T237	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T252	14		T116	10		T119	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T9	8		T122	6		T123	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T15	9		T13	16		T258	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T10	1		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T111	1		T203	2		T173	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T135	1		T191	8		T218	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T141	1		T127	7		T269	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T15	10		T112	1		T259	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T18	10		T31	4		T147	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T139	3		T13	1		T123	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1493	1			T1	2		T3	1		T6	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T19	13		T125	1		T115	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	2		T112	10		T115	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	17		T16	2		T18	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T4	8		T139	1		T143	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T9	2		T16	2		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T122	18		T113	14		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T111	14		T122	11		T237	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T10	13		T12	13		T123	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T239	1		T252	15		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T239	1		T154	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	1		T15	10		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T9	11		T124	10		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T113	15		T169	1		T283	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17529	1			T2	159		T8	125		T9	173
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T295	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T111	9		T173	4		T250	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T191	3		T118	5		T267	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T127	7		T269	12		T251	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T112	9		T259	4		T118	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T18	5		T31	5		T269	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T139	18		T172	11		T119	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	994	1			T7	8		T14	8		T17	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T19	12		T125	8		T259	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T242	8		T246	11		T303	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T9	12		T18	5		T151	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T4	5		T143	9		T126	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T250	8		T266	1		T193	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T24	2		T279	11		T304	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T111	9		T122	12		T237	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	4		T123	14		T237	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T252	12		T156	14		T116	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T154	6		T122	9		T144	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T15	11		T13	13		T258	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T9	2		T156	9		T74	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T301	12		T57	3		T305	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T295	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T117	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T299	1		T197	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T218	4		T217	13		T302	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T111	1		T203	2		T127	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T135	1		T191	8		T241	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T141	1		T192	5		T250	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T139	3		T112	1		T259	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T31	4		T269	1		T251	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T15	10		T13	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T14	25		T18	10		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T19	13		T123	13		T259	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T1	2		T3	1		T6	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T9	17		T16	2		T18	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T4	8		T139	1		T143	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T16	2		T151	13		T250	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T122	18		T123	13		T113	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T9	2		T111	14		T122	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	13		T12	13		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T239	1		T252	15		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T9	11		T239	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T5	1		T15	10		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T2	159		T8	125		T9	173
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T117	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T217	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T111	9		T127	7		T173	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T191	3		T249	11		T246	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T250	2		T269	12		T150	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T139	18		T112	9		T259	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T31	5		T269	11		T251	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T172	11		T119	8		T246	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T14	8		T18	5		T173	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T19	12		T259	10		T247	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	901	1			T7	8		T17	8		T134	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	12		T18	5		T125	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T4	5		T143	9		T126	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T151	9		T250	8		T248	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T123	2		T279	11		T284	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T111	9		T122	12		T237	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T12	4		T154	6		T237	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T252	12		T156	14		T116	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	2		T122	9		T123	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T15	11		T13	13		T258	20

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

auto[0]

3481

1

T4

5

T7

8

T9

14