Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26081

1

T1

2

T2

159

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23018

1

T1

2

T2

159

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3063

1

T9

13

T10

13

T15

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20772

1

T2

159

T4

13

T5

1

auto[1]

5309

1

T1

2

T3

1

T6

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21936

1

T1

2

T2

159

T3

1

auto[1]

4145

1

T4

7

T6

15

T9

30

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	55	1			T254	17		T306	1		T307	29
values[0]	29	1			T203	2		T308	1		T59	7
values[1]	616	1			T15	10		T135	2		T139	21
values[2]	647	1			T9	29		T141	2		T156	10
values[3]	682	1			T13	30		T122	16		T31	9
values[4]	776	1			T15	21		T16	4		T18	15
values[5]	489	1			T19	25		T191	11		T113	14
values[6]	614	1			T9	13		T139	2		T123	28
values[7]	543	1			T9	2		T239	1		T142	1
values[8]	657	1			T18	20		T111	10		T123	21
values[9]	3445	1			T1	2		T3	1		T4	13
minimum	17528	1			T2	159		T8	125		T9	173

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	918	1			T9	29		T15	10		T135	2
values[1]	449	1			T112	10		T114	14		T127	17
values[2]	790	1			T16	2		T13	30		T122	16
values[3]	684	1			T15	21		T16	2		T18	15
values[4]	554	1			T9	13		T19	25		T139	1
values[5]	580	1			T9	2		T139	1		T123	28
values[6]	2633	1			T1	2		T3	1		T6	17
values[7]	746	1			T239	1		T111	23		T113	34
values[8]	1004	1			T4	13		T5	1		T10	13
values[9]	195	1			T12	17		T153	2		T128	17
minimum	17528	1			T2	159		T8	125		T9	173

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

3481

1

T4

5

T7

8

T9

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T9	14		T135	1		T139	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T15	1		T135	1		T203	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T114	14		T309	1		T130	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T112	10		T127	7		T128	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T16	1		T31	7		T258	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	14		T122	10		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T15	12		T16	1		T18	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T112	1		T237	10		T218	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T19	13		T139	1		T252	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T9	5		T125	9		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	1		T123	3		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T139	1		T123	1		T172	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T1	2		T3	1		T6	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T18	6		T123	13		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T111	10		T113	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T239	1		T113	1		T114	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T4	6		T5	1		T14	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T10	1		T154	7		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T12	5		T153	1		T300	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T128	9		T248	1		T254	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17367	1			T2	159		T8	125		T9	167
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	15		T139	2		T122	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T15	9		T203	1		T258	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T130	2		T176	7		T310	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T127	10		T128	10		T118	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T16	1		T31	2		T258	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	16		T122	6		T144	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T15	9		T16	1		T18	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T112	9		T237	11		T218	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T19	12		T252	14		T258	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	8		T124	9		T118	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	1		T123	12		T113	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T123	12		T130	13		T279	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1086	1			T6	15		T132	15		T207	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T18	14		T123	8		T153	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T111	13		T113	18		T287	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T113	14		T240	20		T131	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T4	7		T14	19		T122	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T10	12		T13	1		T143	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T12	12		T153	1		T300	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T128	8		T254	8		T311	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T10	1		T14	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T307	14		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T254	9		T306	1		T280	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T59	5		T312	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T203	1		T308	1		T313	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T135	1		T139	19		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T15	1		T135	1		T258	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	14		T156	10		T114	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T141	2		T240	1		T128	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T31	7		T258	16		T242	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	14		T122	10		T112	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T15	12		T16	2		T18	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T124	2		T112	1		T144	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T19	13		T191	4		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T115	1		T118	6		T255	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T139	1		T123	3		T252	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T9	5		T139	1		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	1		T239	1		T143	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T142	1		T153	8		T172	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T111	10		T145	1		T115	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T18	6		T123	13		T114	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1530	1			T1	2		T3	1		T4	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T10	1		T239	1		T154	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17367	1			T2	159		T8	125		T9	167
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T307	15		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T254	8		T280	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T59	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T203	1		T313	2		T314	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T139	2		T122	17		T173	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T15	9		T258	7		T127	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T9	15		T119	3		T130	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T240	10		T128	10		T118	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T31	2		T258	6		T271	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	16		T122	6		T116	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T15	9		T16	2		T18	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T124	9		T112	9		T144	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T19	12		T191	7		T113	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T115	7		T118	6		T255	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T123	12		T252	14		T258	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T9	8		T123	12		T279	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	1		T143	9		T117	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T153	5		T130	13		T209	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T115	11		T250	25		T287	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T18	14		T123	8		T240	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T4	7		T6	15		T12	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T10	12		T13	1		T143	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T10	1		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T9	17		T135	1		T139	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T15	10		T135	1		T203	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T114	1		T309	1		T130	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T112	1		T127	11		T128	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T16	2		T31	4		T258	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	17		T122	7		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T15	10		T16	2		T18	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T112	10		T237	12		T218	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T19	13		T139	1		T252	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T9	11		T125	1		T124	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	2		T123	13		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T139	1		T123	13		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1425	1			T1	2		T3	1		T6	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T18	15		T123	9		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T111	14		T113	19		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T239	1		T113	15		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T4	8		T5	1		T14	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T10	13		T154	1		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T12	13		T153	2		T300	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T128	9		T248	1		T254	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T2	159		T8	125		T9	173
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T9	12		T139	18		T156	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T258	6		T127	7		T172	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T114	13		T130	10		T242	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T112	9		T127	6		T128	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T31	5		T258	15		T119	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	13		T122	9		T144	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T15	11		T18	5		T151	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T237	9		T218	2		T119	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T19	12		T252	12		T258	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T9	2		T125	8		T118	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T123	2		T126	2		T148	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T172	16		T146	23		T120	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	947	1			T7	8		T17	8		T111	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T18	5		T123	12		T153	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T111	9		T120	4		T270	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T114	3		T267	13		T211	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T4	5		T14	8		T122	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T154	6		T143	9		T117	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T12	4		T210	3		T290	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T128	8		T254	8		T260	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T307	16		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T254	9		T306	1		T280	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T59	6		T312	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T203	2		T308	1		T313	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T135	1		T139	3		T122	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	10		T135	1		T258	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T9	17		T156	1		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T141	2		T240	11		T128	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T31	4		T258	7		T242	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	17		T122	7		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T15	10		T16	4		T18	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T124	11		T112	10		T144	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T19	13		T191	8		T113	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T115	8		T118	7		T255	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T139	1		T123	13		T252	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	11		T139	1		T123	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	2		T239	1		T143	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T142	1		T153	6		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T111	1		T145	1		T115	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T18	15		T123	9		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1651	1			T1	2		T3	1		T4	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	444	1			T10	13		T239	1		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T2	159		T8	125		T9	173
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T307	13		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T254	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T59	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T139	18		T173	4		T266	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T258	6		T127	13		T172	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	12		T156	9		T114	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T128	12		T118	15		T148	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T31	5		T258	15		T242	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T13	13		T122	9		T112	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	11		T18	5		T151	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T144	2		T237	9		T218	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T19	12		T191	3		T259	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T118	5		T255	16		T297	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T123	2		T252	12		T258	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T9	2		T125	8		T146	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T143	9		T156	14		T117	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T153	7		T172	16		T120	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T111	9		T250	21		T270	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T18	5		T123	12		T114	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1141	1			T4	5		T7	8		T12	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T154	6		T143	9		T117	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

auto[0]

3481

1

T4

5

T7

8

T9

14