Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26081

1

T1

2

T2

159

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22594

1

T1

2

T2

159

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3487

1

T5

1

T9

31

T15

31

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20415

1

T2

159

T8

125

T9

188

auto[1]

5666

1

T1

2

T3

1

T4

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21936

1

T1

2

T2

159

T3

1

auto[1]

4145

1

T4

7

T6

15

T9

30

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	271	1			T9	13		T15	21		T13	30
values[0]	5	1			T218	4		T299	1		-	-
values[1]	650	1			T111	10		T135	1		T203	2
values[2]	721	1			T15	10		T139	21		T141	1
values[3]	545	1			T13	1		T31	9		T145	1
values[4]	952	1			T9	29		T14	33		T18	15
values[5]	2687	1			T1	2		T3	1		T6	17
values[6]	516	1			T4	13		T16	2		T139	1
values[7]	782	1			T9	2		T111	23		T122	41
values[8]	628	1			T10	13		T12	17		T239	1
values[9]	796	1			T5	1		T239	2		T154	7
minimum	17528	1			T2	159		T8	125		T9	173

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	555	1			T111	10		T191	11		T241	1
values[1]	820	1			T15	10		T135	1		T139	21
values[2]	517	1			T13	1		T123	13		T31	9
values[3]	2944	1			T1	2		T3	1		T6	17
values[4]	562	1			T16	2		T18	20		T19	25
values[5]	601	1			T4	13		T16	2		T111	23
values[6]	726	1			T9	2		T122	41		T237	21
values[7]	593	1			T10	13		T12	17		T239	1
values[8]	805	1			T5	1		T15	21		T239	2
values[9]	199	1			T9	13		T124	10		T156	10
minimum	17759	1			T2	159		T8	125		T9	173

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

3481

1

T4

5

T7

8

T9

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T241	1		T127	8		T192	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T111	10		T191	4		T117	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T135	1		T141	1		T315	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T15	1		T139	19		T112	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	1		T31	7		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T123	1		T145	1		T172	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T1	2		T3	1		T6	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T9	14		T115	1		T117	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	1		T112	1		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T16	1		T18	6		T19	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T4	6		T116	10		T128	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T16	1		T111	10		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T122	1		T113	1		T148	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	1		T122	13		T237	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T10	1		T12	5		T123	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T239	1		T252	13		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T239	1		T154	7		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T5	1		T15	12		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T9	5		T124	1		T156	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T169	1		T316	1		T162	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17440	1			T2	159		T8	125		T9	167
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T218	3		T240	1		T299	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T127	6		T192	4		T250	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T191	7		T117	1		T171	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T251	2		T279	13		T210	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T15	9		T139	2		T118	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T31	2		T147	6		T246	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T123	12		T247	14		T119	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1144	1			T6	15		T14	19		T18	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	15		T115	11		T117	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	1		T112	9		T115	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T16	1		T18	14		T19	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T4	7		T116	8		T128	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T16	1		T111	13		T143	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T122	17		T113	13		T24	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	1		T122	10		T237	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T10	12		T12	12		T123	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T252	14		T240	9		T116	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T122	6		T144	2		T258	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T15	9		T13	16		T258	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T9	8		T124	9		T283	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T57	8		T317	2		T318	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	6		T10	1		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T218	1		T240	11		T63	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T9	5		T124	1		T240	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T15	12		T13	14		T218	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T218	3		T299	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T135	1		T203	1		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T111	10		T191	4		T240	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T141	1		T192	1		T250	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T15	1		T139	19		T112	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	1		T31	7		T269	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T145	1		T172	12		T247	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	14		T18	6		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T9	14		T123	1		T247	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T1	2		T3	1		T6	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T16	1		T18	6		T19	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T4	6		T116	10		T128	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T16	1		T139	1		T151	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T122	1		T148	16		T309	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	1		T111	10		T122	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T10	1		T12	5		T123	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T239	1		T252	13		T156	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T239	1		T154	7		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	1		T239	1		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17367	1			T2	159		T8	125		T9	167
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T9	8		T124	9		T240	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T15	9		T13	16		T218	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T218	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T203	1		T127	6		T173	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T191	7		T240	11		T118	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T192	4		T250	10		T281	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T15	9		T139	2		T117	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T31	2		T251	2		T246	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T247	14		T265	1		T283	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T14	19		T18	9		T173	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T9	15		T123	12		T247	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1074	1			T6	15		T132	15		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T16	1		T18	14		T19	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T4	7		T116	8		T128	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T16	1		T151	12		T143	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T122	17		T262	1		T279	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T9	1		T111	13		T122	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T10	12		T12	12		T123	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T252	14		T116	10		T119	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T122	6		T144	2		T258	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T258	6		T113	14		T240	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T10	1		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T241	1		T127	7		T192	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T111	1		T191	8		T117	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T135	1		T141	1		T315	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T15	10		T139	3		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	1		T31	4		T147	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T123	13		T145	1		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1498	1			T1	2		T3	1		T6	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T9	17		T115	12		T117	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T112	10		T115	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T16	2		T18	15		T19	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T4	8		T116	9		T128	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T16	2		T111	14		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T122	18		T113	14		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	2		T122	11		T237	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T10	13		T12	13		T123	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T239	1		T252	15		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T239	1		T154	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	1		T15	10		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T9	11		T124	10		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T169	1		T316	1		T162	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17591	1			T2	159		T8	125		T9	173
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T218	4		T240	12		T299	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T127	7		T250	2		T264	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T111	9		T191	3		T118	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T251	10		T279	3		T150	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T139	18		T112	9		T259	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T31	5		T269	11		T246	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T172	11		T119	8		T146	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T7	8		T14	8		T17	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	12		T117	6		T247	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T148	3		T242	8		T246	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T18	5		T19	12		T151	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T4	5		T116	9		T128	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T111	9		T143	9		T126	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T148	15		T24	2		T279	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T122	12		T237	9		T114	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T12	4		T123	14		T237	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T252	12		T156	14		T116	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T154	6		T122	9		T144	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T15	11		T13	13		T258	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T9	2		T156	9		T74	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T57	3		T305	11		T319	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T173	4		T150	11		T54	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T295	8		T238	13		T320	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T9	11		T124	10		T240	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T15	10		T13	17		T218	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T218	4		T299	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T135	1		T203	2		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T111	1		T191	8		T240	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T141	1		T192	5		T250	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T15	10		T139	3		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	1		T31	4		T269	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T145	1		T172	1		T247	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T14	25		T18	10		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T9	17		T123	13		T247	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1410	1			T1	2		T3	1		T6	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T16	2		T18	15		T19	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T4	8		T116	9		T128	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T16	2		T139	1		T151	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T122	18		T148	1		T309	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T9	2		T111	14		T122	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	13		T12	13		T123	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T239	1		T252	15		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T239	1		T154	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	1		T239	1		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T2	159		T8	125		T9	173
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T9	2		T153	7		T304	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T15	11		T13	13		T247	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T127	7		T173	4		T264	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T111	9		T191	3		T118	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T250	2		T150	6		T210	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T139	18		T112	9		T259	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T31	5		T269	11		T251	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T172	11		T270	2		T283	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	8		T18	5		T173	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T9	12		T247	8		T119	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	938	1			T7	8		T17	8		T134	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T18	5		T19	12		T259	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T4	5		T116	9		T128	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T151	9		T143	9		T126	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T148	15		T279	11		T284	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T111	9		T122	12		T237	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T12	4		T123	14		T237	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T252	12		T156	14		T116	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T154	6		T122	9		T144	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T258	14		T117	2		T268	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

auto[0]

3481

1

T4

5

T7

8

T9

14