Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 26081 1 T1 2 T2 159 T3 1


Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[ADC_CTRL_FILTER_COND_IN] 23021 1 T1 2 T2 159 T3 1
auto[ADC_CTRL_FILTER_COND_OUT] 3060 1 T5 1 T14 33 T15 10


Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 20467 1 T2 159 T5 1 T8 125
auto[1] 5614 1 T1 2 T3 1 T4 13


Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 21936 1 T1 2 T2 159 T3 1
auto[1] 4145 1 T4 7 T6 15 T9 30


Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
maximum 212 1 T154 7 T122 18 T141 1
values[0] 11 1 T317 11 - - - -
values[1] 653 1 T5 1 T9 2 T151 22
values[2] 717 1 T14 33 T239 1 T135 1
values[3] 659 1 T18 15 T239 1 T111 23
values[4] 554 1 T12 17 T16 2 T239 1
values[5] 2736 1 T1 2 T3 1 T6 17
values[6] 778 1 T15 10 T139 21 T123 15
values[7] 653 1 T111 10 T156 10 T114 4
values[8] 637 1 T4 13 T9 13 T15 21
values[9] 943 1 T10 13 T139 1 T13 2
minimum 17528 1 T2 159 T8 125 T9 173


Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 767 1 T5 1 T14 33 T135 1
values[1] 596 1 T18 15 T239 1 T139 1
values[2] 645 1 T12 17 T239 1 T111 23
values[3] 2635 1 T1 2 T3 1 T6 17
values[4] 767 1 T9 29 T16 2 T19 25
values[5] 661 1 T15 10 T139 21 T123 15
values[6] 692 1 T111 10 T113 14 T156 10
values[7] 627 1 T4 13 T9 13 T10 13
values[8] 899 1 T139 1 T13 2 T122 18
values[9] 115 1 T154 7 T285 18 T183 1
minimum 17677 1 T2 159 T8 125 T9 175


Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 22600 1 T1 2 T2 159 T3 1
auto[1] 3481 1 T4 5 T7 8 T9 14


Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4


Covered bins
interrupt_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 239 1 T135 1 T143 10 T144 3
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 172 1 T5 1 T14 14 T125 9
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 196 1 T18 6 T239 1 T13 14
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 128 1 T139 1 T13 1 T151 10
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T12 5 T124 1 T145 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 199 1 T239 1 T111 10 T122 13
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1278 1 T1 2 T3 1 T6 2
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 146 1 T16 1 T31 7 T141 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 233 1 T9 14 T16 1 T142 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 156 1 T19 13 T123 1 T240 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 232 1 T139 19 T259 11 T117 3
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 151 1 T15 1 T123 3 T203 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 200 1 T111 10 T156 10 T114 4
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 194 1 T113 1 T259 5 T193 10
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 185 1 T4 6 T9 5 T10 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 127 1 T112 10 T172 12 T119 12
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 220 1 T13 1 T123 13 T252 13
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 214 1 T139 1 T122 1 T141 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 29 1 T285 10 T321 2 T176 3
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 33 1 T154 7 T183 1 T280 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17415 1 T2 159 T8 125 T9 168
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 38 1 T129 1 T272 12 T322 1
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 195 1 T143 9 T144 2 T191 7
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 161 1 T14 19 T218 1 T115 11
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 158 1 T18 9 T13 16 T218 1
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 114 1 T151 12 T218 1 T240 10
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T12 12 T117 1 T127 6
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 144 1 T111 13 T122 10 T258 7
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1042 1 T6 15 T132 15 T122 6
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 169 1 T16 1 T31 2 T24 4
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 198 1 T9 15 T16 1 T112 9
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 180 1 T19 12 T123 12 T240 9
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 123 1 T139 2 T117 5 T173 10
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 155 1 T15 9 T123 12 T203 1
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 121 1 T246 2 T264 2 T265 1
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T113 13 T193 11 T248 12
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 201 1 T4 7 T9 8 T10 12
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 114 1 T119 10 T130 13 T278 4
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 251 1 T13 1 T123 8 T252 14
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 214 1 T122 17 T237 3 T115 7
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 21 1 T285 8 T321 1 T176 7
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 32 1 T280 12 T257 8 T256 12
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 182 1 T9 7 T10 1 T14 2
auto[1] minimum auto[ADC_CTRL_FILTER_COND_OUT] 42 1 T272 12 T322 12 T323 4


Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
* [values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] -- -- 2
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 56 1 T252 13 T173 1 T285 10
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 60 1 T154 7 T122 1 T141 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 1 1 T317 1 - - - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T9 1 T141 1 T144 3
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 154 1 T5 1 T151 10 T115 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 235 1 T239 1 T135 1 T13 14
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 188 1 T14 14 T139 1 T125 9
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 174 1 T18 6 T124 1 T145 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 169 1 T239 1 T111 10 T13 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 169 1 T12 5 T239 1 T122 10
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 129 1 T16 1 T141 1 T156 15
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1337 1 T1 2 T3 1 T6 2
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 138 1 T19 13 T123 1 T31 7
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 254 1 T139 19 T112 1 T259 11
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 167 1 T15 1 T123 3 T203 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 170 1 T111 10 T156 10 T114 4
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 196 1 T259 5 T127 7 T242 10
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 196 1 T4 6 T9 5 T15 12
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 133 1 T112 10 T113 1 T119 12
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 228 1 T10 1 T13 1 T123 13
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 223 1 T139 1 T115 1 T172 12
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17367 1 T2 159 T8 125 T9 167
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 35 1 T252 14 T285 8 T321 1
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 61 1 T122 17 T237 3 T221 1
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 10 1 T317 10 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 154 1 T9 1 T144 2 T116 8
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 153 1 T151 12 T115 11 T240 11
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 173 1 T13 16 T143 9 T191 7
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 121 1 T14 19 T218 2 T240 10
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 153 1 T18 9 T117 1 T281 2
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 163 1 T111 13 T122 10 T258 7
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 148 1 T12 12 T122 6 T127 6
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 108 1 T16 1 T282 5 T24 4
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1077 1 T6 15 T9 15 T16 1
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 184 1 T19 12 T123 12 T31 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 173 1 T139 2 T112 9 T117 5
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 184 1 T15 9 T123 12 T203 1
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 103 1 T173 10 T265 1 T283 15
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 184 1 T127 10 T248 12 T283 8
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 181 1 T4 7 T9 8 T15 9
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 127 1 T113 13 T119 10 T130 13
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 285 1 T10 12 T13 1 T123 8
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 207 1 T115 7 T128 8 T250 10
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 161 1 T9 6 T10 1 T14 2


Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4


Covered bins
wakeup_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 240 1 T135 1 T143 10 T144 3
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 203 1 T5 1 T14 25 T125 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 201 1 T18 10 T239 1 T13 17
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 149 1 T139 1 T13 1 T151 13
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 196 1 T12 13 T124 1 T145 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 185 1 T239 1 T111 14 T122 11
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1394 1 T1 2 T3 1 T6 17
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 216 1 T16 2 T31 4 T141 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 241 1 T9 17 T16 2 T142 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 219 1 T19 13 T123 13 T240 10
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 161 1 T139 3 T259 1 T117 6
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 198 1 T15 10 T123 13 T203 2
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 154 1 T111 1 T156 1 T114 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 218 1 T113 14 T259 1 T193 12
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 243 1 T4 8 T9 11 T10 13
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 143 1 T112 1 T172 1 T119 11
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 297 1 T13 2 T123 9 T252 15
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 260 1 T139 1 T122 18 T141 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 30 1 T285 9 T321 2 T176 8
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 39 1 T154 1 T183 1 T280 13
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17561 1 T2 159 T8 125 T9 175
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 52 1 T129 1 T272 13 T322 13
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 194 1 T143 9 T144 2 T191 3
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 130 1 T14 8 T125 8 T116 11
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 153 1 T18 5 T13 13 T153 7
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 93 1 T151 9 T218 2 T118 15
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 106 1 T12 4 T127 7 T284 12
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 158 1 T111 9 T122 12 T258 6
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 926 1 T7 8 T17 8 T134 17
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 99 1 T31 5 T156 14 T24 2
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 190 1 T9 12 T116 11 T128 12
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 117 1 T19 12 T128 9 T250 8
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 194 1 T139 18 T259 10 T117 2
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 108 1 T123 2 T143 9 T258 14
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 167 1 T111 9 T156 9 T114 3
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 153 1 T259 4 T193 9 T270 2
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 143 1 T4 5 T9 2 T15 11
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 98 1 T112 9 T172 11 T119 11
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 174 1 T123 12 T252 12 T237 9
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 168 1 T237 4 T128 8 T250 2
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 20 1 T285 9 T321 1 T176 2
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 26 1 T154 6 T257 2 T160 2
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 36 1 T114 13 T117 6 T74 1
auto[1] minimum auto[ADC_CTRL_FILTER_COND_OUT] 28 1 T272 11 T297 2 T323 2


Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[1]] [values[0]] * -- -- 2
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 43 1 T252 15 T173 1 T285 9
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 77 1 T154 1 T122 18 T141 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 11 1 T317 11 - - - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 197 1 T9 2 T141 1 T144 3
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 184 1 T5 1 T151 13 T115 12
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 224 1 T239 1 T135 1 T13 17
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 170 1 T14 25 T139 1 T125 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 195 1 T18 10 T124 1 T145 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 204 1 T239 1 T111 14 T13 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 204 1 T12 13 T239 1 T122 7
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 148 1 T16 2 T141 1 T156 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1413 1 T1 2 T3 1 T6 17
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 222 1 T19 13 T123 13 T31 4
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 219 1 T139 3 T112 10 T259 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 230 1 T15 10 T123 13 T203 2
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 134 1 T111 1 T156 1 T114 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 229 1 T259 1 T127 11 T242 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 224 1 T4 8 T9 11 T15 10
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 153 1 T112 1 T113 14 T119 11
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 337 1 T10 13 T13 2 T123 9
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 254 1 T139 1 T115 8 T172 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17528 1 T2 159 T8 125 T9 173
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 48 1 T252 12 T285 9 T321 1
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 44 1 T154 6 T237 4 T266 4
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 149 1 T144 2 T114 13 T116 9
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 123 1 T151 9 T116 11 T279 3
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 184 1 T13 13 T143 9 T191 3
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 139 1 T14 8 T125 8 T218 2
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 132 1 T18 5 T148 15 T284 12
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 128 1 T111 9 T122 12 T258 6
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 113 1 T12 4 T122 9 T127 7
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 89 1 T156 14 T24 2 T268 14
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1001 1 T7 8 T9 12 T17 8
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 100 1 T19 12 T31 5 T128 9
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 208 1 T139 18 T259 10 T117 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 121 1 T123 2 T143 9 T258 14
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 139 1 T111 9 T156 9 T114 3
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 151 1 T259 4 T127 6 T242 9
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 153 1 T4 5 T9 2 T15 11
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 107 1 T112 9 T119 11 T120 5
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 176 1 T123 12 T237 9 T126 12
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 176 1 T172 11 T128 8 T250 2


Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cp   clk_gate_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 22600 1 T1 2 T2 159 T3 1
auto[1] auto[0] 3481 1 T4 5 T7 8 T9 14