Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26081

1

T1

2

T2

159

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20761

1

T2

159

T5

1

T8

125

auto[ADC_CTRL_FILTER_COND_OUT]

5320

1

T1

2

T3

1

T4

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20464

1

T2

159

T4

13

T8

125

auto[1]

5617

1

T1

2

T3

1

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21936

1

T1

2

T2

159

T3

1

auto[1]

4145

1

T4

7

T6

15

T9

30

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	271	1			T16	2		T139	1		T156	10
values[0]	48	1			T238	14		T243	1		T261	22
values[1]	637	1			T239	1		T13	2		T142	1
values[2]	696	1			T4	13		T9	2		T154	7
values[3]	592	1			T9	29		T15	10		T239	1
values[4]	493	1			T18	35		T141	1		T240	11
values[5]	753	1			T9	13		T14	33		T111	23
values[6]	733	1			T5	1		T12	17		T15	21
values[7]	789	1			T10	13		T13	1		T122	23
values[8]	637	1			T239	1		T13	30		T144	1
values[9]	2904	1			T1	2		T3	1		T6	17
minimum	17528	1			T2	159		T8	125		T9	173

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	689	1			T239	1		T154	7		T151	22
values[1]	2780	1			T1	2		T3	1		T4	13
values[2]	428	1			T18	15		T239	1		T111	10
values[3]	580	1			T18	20		T135	1		T124	10
values[4]	722	1			T9	13		T14	33		T111	23
values[5]	827	1			T5	1		T12	17		T15	21
values[6]	529	1			T10	13		T13	1		T191	11
values[7]	836	1			T239	1		T139	1		T13	30
values[8]	822	1			T16	4		T19	25		T139	1
values[9]	130	1			T141	1		T145	1		T173	15
minimum	17738	1			T2	159		T8	125		T9	173

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

3481

1

T4

5

T7

8

T9

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T128	10		T146	11		T266	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T239	1		T154	7		T151	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T9	15		T15	1		T123	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1245	1			T1	2		T3	1		T4	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T111	10		T115	1		T247	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T18	6		T239	1		T156	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T124	1		T141	1		T240	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T18	6		T135	1		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T111	10		T139	19		T114	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	5		T14	14		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	1		T15	12		T31	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	5		T122	13		T143	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T218	3		T241	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T10	1		T13	1		T191	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T13	14		T123	13		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T239	1		T139	1		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T16	2		T139	1		T122	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T19	13		T122	1		T125	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T145	1		T173	5		T253	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T141	1		T250	9		T254	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17384	1			T2	159		T8	125		T9	167
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T13	1		T142	1		T267	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T128	8		T283	16		T209	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T151	12		T143	9		T237	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T9	16		T15	9		T123	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1070	1			T4	7		T6	15		T132	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T115	11		T247	10		T246	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T18	9		T116	5		T118	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T124	9		T240	10		T263	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T18	14		T112	9		T258	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T111	13		T139	2		T127	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T9	8		T14	19		T113	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	9		T31	2		T118	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T12	12		T122	10		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T218	1		T130	2		T246	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T10	12		T191	7		T250	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T13	16		T123	8		T113	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T127	6		T250	10		T251	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T16	2		T122	6		T144	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T19	12		T122	17		T252	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T173	10		T253	9		T324	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T250	9		T254	8		T211	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	6		T10	1		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T13	1		T53	1		T325	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T16	1		T139	1		T156	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T247	9		T250	9		T211	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T238	14		T243	1		T261	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T258	7		T113	1		T128	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T239	1		T13	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	1		T112	10		T116	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	6		T154	7		T151	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	14		T15	1		T111	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T239	1		T135	1		T203	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T141	1		T240	1		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T18	12		T118	11		T119	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T111	10		T139	19		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	5		T14	14		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	1		T15	12		T31	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	5		T237	10		T258	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T218	3		T241	1		T146	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	1		T13	1		T122	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	14		T259	16		T240	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T239	1		T144	1		T127	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T16	1		T122	10		T123	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1322	1			T1	2		T3	1		T6	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17367	1			T2	159		T8	125		T9	167
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T16	1		T173	10		T295	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T247	5		T250	9		T211	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T261	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T258	7		T113	18		T128	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	1		T143	9		T237	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	1		T116	10		T153	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T4	7		T151	12		T251	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T9	15		T15	9		T123	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T203	1		T116	5		T147	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T240	10		T263	10		T272	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T18	23		T118	10		T119	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T111	13		T139	2		T124	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	8		T14	19		T112	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T15	9		T31	2		T128	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	12		T237	11		T258	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T218	1		T130	2		T246	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	12		T122	10		T143	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	16		T240	11		T116	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T127	6		T264	13		T265	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T16	1		T122	6		T123	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1129	1			T6	15		T19	12		T132	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T10	1		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T128	9		T146	1		T266	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T239	1		T154	1		T151	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T9	19		T15	10		T123	26
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1396	1			T1	2		T3	1		T4	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T111	1		T115	12		T247	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T18	10		T239	1		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T124	10		T141	1		T240	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T18	15		T135	1		T112	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T111	14		T139	3		T114	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	11		T14	25		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	1		T15	10		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T12	13		T122	11		T143	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T218	4		T241	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T10	13		T13	1		T191	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T13	17		T123	9		T113	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T239	1		T139	1		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T16	4		T139	1		T122	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T19	13		T122	18		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T145	1		T173	11		T253	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T141	1		T250	10		T254	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17554	1			T2	159		T8	125		T9	173
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T13	2		T142	1		T267	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T128	9		T146	10		T266	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T154	6		T151	9		T143	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T9	12		T123	2		T112	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	919	1			T4	5		T7	8		T17	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T111	9		T247	11		T267	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T18	5		T156	14		T116	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T268	25		T272	10		T273	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T18	5		T258	14		T128	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T111	9		T139	18		T114	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T9	2		T14	8		T172	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T15	11		T31	5		T126	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	4		T122	12		T143	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T146	10		T269	12		T130	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T191	3		T126	12		T250	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	13		T123	12		T259	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T127	7		T250	2		T251	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T122	9		T144	2		T218	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T19	12		T125	8		T252	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T173	4		T324	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T250	8		T254	8		T211	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T246	11		T256	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T267	13		T238	13		T310	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T16	2		T139	1		T156	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T247	6		T250	10		T211	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T238	1		T243	1		T261	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T258	8		T113	19		T128	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T239	1		T13	2		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	2		T112	1		T116	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	8		T154	1		T151	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T9	17		T15	10		T111	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T239	1		T135	1		T203	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T141	1		T240	11		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T18	25		T118	11		T119	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T111	14		T139	3		T124	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T9	11		T14	25		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	1		T15	10		T31	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T12	13		T237	12		T258	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T218	4		T241	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T10	13		T13	1		T122	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	17		T259	2		T240	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T239	1		T144	1		T127	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T16	2		T122	7		T123	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1472	1			T1	2		T3	1		T6	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T2	159		T8	125		T9	173
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T156	9		T172	11		T173	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T247	8		T250	8		T211	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T238	13		T261	9		T276	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T258	6		T128	9		T266	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T143	9		T237	4		T267	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T112	9		T116	11		T146	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	5		T154	6		T151	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	12		T111	9		T123	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T156	14		T116	11		T262	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T268	14		T272	10		T273	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T18	10		T118	10		T119	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T111	9		T139	18		T114	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	2		T14	8		T258	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T15	11		T31	5		T126	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	4		T237	9		T258	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T146	10		T269	12		T130	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T122	12		T143	9		T191	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	13		T259	14		T116	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T127	7		T264	9		T274	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T122	9		T123	12		T144	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	979	1			T7	8		T17	8		T19	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22600

1

T1

2

T2

159

T3

1

auto[1]

auto[0]

3481

1

T4

5

T7

8

T9

14