Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.59	98.98	95.69	100.00	100.00	98.18	98.64	91.62

Total test records in report: 917

T794	/workspace/coverage/default/16.adc_ctrl_filters_both.785493793	Feb 25 12:45:41 PM PST 24	Feb 25 12:51:40 PM PST 24	162781725669 ps
T795	/workspace/coverage/default/39.adc_ctrl_filters_both.3360375526	Feb 25 12:47:42 PM PST 24	Feb 25 12:54:39 PM PST 24	338242226539 ps
T36	/workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2766456610	Feb 25 12:53:03 PM PST 24	Feb 25 12:53:05 PM PST 24	539257226 ps
T32	/workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4218579929	Feb 25 12:52:23 PM PST 24	Feb 25 12:52:25 PM PST 24	499775312 ps
T796	/workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1282190050	Feb 25 12:53:16 PM PST 24	Feb 25 12:53:18 PM PST 24	343690466 ps
T30	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3450884831	Feb 25 12:52:39 PM PST 24	Feb 25 12:52:41 PM PST 24	331925217 ps
T76	/workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2740388458	Feb 25 12:53:06 PM PST 24	Feb 25 12:53:08 PM PST 24	444811155 ps
T33	/workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1641650997	Feb 25 12:53:08 PM PST 24	Feb 25 12:53:10 PM PST 24	604046510 ps
T797	/workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2237001639	Feb 25 12:53:16 PM PST 24	Feb 25 12:53:18 PM PST 24	391450293 ps
T798	/workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3882657923	Feb 25 12:52:32 PM PST 24	Feb 25 12:52:33 PM PST 24	374435209 ps
T799	/workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.864842499	Feb 25 12:52:37 PM PST 24	Feb 25 12:52:38 PM PST 24	362841875 ps
T800	/workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1619913811	Feb 25 12:53:16 PM PST 24	Feb 25 12:53:18 PM PST 24	502681897 ps
T27	/workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.327534104	Feb 25 12:53:09 PM PST 24	Feb 25 12:53:13 PM PST 24	4641389483 ps
T34	/workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2920472102	Feb 25 12:52:38 PM PST 24	Feb 25 12:52:42 PM PST 24	921676666 ps
T104	/workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1721962318	Feb 25 12:53:04 PM PST 24	Feb 25 12:53:27 PM PST 24	8482335553 ps
T77	/workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.4194086540	Feb 25 12:52:46 PM PST 24	Feb 25 12:52:48 PM PST 24	412007980 ps
T105	/workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.12852858	Feb 25 12:52:24 PM PST 24	Feb 25 12:52:28 PM PST 24	4543993306 ps
T78	/workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3043903173	Feb 25 12:53:00 PM PST 24	Feb 25 12:53:02 PM PST 24	473724313 ps
T82	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3340913143	Feb 25 12:52:33 PM PST 24	Feb 25 12:52:35 PM PST 24	523969785 ps
T28	/workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3608291675	Feb 25 12:52:46 PM PST 24	Feb 25 12:52:58 PM PST 24	4453604438 ps
T79	/workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2058988913	Feb 25 12:52:53 PM PST 24	Feb 25 12:52:55 PM PST 24	573259673 ps
T801	/workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3825830764	Feb 25 12:52:38 PM PST 24	Feb 25 12:52:39 PM PST 24	501028330 ps
T106	/workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.804418520	Feb 25 12:52:40 PM PST 24	Feb 25 12:52:42 PM PST 24	5008545197 ps
T802	/workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.446508852	Feb 25 12:53:23 PM PST 24	Feb 25 12:53:24 PM PST 24	435349609 ps
T80	/workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1556482675	Feb 25 12:52:46 PM PST 24	Feb 25 12:52:47 PM PST 24	439904643 ps
T29	/workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.260049372	Feb 25 12:52:46 PM PST 24	Feb 25 12:52:55 PM PST 24	2294569948 ps
T107	/workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3889377130	Feb 25 12:52:49 PM PST 24	Feb 25 12:52:52 PM PST 24	482584253 ps
T803	/workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2399570940	Feb 25 12:53:11 PM PST 24	Feb 25 12:53:12 PM PST 24	371556644 ps
T109	/workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2023021670	Feb 25 12:52:59 PM PST 24	Feb 25 12:53:03 PM PST 24	4080757106 ps
T101	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4194619465	Feb 25 12:52:31 PM PST 24	Feb 25 12:54:30 PM PST 24	51935857731 ps
T83	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1111638377	Feb 25 12:52:47 PM PST 24	Feb 25 12:52:52 PM PST 24	1129608701 ps
T97	/workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4269968059	Feb 25 12:52:47 PM PST 24	Feb 25 12:52:51 PM PST 24	3879687564 ps
T804	/workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1984225703	Feb 25 12:53:09 PM PST 24	Feb 25 12:53:10 PM PST 24	438611748 ps
T108	/workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.243817949	Feb 25 12:52:37 PM PST 24	Feb 25 12:52:40 PM PST 24	616398537 ps
T805	/workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.382370888	Feb 25 12:52:30 PM PST 24	Feb 25 12:52:33 PM PST 24	4307869346 ps
T806	/workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.205155513	Feb 25 12:52:37 PM PST 24	Feb 25 12:52:39 PM PST 24	540792169 ps
T807	/workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1520209602	Feb 25 12:53:03 PM PST 24	Feb 25 12:53:04 PM PST 24	469532845 ps
T102	/workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.295546772	Feb 25 12:53:04 PM PST 24	Feb 25 12:53:05 PM PST 24	338201410 ps
T808	/workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2969493721	Feb 25 12:53:04 PM PST 24	Feb 25 12:53:04 PM PST 24	450281696 ps
T809	/workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.269332307	Feb 25 12:53:08 PM PST 24	Feb 25 12:53:09 PM PST 24	366675864 ps
T103	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2723350875	Feb 25 12:52:43 PM PST 24	Feb 25 12:52:45 PM PST 24	1313849092 ps
T810	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.57476583	Feb 25 12:52:44 PM PST 24	Feb 25 12:52:46 PM PST 24	476545308 ps
T811	/workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1814038815	Feb 25 12:52:50 PM PST 24	Feb 25 12:52:52 PM PST 24	594237290 ps
T98	/workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.624327739	Feb 25 12:52:58 PM PST 24	Feb 25 12:53:00 PM PST 24	4419258799 ps
T225	/workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.703829177	Feb 25 12:52:37 PM PST 24	Feb 25 12:52:40 PM PST 24	5290158264 ps
T99	/workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.975826377	Feb 25 12:52:43 PM PST 24	Feb 25 12:52:46 PM PST 24	2241697003 ps
T812	/workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1142822336	Feb 25 12:52:41 PM PST 24	Feb 25 12:52:42 PM PST 24	336273277 ps
T813	/workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.591650066	Feb 25 12:52:29 PM PST 24	Feb 25 12:52:30 PM PST 24	429608811 ps
T814	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2561921876	Feb 25 12:52:30 PM PST 24	Feb 25 12:52:32 PM PST 24	448740139 ps
T84	/workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3541293572	Feb 25 12:53:07 PM PST 24	Feb 25 12:53:09 PM PST 24	384313515 ps
T815	/workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.283885262	Feb 25 12:52:48 PM PST 24	Feb 25 12:53:01 PM PST 24	4540779380 ps
T816	/workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2316085773	Feb 25 12:53:11 PM PST 24	Feb 25 12:53:12 PM PST 24	345502319 ps
T817	/workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1183988225	Feb 25 12:53:06 PM PST 24	Feb 25 12:53:07 PM PST 24	545961670 ps
T818	/workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1018090771	Feb 25 12:53:06 PM PST 24	Feb 25 12:53:08 PM PST 24	365187875 ps
T819	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2270390294	Feb 25 12:52:24 PM PST 24	Feb 25 12:52:29 PM PST 24	970537665 ps
T85	/workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2677580812	Feb 25 12:53:04 PM PST 24	Feb 25 12:53:05 PM PST 24	456591784 ps
T820	/workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2895982365	Feb 25 12:53:09 PM PST 24	Feb 25 12:53:12 PM PST 24	679747874 ps
T821	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2094015405	Feb 25 12:52:29 PM PST 24	Feb 25 12:52:31 PM PST 24	1261983616 ps
T822	/workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.573660594	Feb 25 12:52:25 PM PST 24	Feb 25 12:52:28 PM PST 24	813872208 ps
T823	/workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1424566179	Feb 25 12:53:11 PM PST 24	Feb 25 12:53:12 PM PST 24	436031500 ps
T824	/workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1917412940	Feb 25 12:53:02 PM PST 24	Feb 25 12:53:09 PM PST 24	8457065964 ps
T86	/workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2898547211	Feb 25 12:53:02 PM PST 24	Feb 25 12:53:04 PM PST 24	407095451 ps
T825	/workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.505948443	Feb 25 12:53:05 PM PST 24	Feb 25 12:53:07 PM PST 24	654470112 ps
T826	/workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.344335680	Feb 25 12:52:49 PM PST 24	Feb 25 12:52:51 PM PST 24	509966088 ps
T827	/workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3672867026	Feb 25 12:52:59 PM PST 24	Feb 25 12:53:00 PM PST 24	417280686 ps
T100	/workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.371699872	Feb 25 12:53:04 PM PST 24	Feb 25 12:53:05 PM PST 24	527283612 ps
T828	/workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.996128435	Feb 25 12:52:37 PM PST 24	Feb 25 12:52:39 PM PST 24	358426119 ps
T829	/workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2170882474	Feb 25 12:53:03 PM PST 24	Feb 25 12:53:07 PM PST 24	9146476087 ps
T830	/workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1061400929	Feb 25 12:52:30 PM PST 24	Feb 25 12:52:32 PM PST 24	484496582 ps
T831	/workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.707858333	Feb 25 12:52:48 PM PST 24	Feb 25 12:52:49 PM PST 24	370910051 ps
T832	/workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2822822155	Feb 25 12:53:04 PM PST 24	Feb 25 12:53:05 PM PST 24	506658509 ps
T833	/workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1243944379	Feb 25 12:52:26 PM PST 24	Feb 25 12:52:37 PM PST 24	4056315238 ps
T834	/workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3924162007	Feb 25 12:53:07 PM PST 24	Feb 25 12:53:10 PM PST 24	486541359 ps
T835	/workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1473221413	Feb 25 12:53:03 PM PST 24	Feb 25 12:53:06 PM PST 24	4851167789 ps
T836	/workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3340835328	Feb 25 12:52:39 PM PST 24	Feb 25 12:52:41 PM PST 24	379196570 ps
T837	/workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2367697775	Feb 25 12:53:06 PM PST 24	Feb 25 12:53:08 PM PST 24	1335604711 ps
T838	/workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3774023200	Feb 25 12:53:06 PM PST 24	Feb 25 12:53:08 PM PST 24	405889032 ps
T839	/workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3325630244	Feb 25 12:52:48 PM PST 24	Feb 25 12:52:52 PM PST 24	4455246201 ps
T840	/workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1444066939	Feb 25 12:52:46 PM PST 24	Feb 25 12:52:48 PM PST 24	314040315 ps
T841	/workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1267899625	Feb 25 12:53:03 PM PST 24	Feb 25 12:53:04 PM PST 24	478495627 ps
T87	/workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4121608718	Feb 25 12:52:48 PM PST 24	Feb 25 12:52:49 PM PST 24	525948766 ps
T842	/workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2033896937	Feb 25 12:53:02 PM PST 24	Feb 25 12:53:06 PM PST 24	2501189852 ps
T843	/workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2583183185	Feb 25 12:53:05 PM PST 24	Feb 25 12:53:06 PM PST 24	457807622 ps
T844	/workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1757087873	Feb 25 12:53:03 PM PST 24	Feb 25 12:53:07 PM PST 24	4516463526 ps
T845	/workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2163496578	Feb 25 12:52:32 PM PST 24	Feb 25 12:52:44 PM PST 24	5198436242 ps
T846	/workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3000239664	Feb 25 12:53:04 PM PST 24	Feb 25 12:53:05 PM PST 24	476865540 ps
T847	/workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.461429634	Feb 25 12:52:48 PM PST 24	Feb 25 12:52:50 PM PST 24	357907122 ps
T88	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2167125725	Feb 25 12:52:31 PM PST 24	Feb 25 12:52:32 PM PST 24	1405173496 ps
T848	/workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3622924300	Feb 25 12:53:08 PM PST 24	Feb 25 12:53:09 PM PST 24	295718957 ps
T89	/workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3824676184	Feb 25 12:52:39 PM PST 24	Feb 25 12:52:40 PM PST 24	507477818 ps
T849	/workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3215067149	Feb 25 12:52:33 PM PST 24	Feb 25 12:52:36 PM PST 24	484578113 ps
T850	/workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1974688572	Feb 25 12:53:04 PM PST 24	Feb 25 12:53:05 PM PST 24	956375664 ps
T851	/workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.997163159	Feb 25 12:53:13 PM PST 24	Feb 25 12:53:15 PM PST 24	367503775 ps
T90	/workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2798731110	Feb 25 12:53:03 PM PST 24	Feb 25 12:53:05 PM PST 24	443224882 ps
T852	/workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.376904122	Feb 25 12:53:11 PM PST 24	Feb 25 12:53:12 PM PST 24	509029160 ps
T853	/workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.668428859	Feb 25 12:52:59 PM PST 24	Feb 25 12:53:00 PM PST 24	366431741 ps
T854	/workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.327975737	Feb 25 12:53:09 PM PST 24	Feb 25 12:53:11 PM PST 24	456334983 ps
T855	/workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.758061739	Feb 25 12:53:06 PM PST 24	Feb 25 12:53:09 PM PST 24	531451413 ps
T856	/workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1428813529	Feb 25 12:52:48 PM PST 24	Feb 25 12:52:53 PM PST 24	8080527458 ps
T857	/workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3658785891	Feb 25 12:53:09 PM PST 24	Feb 25 12:53:10 PM PST 24	407810085 ps
T858	/workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.4264643196	Feb 25 12:53:09 PM PST 24	Feb 25 12:53:10 PM PST 24	355243833 ps
T859	/workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2477494487	Feb 25 12:53:11 PM PST 24	Feb 25 12:53:12 PM PST 24	483412423 ps
T860	/workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4137199526	Feb 25 12:52:38 PM PST 24	Feb 25 12:52:40 PM PST 24	358226480 ps
T861	/workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2302099513	Feb 25 12:52:27 PM PST 24	Feb 25 12:52:30 PM PST 24	2237996575 ps
T862	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2667489093	Feb 25 12:52:26 PM PST 24	Feb 25 12:52:28 PM PST 24	482763928 ps
T863	/workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1095866320	Feb 25 12:53:03 PM PST 24	Feb 25 12:53:05 PM PST 24	604553168 ps
T864	/workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1153514089	Feb 25 12:52:58 PM PST 24	Feb 25 12:53:00 PM PST 24	406872611 ps
T865	/workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2420289546	Feb 25 12:53:11 PM PST 24	Feb 25 12:53:12 PM PST 24	407641154 ps
T866	/workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2523140089	Feb 25 12:53:03 PM PST 24	Feb 25 12:53:04 PM PST 24	482869196 ps
T867	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.638423651	Feb 25 12:52:29 PM PST 24	Feb 25 12:52:31 PM PST 24	454923999 ps
T868	/workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3677501056	Feb 25 12:52:48 PM PST 24	Feb 25 12:52:50 PM PST 24	611241805 ps
T869	/workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3335920031	Feb 25 12:53:11 PM PST 24	Feb 25 12:53:12 PM PST 24	474238481 ps
T870	/workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1778256758	Feb 25 12:53:08 PM PST 24	Feb 25 12:53:09 PM PST 24	424900883 ps
T871	/workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1599288854	Feb 25 12:53:06 PM PST 24	Feb 25 12:53:13 PM PST 24	5140517041 ps
T91	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.750014661	Feb 25 12:52:29 PM PST 24	Feb 25 12:52:45 PM PST 24	20901478827 ps
T872	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1696003139	Feb 25 12:52:48 PM PST 24	Feb 25 12:52:50 PM PST 24	481604095 ps
T873	/workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.534484025	Feb 25 12:53:05 PM PST 24	Feb 25 12:53:06 PM PST 24	453931520 ps
T874	/workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3028594388	Feb 25 12:52:48 PM PST 24	Feb 25 12:52:49 PM PST 24	545587318 ps
T875	/workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3443324904	Feb 25 12:52:47 PM PST 24	Feb 25 12:52:48 PM PST 24	2535862511 ps
T876	/workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3757845470	Feb 25 12:53:06 PM PST 24	Feb 25 12:53:11 PM PST 24	8467896650 ps
T877	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2151155805	Feb 25 12:52:38 PM PST 24	Feb 25 12:52:40 PM PST 24	925637018 ps
T878	/workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1379722248	Feb 25 12:53:13 PM PST 24	Feb 25 12:53:15 PM PST 24	522893765 ps
T879	/workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2618036834	Feb 25 12:53:02 PM PST 24	Feb 25 12:53:04 PM PST 24	496226826 ps
T880	/workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.4289617817	Feb 25 12:53:05 PM PST 24	Feb 25 12:53:06 PM PST 24	345303382 ps
T881	/workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3452838773	Feb 25 12:52:48 PM PST 24	Feb 25 12:52:53 PM PST 24	4858033247 ps
T882	/workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1092496591	Feb 25 12:53:00 PM PST 24	Feb 25 12:53:02 PM PST 24	351870539 ps
T883	/workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2547280867	Feb 25 12:52:49 PM PST 24	Feb 25 12:52:50 PM PST 24	487981774 ps
T884	/workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3156451385	Feb 25 12:53:13 PM PST 24	Feb 25 12:53:15 PM PST 24	468845986 ps
T885	/workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2321383703	Feb 25 12:52:48 PM PST 24	Feb 25 12:52:51 PM PST 24	4418887057 ps
T886	/workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.913224890	Feb 25 12:53:09 PM PST 24	Feb 25 12:53:11 PM PST 24	504703924 ps
T887	/workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1294091767	Feb 25 12:52:49 PM PST 24	Feb 25 12:52:51 PM PST 24	563930671 ps
T888	/workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1542063978	Feb 25 12:52:37 PM PST 24	Feb 25 12:52:38 PM PST 24	511638661 ps
T92	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1994204475	Feb 25 12:52:34 PM PST 24	Feb 25 12:52:36 PM PST 24	561259268 ps
T889	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3573571493	Feb 25 12:52:39 PM PST 24	Feb 25 12:52:43 PM PST 24	1172168515 ps
T93	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1462841012	Feb 25 12:52:30 PM PST 24	Feb 25 12:54:30 PM PST 24	52320807599 ps
T890	/workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3465741535	Feb 25 12:53:16 PM PST 24	Feb 25 12:53:17 PM PST 24	310395738 ps
T891	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2172547417	Feb 25 12:52:34 PM PST 24	Feb 25 12:52:36 PM PST 24	364371258 ps
T892	/workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1090745199	Feb 25 12:52:30 PM PST 24	Feb 25 12:52:54 PM PST 24	8396401087 ps
T893	/workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.444500529	Feb 25 12:53:13 PM PST 24	Feb 25 12:53:15 PM PST 24	357947103 ps
T894	/workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.4004437875	Feb 25 12:52:47 PM PST 24	Feb 25 12:52:47 PM PST 24	528618552 ps
T895	/workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2269536871	Feb 25 12:53:01 PM PST 24	Feb 25 12:53:21 PM PST 24	7690087591 ps
T896	/workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3069264459	Feb 25 12:53:05 PM PST 24	Feb 25 12:53:08 PM PST 24	10958490193 ps
T897	/workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3256569129	Feb 25 12:52:48 PM PST 24	Feb 25 12:53:00 PM PST 24	8345489245 ps
T898	/workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3985436529	Feb 25 12:53:04 PM PST 24	Feb 25 12:53:05 PM PST 24	435870005 ps
T899	/workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1559226029	Feb 25 12:53:11 PM PST 24	Feb 25 12:53:13 PM PST 24	388805271 ps
T900	/workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.620831187	Feb 25 12:52:37 PM PST 24	Feb 25 12:52:42 PM PST 24	5429177151 ps
T94	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4135007336	Feb 25 12:52:32 PM PST 24	Feb 25 12:52:33 PM PST 24	537981640 ps
T901	/workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.910778873	Feb 25 12:53:03 PM PST 24	Feb 25 12:53:06 PM PST 24	2665791460 ps
T902	/workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3068117733	Feb 25 12:52:38 PM PST 24	Feb 25 12:52:44 PM PST 24	2337249058 ps
T903	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.903162320	Feb 25 12:52:34 PM PST 24	Feb 25 12:52:36 PM PST 24	707332217 ps
T904	/workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1497025541	Feb 25 12:53:07 PM PST 24	Feb 25 12:53:08 PM PST 24	487773812 ps
T905	/workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1631604305	Feb 25 12:52:38 PM PST 24	Feb 25 12:52:40 PM PST 24	575402466 ps
T906	/workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3744816353	Feb 25 12:52:22 PM PST 24	Feb 25 12:52:26 PM PST 24	558983203 ps
T907	/workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.906620040	Feb 25 12:53:05 PM PST 24	Feb 25 12:53:07 PM PST 24	2346819514 ps
T226	/workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.321426900	Feb 25 12:53:03 PM PST 24	Feb 25 12:53:09 PM PST 24	4214720244 ps
T908	/workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4129310491	Feb 25 12:53:02 PM PST 24	Feb 25 12:53:04 PM PST 24	583585077 ps
T909	/workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1836618016	Feb 25 12:52:24 PM PST 24	Feb 25 12:52:31 PM PST 24	2577183329 ps
T95	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3699277906	Feb 25 12:52:48 PM PST 24	Feb 25 12:53:01 PM PST 24	24990344167 ps
T910	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.865948015	Feb 25 12:52:33 PM PST 24	Feb 25 12:52:35 PM PST 24	754467421 ps
T911	/workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3161609925	Feb 25 12:53:16 PM PST 24	Feb 25 12:53:17 PM PST 24	404502822 ps
T96	/workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.272293490	Feb 25 12:52:47 PM PST 24	Feb 25 12:52:48 PM PST 24	333881782 ps
T912	/workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2520844960	Feb 25 12:53:04 PM PST 24	Feb 25 12:53:08 PM PST 24	312663661 ps
T913	/workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.88501053	Feb 25 12:53:03 PM PST 24	Feb 25 12:53:06 PM PST 24	659339144 ps
T914	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.494012301	Feb 25 12:52:30 PM PST 24	Feb 25 12:52:32 PM PST 24	421766158 ps
T915	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1674101176	Feb 25 12:52:25 PM PST 24	Feb 25 12:52:45 PM PST 24	46062745935 ps
T916	/workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3310066299	Feb 25 12:53:06 PM PST 24	Feb 25 12:53:08 PM PST 24	2550771399 ps
T917	/workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.999914334	Feb 25 12:53:08 PM PST 24	Feb 25 12:53:10 PM PST 24	2073327732 ps

Test location	/workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.88145212
Short name	T9
Test name
Test status
Simulation time	595735031888 ps
CPU time	330.39 seconds
Started	Feb 25 12:48:51 PM PST 24
Finished	Feb 25 12:54:21 PM PST 24
Peak memory	210048 kb
Host	smart-05cba7f2-793d-44a3-b58a-30cd1fee9fe2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88145212 -assert nopos tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.88145212
Directory	/workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_both.3756849081
Short name	T18
Test name
Test status
Simulation time	324705467605 ps
CPU time	377.4 seconds
Started	Feb 25 12:45:05 PM PST 24
Finished	Feb 25 12:51:23 PM PST 24
Peak memory	201464 kb
Host	smart-f2705802-79d6-4a32-8a86-a87e9a35f2b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3756849081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3756849081
Directory	/workspace/7.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/13.adc_ctrl_stress_all.2400433507
Short name	T127
Test name
Test status
Simulation time	437741997509 ps
CPU time	711.03 seconds
Started	Feb 25 12:45:14 PM PST 24
Finished	Feb 25 12:57:06 PM PST 24
Peak memory	201716 kb
Host	smart-c84360bd-4516-4d85-b643-84aea54e25ac
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400433507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all .2400433507
Directory	/workspace/13.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/34.adc_ctrl_clock_gating.3632013065
Short name	T13
Test name
Test status
Simulation time	502617956686 ps
CPU time	219.71 seconds
Started	Feb 25 12:47:13 PM PST 24
Finished	Feb 25 12:50:53 PM PST 24
Peak memory	200964 kb
Host	smart-e02c0267-fd1f-4e20-a10d-dd10268ea598
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632013065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat ing.3632013065
Directory	/workspace/34.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/41.adc_ctrl_clock_gating.1875530801
Short name	T128
Test name
Test status
Simulation time	487191736237 ps
CPU time	616.75 seconds
Started	Feb 25 12:48:14 PM PST 24
Finished	Feb 25 12:58:31 PM PST 24
Peak memory	201400 kb
Host	smart-10f616b5-c0b1-4760-96fe-bcaff95df184
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875530801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat ing.1875530801
Directory	/workspace/41.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/46.adc_ctrl_clock_gating.714116815
Short name	T117
Test name
Test status
Simulation time	493645896611 ps
CPU time	164.52 seconds
Started	Feb 25 12:48:30 PM PST 24
Finished	Feb 25 12:51:15 PM PST 24
Peak memory	201396 kb
Host	smart-0faea6ec-efe1-45b4-bcc5-4a1ee5de1ff7
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714116815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati ng.714116815
Directory	/workspace/46.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_both.295815228
Short name	T279
Test name
Test status
Simulation time	491489947200 ps
CPU time	273.78 seconds
Started	Feb 25 12:46:51 PM PST 24
Finished	Feb 25 12:51:25 PM PST 24
Peak memory	201504 kb
Host	smart-6067ca0a-d928-4a78-97dc-474f415cb490
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=295815228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.295815228
Directory	/workspace/32.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2459450175
Short name	T24
Test name
Test status
Simulation time	131129447248 ps
CPU time	163.61 seconds
Started	Feb 25 12:44:50 PM PST 24
Finished	Feb 25 12:47:34 PM PST 24
Peak memory	210064 kb
Host	smart-c15687ee-0629-45f4-a329-2fffb4bc96bf
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459450175 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2459450175
Directory	/workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_both.550134018
Short name	T250
Test name
Test status
Simulation time	489692859662 ps
CPU time	741.33 seconds
Started	Feb 25 12:47:23 PM PST 24
Finished	Feb 25 12:59:46 PM PST 24
Peak memory	201396 kb
Host	smart-b1104386-fab7-4857-9581-81a74c11296c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=550134018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.550134018
Directory	/workspace/37.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1910240297
Short name	T6
Test name
Test status
Simulation time	319382168600 ps
CPU time	385.46 seconds
Started	Feb 25 12:44:53 PM PST 24
Finished	Feb 25 12:51:18 PM PST 24
Peak memory	201476 kb
Host	smart-8c5d1837-38e6-4ce0-b1dd-fdd3090d1236
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910240297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup t_fixed.1910240297
Directory	/workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_both.2365422836
Short name	T116
Test name
Test status
Simulation time	494656751765 ps
CPU time	196.71 seconds
Started	Feb 25 12:45:00 PM PST 24
Finished	Feb 25 12:48:16 PM PST 24
Peak memory	201504 kb
Host	smart-b5554618-1928-44ef-a2e7-24359087ad9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2365422836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2365422836
Directory	/workspace/9.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1147330644
Short name	T54
Test name
Test status
Simulation time	117856070286 ps
CPU time	110.36 seconds
Started	Feb 25 12:48:23 PM PST 24
Finished	Feb 25 12:50:14 PM PST 24
Peak memory	210204 kb
Host	smart-17530358-0df7-43a7-9dfa-fc40a19e9ce1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147330644 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1147330644
Directory	/workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.adc_ctrl_clock_gating.953506302
Short name	T153
Test name
Test status
Simulation time	491078385194 ps
CPU time	58.31 seconds
Started	Feb 25 12:45:09 PM PST 24
Finished	Feb 25 12:46:07 PM PST 24
Peak memory	201456 kb
Host	smart-fd813ad0-3743-4da5-a81a-34d3daf5f556
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953506302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati ng.953506302
Directory	/workspace/10.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1049947080
Short name	T218
Test name
Test status
Simulation time	240845441842 ps
CPU time	123.79 seconds
Started	Feb 25 12:46:00 PM PST 24
Finished	Feb 25 12:48:04 PM PST 24
Peak memory	211152 kb
Host	smart-4b8184d7-897e-43f9-bf10-e82072c63df6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049947080 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1049947080
Directory	/workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.adc_ctrl_clock_gating.3877948879
Short name	T251
Test name
Test status
Simulation time	490003424164 ps
CPU time	352.74 seconds
Started	Feb 25 12:45:32 PM PST 24
Finished	Feb 25 12:51:25 PM PST 24
Peak memory	201524 kb
Host	smart-0bf1d95d-3b36-4c02-93bf-9d3a39ae8942
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877948879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat ing.3877948879
Directory	/workspace/15.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/0.adc_ctrl_alert_test.671037408
Short name	T39
Test name
Test status
Simulation time	536096843 ps
CPU time	0.94 seconds
Started	Feb 25 12:44:30 PM PST 24
Finished	Feb 25 12:44:32 PM PST 24
Peak memory	201128 kb
Host	smart-471c4b16-932d-4e99-a08c-6174b954f6fb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671037408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.671037408
Directory	/workspace/0.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1641650997
Short name	T33
Test name
Test status
Simulation time	604046510 ps
CPU time	2.48 seconds
Started	Feb 25 12:53:08 PM PST 24
Finished	Feb 25 12:53:10 PM PST 24
Peak memory	217544 kb
Host	smart-e941aeab-9651-4054-bbd3-67abfb3c2b18
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641650997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1641650997
Directory	/workspace/17.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2898547211
Short name	T86
Test name
Test status
Simulation time	407095451 ps
CPU time	2.02 seconds
Started	Feb 25 12:53:02 PM PST 24
Finished	Feb 25 12:53:04 PM PST 24
Peak memory	200872 kb
Host	smart-40b3c86b-af73-459d-921b-995a02d530ff
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898547211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2898547211
Directory	/workspace/13.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/default/0.adc_ctrl_sec_cm.279427079
Short name	T40
Test name
Test status
Simulation time	8105283627 ps
CPU time	19.37 seconds
Started	Feb 25 12:44:36 PM PST 24
Finished	Feb 25 12:44:56 PM PST 24
Peak memory	217476 kb
Host	smart-176c8d70-3c1f-4bfc-96af-13178638d733
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279427079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.279427079
Directory	/workspace/0.adc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/28.adc_ctrl_stress_all.3031464654
Short name	T173
Test name
Test status
Simulation time	660411954777 ps
CPU time	1272.78 seconds
Started	Feb 25 12:46:16 PM PST 24
Finished	Feb 25 01:07:29 PM PST 24
Peak memory	201528 kb
Host	smart-7853bf7e-099e-48cb-b609-42fccaeff171
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031464654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all .3031464654
Directory	/workspace/28.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/48.adc_ctrl_clock_gating.3935298160
Short name	T258
Test name
Test status
Simulation time	506913602372 ps
CPU time	585.33 seconds
Started	Feb 25 12:48:51 PM PST 24
Finished	Feb 25 12:58:37 PM PST 24
Peak memory	201392 kb
Host	smart-4b98f68f-1a49-4d0d-a509-8ef420968e6b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935298160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat ing.3935298160
Directory	/workspace/48.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_interrupt.584021080
Short name	T113
Test name
Test status
Simulation time	498454861146 ps
CPU time	531.87 seconds
Started	Feb 25 12:46:07 PM PST 24
Finished	Feb 25 12:54:59 PM PST 24
Peak memory	201600 kb
Host	smart-7932f413-9eb8-4437-adbf-c68bf99c2a60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=584021080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.584021080
Directory	/workspace/27.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_both.3193397971
Short name	T118
Test name
Test status
Simulation time	500841800078 ps
CPU time	354.18 seconds
Started	Feb 25 12:45:10 PM PST 24
Finished	Feb 25 12:51:04 PM PST 24
Peak memory	201540 kb
Host	smart-7032b254-a173-4314-90f0-5c0e4ac40ec7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3193397971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3193397971
Directory	/workspace/11.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/36.adc_ctrl_clock_gating.881452275
Short name	T176
Test name
Test status
Simulation time	333826122363 ps
CPU time	202.35 seconds
Started	Feb 25 12:47:15 PM PST 24
Finished	Feb 25 12:50:38 PM PST 24
Peak memory	201396 kb
Host	smart-1b3dd760-0120-432a-86d6-7b8c1e697de2
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881452275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati ng.881452275
Directory	/workspace/36.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2533438050
Short name	T55
Test name
Test status
Simulation time	715526176435 ps
CPU time	341.27 seconds
Started	Feb 25 12:44:26 PM PST 24
Finished	Feb 25 12:50:07 PM PST 24
Peak memory	210048 kb
Host	smart-484d95ba-bb55-4c70-9532-72d47c08cd68
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533438050 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2533438050
Directory	/workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.adc_ctrl_clock_gating.1855131936
Short name	T257
Test name
Test status
Simulation time	323357090561 ps
CPU time	407.09 seconds
Started	Feb 25 12:44:47 PM PST 24
Finished	Feb 25 12:51:34 PM PST 24
Peak memory	201520 kb
Host	smart-a584de6d-e67b-4053-a5e0-185adb654005
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855131936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati ng.1855131936
Directory	/workspace/3.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_both.813311148
Short name	T122
Test name
Test status
Simulation time	491656209310 ps
CPU time	170.55 seconds
Started	Feb 25 12:45:42 PM PST 24
Finished	Feb 25 12:48:33 PM PST 24
Peak memory	201504 kb
Host	smart-5dba1df9-1acb-459f-80cc-9bd0630ac3c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=813311148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.813311148
Directory	/workspace/20.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/40.adc_ctrl_clock_gating.1505844934
Short name	T272
Test name
Test status
Simulation time	503118260921 ps
CPU time	526.86 seconds
Started	Feb 25 12:47:52 PM PST 24
Finished	Feb 25 12:56:39 PM PST 24
Peak memory	201436 kb
Host	smart-466bd7f6-ee6d-4332-bb0a-27443e1af66f
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505844934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat ing.1505844934
Directory	/workspace/40.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_both.3802007866
Short name	T123
Test name
Test status
Simulation time	495521138397 ps
CPU time	308.93 seconds
Started	Feb 25 12:45:08 PM PST 24
Finished	Feb 25 12:50:17 PM PST 24
Peak memory	201500 kb
Host	smart-f820d08e-0a59-4ac1-9229-ffed3f693b1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3802007866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3802007866
Directory	/workspace/10.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_wakeup.3349718934
Short name	T158
Test name
Test status
Simulation time	499775156614 ps
CPU time	587.86 seconds
Started	Feb 25 12:44:49 PM PST 24
Finished	Feb 25 12:54:37 PM PST 24
Peak memory	201364 kb
Host	smart-9fede0a5-819b-4697-b3a5-a9fb90652770
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349718934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_ wakeup.3349718934
Directory	/workspace/6.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/16.adc_ctrl_clock_gating.3732690914
Short name	T4
Test name
Test status
Simulation time	158136128294 ps
CPU time	77.04 seconds
Started	Feb 25 12:45:43 PM PST 24
Finished	Feb 25 12:47:00 PM PST 24
Peak memory	201456 kb
Host	smart-b2926714-3f60-4680-913b-4b0d6737aea2
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732690914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat ing.3732690914
Directory	/workspace/16.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_both.3705497664
Short name	T111
Test name
Test status
Simulation time	320507162322 ps
CPU time	151.45 seconds
Started	Feb 25 12:46:04 PM PST 24
Finished	Feb 25 12:48:36 PM PST 24
Peak memory	201540 kb
Host	smart-ee64feec-0a69-44aa-939c-389d322dea7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3705497664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3705497664
Directory	/workspace/24.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.703829177
Short name	T225
Test name
Test status
Simulation time	5290158264 ps
CPU time	2.42 seconds
Started	Feb 25 12:52:37 PM PST 24
Finished	Feb 25 12:52:40 PM PST 24
Peak memory	201256 kb
Host	smart-77aae648-05bc-498e-862c-8767d2c18edc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703829177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int g_err.703829177
Directory	/workspace/5.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_both.1127370802
Short name	T119
Test name
Test status
Simulation time	501023451971 ps
CPU time	1172.4 seconds
Started	Feb 25 12:45:02 PM PST 24
Finished	Feb 25 01:04:35 PM PST 24
Peak memory	201468 kb
Host	smart-aa3b24df-ba41-4911-b226-f0772ad6f122
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1127370802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1127370802
Directory	/workspace/8.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.260049372
Short name	T29
Test name
Test status
Simulation time	2294569948 ps
CPU time	9.32 seconds
Started	Feb 25 12:52:46 PM PST 24
Finished	Feb 25 12:52:55 PM PST 24
Peak memory	200944 kb
Host	smart-0eaa5d54-dc26-4372-af27-1e8ab048bfbf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260049372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c trl_same_csr_outstanding.260049372
Directory	/workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_interrupt.2569929091
Short name	T280
Test name
Test status
Simulation time	493090957699 ps
CPU time	546.11 seconds
Started	Feb 25 12:44:36 PM PST 24
Finished	Feb 25 12:53:43 PM PST 24
Peak memory	201400 kb
Host	smart-f0ce9d24-d1c3-49e3-9d02-5f7c546f5f1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2569929091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2569929091
Directory	/workspace/1.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.4005482322
Short name	T74
Test name
Test status
Simulation time	111216671767 ps
CPU time	222.82 seconds
Started	Feb 25 12:46:04 PM PST 24
Finished	Feb 25 12:49:47 PM PST 24
Peak memory	209844 kb
Host	smart-f006c9c1-991f-4832-a450-8f97223311d0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005482322 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.4005482322
Directory	/workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.adc_ctrl_clock_gating.246823597
Short name	T301
Test name
Test status
Simulation time	502403185253 ps
CPU time	540.41 seconds
Started	Feb 25 12:46:50 PM PST 24
Finished	Feb 25 12:55:51 PM PST 24
Peak memory	201464 kb
Host	smart-73914bba-aa5c-4f23-a0ea-7b58c0dda98b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246823597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati ng.246823597
Directory	/workspace/32.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_wakeup.906314222
Short name	T276
Test name
Test status
Simulation time	497226410462 ps
CPU time	563.68 seconds
Started	Feb 25 12:45:16 PM PST 24
Finished	Feb 25 12:54:40 PM PST 24
Peak memory	201564 kb
Host	smart-3fa28fa0-c33a-43f2-965b-cdaafc870c8b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906314222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_ wakeup.906314222
Directory	/workspace/12.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/12.adc_ctrl_stress_all.390723751
Short name	T19
Test name
Test status
Simulation time	281311271130 ps
CPU time	478.39 seconds
Started	Feb 25 12:45:13 PM PST 24
Finished	Feb 25 12:53:12 PM PST 24
Peak memory	201760 kb
Host	smart-67150de1-2623-4291-be38-ed507b78a0c6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390723751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all. 390723751
Directory	/workspace/12.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.adc_ctrl_clock_gating.3961755732
Short name	T295
Test name
Test status
Simulation time	495105225442 ps
CPU time	717.61 seconds
Started	Feb 25 12:46:24 PM PST 24
Finished	Feb 25 12:58:22 PM PST 24
Peak memory	201420 kb
Host	smart-36487740-2c34-4f07-bb8a-ef4b2ceaecd8
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961755732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat ing.3961755732
Directory	/workspace/29.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/28.adc_ctrl_clock_gating.3193272994
Short name	T305
Test name
Test status
Simulation time	325841623341 ps
CPU time	369.55 seconds
Started	Feb 25 12:46:18 PM PST 24
Finished	Feb 25 12:52:28 PM PST 24
Peak memory	201484 kb
Host	smart-7f160663-2c7d-4711-8361-a06bd078947b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193272994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat ing.3193272994
Directory	/workspace/28.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_both.1452635739
Short name	T256
Test name
Test status
Simulation time	494728573140 ps
CPU time	297.07 seconds
Started	Feb 25 12:46:50 PM PST 24
Finished	Feb 25 12:51:48 PM PST 24
Peak memory	201568 kb
Host	smart-30c93f4f-cdc2-484d-82c4-8b224ec5578c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452635739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1452635739
Directory	/workspace/33.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_both.2974997165
Short name	T292
Test name
Test status
Simulation time	503331330712 ps
CPU time	283.07 seconds
Started	Feb 25 12:44:45 PM PST 24
Finished	Feb 25 12:49:28 PM PST 24
Peak memory	201572 kb
Host	smart-7c13ae28-9dea-4143-a8af-83b813cc53dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2974997165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2974997165
Directory	/workspace/3.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1459088473
Short name	T59
Test name
Test status
Simulation time	41752039407 ps
CPU time	86.1 seconds
Started	Feb 25 12:46:35 PM PST 24
Finished	Feb 25 12:48:02 PM PST 24
Peak memory	210084 kb
Host	smart-84e6db26-3033-410d-80b1-ed19b46fc472
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459088473 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1459088473
Directory	/workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.adc_ctrl_clock_gating.4181230372
Short name	T255
Test name
Test status
Simulation time	168449055306 ps
CPU time	174.91 seconds
Started	Feb 25 12:46:49 PM PST 24
Finished	Feb 25 12:49:44 PM PST 24
Peak memory	201540 kb
Host	smart-210457b0-98f0-47bf-8a2a-6fb447b62a3b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181230372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat ing.4181230372
Directory	/workspace/33.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2367697775
Short name	T837
Test name
Test status
Simulation time	1335604711 ps
CPU time	1.84 seconds
Started	Feb 25 12:53:06 PM PST 24
Finished	Feb 25 12:53:08 PM PST 24
Peak memory	201176 kb
Host	smart-9c8ebe02-1699-40dc-b646-1128e8e199fb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367697775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2367697775
Directory	/workspace/19.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/0.adc_ctrl_clock_gating.1387743891
Short name	T244
Test name
Test status
Simulation time	489036937836 ps
CPU time	1085.06 seconds
Started	Feb 25 12:44:26 PM PST 24
Finished	Feb 25 01:02:31 PM PST 24
Peak memory	201340 kb
Host	smart-745fa8ba-fa27-4887-9b67-5bd1b7ac426f
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387743891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati ng.1387743891
Directory	/workspace/0.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/10.adc_ctrl_fsm_reset.3012907707
Short name	T230
Test name
Test status
Simulation time	114441621378 ps
CPU time	582.56 seconds
Started	Feb 25 12:45:08 PM PST 24
Finished	Feb 25 12:54:51 PM PST 24
Peak memory	201844 kb
Host	smart-5c413c7c-ed77-4a06-8fe8-5fb237891a3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3012907707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3012907707
Directory	/workspace/10.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3641371756
Short name	T7
Test name
Test status
Simulation time	160053142026 ps
CPU time	53.86 seconds
Started	Feb 25 12:45:12 PM PST 24
Finished	Feb 25 12:46:05 PM PST 24
Peak memory	201472 kb
Host	smart-750beb2a-644b-4a46-b51f-397ba168c9b3
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641371756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13 .adc_ctrl_filters_wakeup_fixed.3641371756
Directory	/workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_both.1877488643
Short name	T163
Test name
Test status
Simulation time	498108074762 ps
CPU time	187.99 seconds
Started	Feb 25 12:46:36 PM PST 24
Finished	Feb 25 12:49:44 PM PST 24
Peak memory	201444 kb
Host	smart-ab4bc807-6c55-45b1-b42d-d0a8a981f031
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1877488643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1877488643
Directory	/workspace/30.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/35.adc_ctrl_clock_gating.1296018247
Short name	T203
Test name
Test status
Simulation time	160295228527 ps
CPU time	25.67 seconds
Started	Feb 25 12:47:06 PM PST 24
Finished	Feb 25 12:47:32 PM PST 24
Peak memory	201456 kb
Host	smart-3dbba8f9-17ea-46d2-b3c2-013138bb304c
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296018247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat ing.1296018247
Directory	/workspace/35.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/47.adc_ctrl_clock_gating.1613186175
Short name	T166
Test name
Test status
Simulation time	490278563296 ps
CPU time	152.65 seconds
Started	Feb 25 12:48:43 PM PST 24
Finished	Feb 25 12:51:16 PM PST 24
Peak memory	201564 kb
Host	smart-f4ba2343-2602-4a6f-9b6a-7452463eaa16
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613186175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat ing.1613186175
Directory	/workspace/47.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_interrupt.3158544384
Short name	T317
Test name
Test status
Simulation time	494091912294 ps
CPU time	1099.39 seconds
Started	Feb 25 12:44:53 PM PST 24
Finished	Feb 25 01:03:12 PM PST 24
Peak memory	201576 kb
Host	smart-08a5c115-eb63-470a-ad1e-6eb367c954f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3158544384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3158544384
Directory	/workspace/6.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.290570579
Short name	T342
Test name
Test status
Simulation time	144309811349 ps
CPU time	108.27 seconds
Started	Feb 25 12:46:28 PM PST 24
Finished	Feb 25 12:48:16 PM PST 24
Peak memory	210108 kb
Host	smart-9660f3cb-85bc-4421-b599-405db928b0e6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290570579 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.290570579
Directory	/workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.adc_ctrl_stress_all.651659915
Short name	T270
Test name
Test status
Simulation time	310503902202 ps
CPU time	621.23 seconds
Started	Feb 25 12:46:40 PM PST 24
Finished	Feb 25 12:57:01 PM PST 24
Peak memory	212164 kb
Host	smart-d9e033f1-e75c-4ce5-820c-ccf3b0bd2fed
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651659915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all. 651659915
Directory	/workspace/31.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.adc_ctrl_clock_gating.2699853958
Short name	T289
Test name
Test status
Simulation time	489396593181 ps
CPU time	281.91 seconds
Started	Feb 25 12:49:03 PM PST 24
Finished	Feb 25 12:53:45 PM PST 24
Peak memory	201400 kb
Host	smart-f0c9996b-4480-4c2f-9ef7-fb79505acdf7
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699853958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat ing.2699853958
Directory	/workspace/49.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/5.adc_ctrl_clock_gating.3351282327
Short name	T307
Test name
Test status
Simulation time	321467734106 ps
CPU time	166.61 seconds
Started	Feb 25 12:44:52 PM PST 24
Finished	Feb 25 12:47:39 PM PST 24
Peak memory	201464 kb
Host	smart-abaee951-af39-4ffb-9a12-e1ed787a25ae
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351282327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati ng.3351282327
Directory	/workspace/5.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_wakeup.2672657309
Short name	T275
Test name
Test status
Simulation time	496954940107 ps
CPU time	269.27 seconds
Started	Feb 25 12:45:07 PM PST 24
Finished	Feb 25 12:49:37 PM PST 24
Peak memory	201536 kb
Host	smart-7a1a025d-ae8a-4378-9002-60f530812517
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672657309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_ wakeup.2672657309
Directory	/workspace/7.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/0.adc_ctrl_fsm_reset.3347792246
Short name	T232
Test name
Test status
Simulation time	110647798916 ps
CPU time	605.05 seconds
Started	Feb 25 12:44:37 PM PST 24
Finished	Feb 25 12:54:42 PM PST 24
Peak memory	201832 kb
Host	smart-ba8a76f0-4298-4fa4-905d-e416d40de3dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3347792246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3347792246
Directory	/workspace/0.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_interrupt.4289499132
Short name	T277
Test name
Test status
Simulation time	331601428362 ps
CPU time	331.11 seconds
Started	Feb 25 12:45:07 PM PST 24
Finished	Feb 25 12:50:39 PM PST 24
Peak memory	201556 kb
Host	smart-df185c3d-5114-4ac0-ac9f-c73d7135cbd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4289499132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.4289499132
Directory	/workspace/10.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_both.3245048707
Short name	T331
Test name
Test status
Simulation time	476319015161 ps
CPU time	1208.99 seconds
Started	Feb 25 12:46:57 PM PST 24
Finished	Feb 25 01:07:06 PM PST 24
Peak memory	201604 kb
Host	smart-1ab97496-7edf-43a0-b2d8-ebf33a882815
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3245048707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3245048707
Directory	/workspace/34.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_interrupt.370012842
Short name	T197
Test name
Test status
Simulation time	490857860520 ps
CPU time	313.75 seconds
Started	Feb 25 12:47:21 PM PST 24
Finished	Feb 25 12:52:34 PM PST 24
Peak memory	201560 kb
Host	smart-c59fa44b-8e24-470e-8aa7-bd7b7dbe71a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=370012842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.370012842
Directory	/workspace/37.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_wakeup.1813715641
Short name	T344
Test name
Test status
Simulation time	503268492898 ps
CPU time	118.51 seconds
Started	Feb 25 12:44:49 PM PST 24
Finished	Feb 25 12:46:48 PM PST 24
Peak memory	201444 kb
Host	smart-70b30e05-ba3b-4249-94c5-0cce41e9402d
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813715641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_ wakeup.1813715641
Directory	/workspace/4.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_wakeup.3070531660
Short name	T293
Test name
Test status
Simulation time	165462381019 ps
CPU time	177.47 seconds
Started	Feb 25 12:47:57 PM PST 24
Finished	Feb 25 12:50:55 PM PST 24
Peak memory	201564 kb
Host	smart-0341863d-8268-48ee-a1e8-2cae68df339a
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070531660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters _wakeup.3070531660
Directory	/workspace/41.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1899679148
Short name	T265
Test name
Test status
Simulation time	226633827306 ps
CPU time	121.67 seconds
Started	Feb 25 12:48:21 PM PST 24
Finished	Feb 25 12:50:23 PM PST 24
Peak memory	210440 kb
Host	smart-a803d031-b4ea-4afd-a0bb-2d966483cf30
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899679148 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1899679148
Directory	/workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.adc_ctrl_fsm_reset.1467069010
Short name	T25
Test name
Test status
Simulation time	110472928966 ps
CPU time	312.91 seconds
Started	Feb 25 12:45:13 PM PST 24
Finished	Feb 25 12:50:26 PM PST 24
Peak memory	201784 kb
Host	smart-b079c169-a867-4733-93af-0240f3a1fce2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1467069010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1467069010
Directory	/workspace/9.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2023021670
Short name	T109
Test name
Test status
Simulation time	4080757106 ps
CPU time	3.43 seconds
Started	Feb 25 12:52:59 PM PST 24
Finished	Feb 25 12:53:03 PM PST 24
Peak memory	201172 kb
Host	smart-72c3e409-b08f-47e3-8afc-3fa0ce43c202
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023021670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i ntg_err.2023021670
Directory	/workspace/12.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_both.240079943
Short name	T319
Test name
Test status
Simulation time	494532317681 ps
CPU time	562.7 seconds
Started	Feb 25 12:45:12 PM PST 24
Finished	Feb 25 12:54:35 PM PST 24
Peak memory	201568 kb
Host	smart-6ed8be37-cd10-4e80-8382-235926675ed4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240079943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.240079943
Directory	/workspace/12.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/20.adc_ctrl_clock_gating.1144667149
Short name	T261
Test name
Test status
Simulation time	494021739072 ps
CPU time	286.78 seconds
Started	Feb 25 12:45:43 PM PST 24
Finished	Feb 25 12:50:31 PM PST 24
Peak memory	201520 kb
Host	smart-19cd204f-238c-4fa2-bbce-84389c7c2495
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144667149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat ing.1144667149
Directory	/workspace/20.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/35.adc_ctrl_fsm_reset.777434659
Short name	T26
Test name
Test status
Simulation time	110397097908 ps
CPU time	334.37 seconds
Started	Feb 25 12:47:13 PM PST 24
Finished	Feb 25 12:52:47 PM PST 24
Peak memory	201856 kb
Host	smart-17a589de-3745-45f9-9d4e-c4f8fa1d6ff7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=777434659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.777434659
Directory	/workspace/35.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_wakeup.1817925141
Short name	T198
Test name
Test status
Simulation time	334315421598 ps
CPU time	303.86 seconds
Started	Feb 25 12:48:11 PM PST 24
Finished	Feb 25 12:53:15 PM PST 24
Peak memory	201516 kb
Host	smart-14be3b86-f698-4886-b8d2-76be80bae612
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817925141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters _wakeup.1817925141
Directory	/workspace/42.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_interrupt.3533851777
Short name	T159
Test name
Test status
Simulation time	325444322461 ps
CPU time	191.7 seconds
Started	Feb 25 12:49:00 PM PST 24
Finished	Feb 25 12:52:12 PM PST 24
Peak memory	201416 kb
Host	smart-eae896a8-6e84-4013-8eed-bbf9cefadaa5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3533851777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3533851777
Directory	/workspace/49.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_both.2049752260
Short name	T112
Test name
Test status
Simulation time	329041385756 ps
CPU time	361.77 seconds
Started	Feb 25 12:44:34 PM PST 24
Finished	Feb 25 12:50:36 PM PST 24
Peak memory	201440 kb
Host	smart-a2d9045c-f16e-490b-b292-1b4e45ad7a88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2049752260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2049752260
Directory	/workspace/0.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_wakeup.1264377247
Short name	T297
Test name
Test status
Simulation time	492178118044 ps
CPU time	1149.28 seconds
Started	Feb 25 12:44:32 PM PST 24
Finished	Feb 25 01:03:41 PM PST 24
Peak memory	201352 kb
Host	smart-57321228-0ccf-4e6e-b134-219aae9f10b7
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264377247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_ wakeup.1264377247
Directory	/workspace/0.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_wakeup.1832312369
Short name	T259
Test name
Test status
Simulation time	328614394847 ps
CPU time	764.07 seconds
Started	Feb 25 12:45:06 PM PST 24
Finished	Feb 25 12:57:51 PM PST 24
Peak memory	201476 kb
Host	smart-18849b36-69ba-4352-8e03-fdd47e9ff0bb
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832312369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters _wakeup.1832312369
Directory	/workspace/10.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_both.1345155889
Short name	T217
Test name
Test status
Simulation time	334123116151 ps
CPU time	343.91 seconds
Started	Feb 25 12:45:18 PM PST 24
Finished	Feb 25 12:51:03 PM PST 24
Peak memory	201476 kb
Host	smart-b9a900b9-3240-4639-b4ee-ff5911f7e4aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1345155889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1345155889
Directory	/workspace/13.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_both.367791106
Short name	T286
Test name
Test status
Simulation time	330556895976 ps
CPU time	695.3 seconds
Started	Feb 25 12:45:28 PM PST 24
Finished	Feb 25 12:57:04 PM PST 24
Peak memory	201472 kb
Host	smart-43772ae7-7de9-43a4-ac53-b8781c4faab4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=367791106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.367791106
Directory	/workspace/17.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/22.adc_ctrl_stress_all.888309531
Short name	T336
Test name
Test status
Simulation time	215156014893 ps
CPU time	479.98 seconds
Started	Feb 25 12:45:55 PM PST 24
Finished	Feb 25 12:53:56 PM PST 24
Peak memory	201416 kb
Host	smart-5b0823f7-b6f3-46f8-9366-890096e9f9c3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888309531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all. 888309531
Directory	/workspace/22.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3627296515
Short name	T35
Test name
Test status
Simulation time	254759742003 ps
CPU time	442.97 seconds
Started	Feb 25 12:47:42 PM PST 24
Finished	Feb 25 12:55:05 PM PST 24
Peak memory	217504 kb
Host	smart-823d9179-7dca-40ea-a87f-38b9deeaffc9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627296515 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3627296515
Directory	/workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.adc_ctrl_clock_gating.3349741025
Short name	T183
Test name
Test status
Simulation time	335177896376 ps
CPU time	369.67 seconds
Started	Feb 25 12:48:33 PM PST 24
Finished	Feb 25 12:54:43 PM PST 24
Peak memory	201520 kb
Host	smart-c4a78038-01ef-4e66-8be2-6b9623269a70
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349741025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat ing.3349741025
Directory	/workspace/45.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/8.adc_ctrl_clock_gating.2844716721
Short name	T254
Test name
Test status
Simulation time	168969189092 ps
CPU time	161.23 seconds
Started	Feb 25 12:45:15 PM PST 24
Finished	Feb 25 12:47:56 PM PST 24
Peak memory	201524 kb
Host	smart-0cf1c53f-7036-42eb-9f01-ddd25cf11472
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844716721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati ng.2844716721
Directory	/workspace/8.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/8.adc_ctrl_fsm_reset.1405424951
Short name	T358
Test name
Test status
Simulation time	97068299231 ps
CPU time	361.95 seconds
Started	Feb 25 12:45:00 PM PST 24
Finished	Feb 25 12:51:02 PM PST 24
Peak memory	201816 kb
Host	smart-540d87f6-197c-41b9-b511-872cdf9c9e11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1405424951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1405424951
Directory	/workspace/8.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2270390294
Short name	T819
Test name
Test status
Simulation time	970537665 ps
CPU time	4.28 seconds
Started	Feb 25 12:52:24 PM PST 24
Finished	Feb 25 12:52:29 PM PST 24
Peak memory	201044 kb
Host	smart-bb7125a7-d833-41ef-9f9c-d496e4d0bc6e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270390294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia sing.2270390294
Directory	/workspace/0.adc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1674101176
Short name	T915
Test name
Test status
Simulation time	46062745935 ps
CPU time	19.41 seconds
Started	Feb 25 12:52:25 PM PST 24
Finished	Feb 25 12:52:45 PM PST 24
Peak memory	201260 kb
Host	smart-417680dc-f49f-4aef-aaea-3ea0e4817593
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674101176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_ bash.1674101176
Directory	/workspace/0.adc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.903162320
Short name	T903
Test name
Test status
Simulation time	707332217 ps
CPU time	0.85 seconds
Started	Feb 25 12:52:34 PM PST 24
Finished	Feb 25 12:52:36 PM PST 24
Peak memory	200820 kb
Host	smart-d95f9e48-1037-4b20-aa5e-0709b8471338
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903162320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re set.903162320
Directory	/workspace/0.adc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.638423651
Short name	T867
Test name
Test status
Simulation time	454923999 ps
CPU time	1.27 seconds
Started	Feb 25 12:52:29 PM PST 24
Finished	Feb 25 12:52:31 PM PST 24
Peak memory	217560 kb
Host	smart-fd6f0a2c-0912-4a04-b091-314005ae7719
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638423651 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.638423651
Directory	/workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2172547417
Short name	T891
Test name
Test status
Simulation time	364371258 ps
CPU time	1.41 seconds
Started	Feb 25 12:52:34 PM PST 24
Finished	Feb 25 12:52:36 PM PST 24
Peak memory	200816 kb
Host	smart-50008314-861c-4437-92c4-2731a390560d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172547417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2172547417
Directory	/workspace/0.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.591650066
Short name	T813
Test name
Test status
Simulation time	429608811 ps
CPU time	0.9 seconds
Started	Feb 25 12:52:29 PM PST 24
Finished	Feb 25 12:52:30 PM PST 24
Peak memory	200872 kb
Host	smart-41199eae-f997-4567-a953-85d915479134
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591650066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.591650066
Directory	/workspace/0.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1836618016
Short name	T909
Test name
Test status
Simulation time	2577183329 ps
CPU time	6.11 seconds
Started	Feb 25 12:52:24 PM PST 24
Finished	Feb 25 12:52:31 PM PST 24
Peak memory	200868 kb
Host	smart-9ac37e02-504a-491b-8f93-a96daf461cda
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836618016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c trl_same_csr_outstanding.1836618016
Directory	/workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3744816353
Short name	T906
Test name
Test status
Simulation time	558983203 ps
CPU time	3.34 seconds
Started	Feb 25 12:52:22 PM PST 24
Finished	Feb 25 12:52:26 PM PST 24
Peak memory	209336 kb
Host	smart-d0bb2395-2c1b-492f-9e86-601465eb3d22
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744816353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3744816353
Directory	/workspace/0.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.382370888
Short name	T805
Test name
Test status
Simulation time	4307869346 ps
CPU time	2.74 seconds
Started	Feb 25 12:52:30 PM PST 24
Finished	Feb 25 12:52:33 PM PST 24
Peak memory	201276 kb
Host	smart-0b07a1ef-9e03-41a6-8def-3438ccd2b877
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382370888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int g_err.382370888
Directory	/workspace/0.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4135007336
Short name	T94
Test name
Test status
Simulation time	537981640 ps
CPU time	1.59 seconds
Started	Feb 25 12:52:32 PM PST 24
Finished	Feb 25 12:52:33 PM PST 24
Peak memory	201148 kb
Host	smart-fa7186ee-3ca9-457c-a7f6-83ec8bd321cf
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135007336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia sing.4135007336
Directory	/workspace/1.adc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.750014661
Short name	T91
Test name
Test status
Simulation time	20901478827 ps
CPU time	15.61 seconds
Started	Feb 25 12:52:29 PM PST 24
Finished	Feb 25 12:52:45 PM PST 24
Peak memory	201160 kb
Host	smart-bd32bb22-8bfb-4961-a7cb-ce515b37120a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750014661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b ash.750014661
Directory	/workspace/1.adc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2094015405
Short name	T821
Test name
Test status
Simulation time	1261983616 ps
CPU time	1.45 seconds
Started	Feb 25 12:52:29 PM PST 24
Finished	Feb 25 12:52:31 PM PST 24
Peak memory	200828 kb
Host	smart-310dd278-51d7-424f-b5c8-1eb2c86fdd65
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094015405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r eset.2094015405
Directory	/workspace/1.adc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2561921876
Short name	T814
Test name
Test status
Simulation time	448740139 ps
CPU time	1.83 seconds
Started	Feb 25 12:52:30 PM PST 24
Finished	Feb 25 12:52:32 PM PST 24
Peak memory	200944 kb
Host	smart-4b677c30-d4d4-4cf3-949b-8a47f11e2029
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561921876 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2561921876
Directory	/workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2667489093
Short name	T862
Test name
Test status
Simulation time	482763928 ps
CPU time	1.07 seconds
Started	Feb 25 12:52:26 PM PST 24
Finished	Feb 25 12:52:28 PM PST 24
Peak memory	200896 kb
Host	smart-66daa216-2f3f-4d4b-a562-14d0a52492d1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667489093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2667489093
Directory	/workspace/1.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1061400929
Short name	T830
Test name
Test status
Simulation time	484496582 ps
CPU time	0.9 seconds
Started	Feb 25 12:52:30 PM PST 24
Finished	Feb 25 12:52:32 PM PST 24
Peak memory	200724 kb
Host	smart-8d0b604f-337c-4ed7-9e22-2c739f9e9a21
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061400929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1061400929
Directory	/workspace/1.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2302099513
Short name	T861
Test name
Test status
Simulation time	2237996575 ps
CPU time	2.06 seconds
Started	Feb 25 12:52:27 PM PST 24
Finished	Feb 25 12:52:30 PM PST 24
Peak memory	200944 kb
Host	smart-12ba6069-b7d9-4242-ab09-66bc351ccba2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302099513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c trl_same_csr_outstanding.2302099513
Directory	/workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.573660594
Short name	T822
Test name
Test status
Simulation time	813872208 ps
CPU time	2.54 seconds
Started	Feb 25 12:52:25 PM PST 24
Finished	Feb 25 12:52:28 PM PST 24
Peak memory	210456 kb
Host	smart-422f53b1-d41f-46e1-b26d-036bc319a002
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573660594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.573660594
Directory	/workspace/1.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1243944379
Short name	T833
Test name
Test status
Simulation time	4056315238 ps
CPU time	10.6 seconds
Started	Feb 25 12:52:26 PM PST 24
Finished	Feb 25 12:52:37 PM PST 24
Peak memory	201236 kb
Host	smart-ceb3ca8e-a83b-4bb3-be5d-a63de3150371
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243944379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in tg_err.1243944379
Directory	/workspace/1.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1556482675
Short name	T80
Test name
Test status
Simulation time	439904643 ps
CPU time	1.17 seconds
Started	Feb 25 12:52:46 PM PST 24
Finished	Feb 25 12:52:47 PM PST 24
Peak memory	200932 kb
Host	smart-0a70c8ef-06e7-4e3f-9da3-23b1388a350b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556482675 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1556482675
Directory	/workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.272293490
Short name	T96
Test name
Test status
Simulation time	333881782 ps
CPU time	1.14 seconds
Started	Feb 25 12:52:47 PM PST 24
Finished	Feb 25 12:52:48 PM PST 24
Peak memory	200884 kb
Host	smart-c560c5bb-3b95-4a91-adc2-43dd32f53124
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272293490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.272293490
Directory	/workspace/10.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3028594388
Short name	T874
Test name
Test status
Simulation time	545587318 ps
CPU time	0.81 seconds
Started	Feb 25 12:52:48 PM PST 24
Finished	Feb 25 12:52:49 PM PST 24
Peak memory	200804 kb
Host	smart-a4526916-9d4e-4eef-b798-3306a094b533
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028594388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3028594388
Directory	/workspace/10.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2058988913
Short name	T79
Test name
Test status
Simulation time	573259673 ps
CPU time	2.18 seconds
Started	Feb 25 12:52:53 PM PST 24
Finished	Feb 25 12:52:55 PM PST 24
Peak memory	201128 kb
Host	smart-3720b990-65c9-4862-87a8-06cc7f4bf4e9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058988913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2058988913
Directory	/workspace/10.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.283885262
Short name	T815
Test name
Test status
Simulation time	4540779380 ps
CPU time	12.71 seconds
Started	Feb 25 12:52:48 PM PST 24
Finished	Feb 25 12:53:01 PM PST 24
Peak memory	201296 kb
Host	smart-1bd82264-28c2-4bd2-9747-aba875a6779a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283885262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in tg_err.283885262
Directory	/workspace/10.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3043903173
Short name	T78
Test name
Test status
Simulation time	473724313 ps
CPU time	1.56 seconds
Started	Feb 25 12:53:00 PM PST 24
Finished	Feb 25 12:53:02 PM PST 24
Peak memory	200876 kb
Host	smart-4349a38d-0520-4aea-9194-80472f0eaef2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043903173 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3043903173
Directory	/workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1153514089
Short name	T864
Test name
Test status
Simulation time	406872611 ps
CPU time	1.64 seconds
Started	Feb 25 12:52:58 PM PST 24
Finished	Feb 25 12:53:00 PM PST 24
Peak memory	200820 kb
Host	smart-45bb62d9-4c73-4dd3-97d2-e8010ab1e660
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153514089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1153514089
Directory	/workspace/11.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1092496591
Short name	T882
Test name
Test status
Simulation time	351870539 ps
CPU time	1.46 seconds
Started	Feb 25 12:53:00 PM PST 24
Finished	Feb 25 12:53:02 PM PST 24
Peak memory	200700 kb
Host	smart-09c34154-b994-4709-8db0-d0832c8d167a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092496591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1092496591
Directory	/workspace/11.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1473221413
Short name	T835
Test name
Test status
Simulation time	4851167789 ps
CPU time	2.88 seconds
Started	Feb 25 12:53:03 PM PST 24
Finished	Feb 25 12:53:06 PM PST 24
Peak memory	201200 kb
Host	smart-be686e7b-d4b3-4f70-9cd6-ffd3fc25ab23
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473221413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ ctrl_same_csr_outstanding.1473221413
Directory	/workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.4194086540
Short name	T77
Test name
Test status
Simulation time	412007980 ps
CPU time	1.74 seconds
Started	Feb 25 12:52:46 PM PST 24
Finished	Feb 25 12:52:48 PM PST 24
Peak memory	201180 kb
Host	smart-d1419276-d9bb-4e77-a8b5-a887d4719647
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194086540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.4194086540
Directory	/workspace/11.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1917412940
Short name	T824
Test name
Test status
Simulation time	8457065964 ps
CPU time	7.04 seconds
Started	Feb 25 12:53:02 PM PST 24
Finished	Feb 25 12:53:09 PM PST 24
Peak memory	201152 kb
Host	smart-858e6206-5135-4bf3-83eb-881f1e34a9af
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917412940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i ntg_err.1917412940
Directory	/workspace/11.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4129310491
Short name	T908
Test name
Test status
Simulation time	583585077 ps
CPU time	1.79 seconds
Started	Feb 25 12:53:02 PM PST 24
Finished	Feb 25 12:53:04 PM PST 24
Peak memory	200912 kb
Host	smart-fbc67804-896e-44de-aa18-7c27520e8372
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129310491 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.4129310491
Directory	/workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1095866320
Short name	T863
Test name
Test status
Simulation time	604553168 ps
CPU time	1.29 seconds
Started	Feb 25 12:53:03 PM PST 24
Finished	Feb 25 12:53:05 PM PST 24
Peak memory	200900 kb
Host	smart-8b934b8d-d32a-408b-b278-aeb86c007875
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095866320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1095866320
Directory	/workspace/12.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3672867026
Short name	T827
Test name
Test status
Simulation time	417280686 ps
CPU time	0.93 seconds
Started	Feb 25 12:52:59 PM PST 24
Finished	Feb 25 12:53:00 PM PST 24
Peak memory	200584 kb
Host	smart-a5f3922e-2775-4b69-aa94-752087191d2e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672867026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3672867026
Directory	/workspace/12.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.624327739
Short name	T98
Test name
Test status
Simulation time	4419258799 ps
CPU time	2.07 seconds
Started	Feb 25 12:52:58 PM PST 24
Finished	Feb 25 12:53:00 PM PST 24
Peak memory	201236 kb
Host	smart-ae4e48ab-293f-4439-9cf1-445f24a28fc1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624327739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c trl_same_csr_outstanding.624327739
Directory	/workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2618036834
Short name	T879
Test name
Test status
Simulation time	496226826 ps
CPU time	2.04 seconds
Started	Feb 25 12:53:02 PM PST 24
Finished	Feb 25 12:53:04 PM PST 24
Peak memory	209356 kb
Host	smart-5fd63e57-3f73-441a-94db-274c1d1d5ebd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618036834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2618036834
Directory	/workspace/12.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.505948443
Short name	T825
Test name
Test status
Simulation time	654470112 ps
CPU time	1.73 seconds
Started	Feb 25 12:53:05 PM PST 24
Finished	Feb 25 12:53:07 PM PST 24
Peak memory	200948 kb
Host	smart-9a431082-3389-469a-a157-71dea7e2262b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505948443 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.505948443
Directory	/workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1520209602
Short name	T807
Test name
Test status
Simulation time	469532845 ps
CPU time	0.89 seconds
Started	Feb 25 12:53:03 PM PST 24
Finished	Feb 25 12:53:04 PM PST 24
Peak memory	200876 kb
Host	smart-0103fa2a-d9b9-4372-8e73-04240202a2b4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520209602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1520209602
Directory	/workspace/13.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2033896937
Short name	T842
Test name
Test status
Simulation time	2501189852 ps
CPU time	3.02 seconds
Started	Feb 25 12:53:02 PM PST 24
Finished	Feb 25 12:53:06 PM PST 24
Peak memory	200944 kb
Host	smart-e1e2f2b5-50e0-4a9f-87cf-d41f750ea24c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033896937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ ctrl_same_csr_outstanding.2033896937
Directory	/workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.668428859
Short name	T853
Test name
Test status
Simulation time	366431741 ps
CPU time	1.55 seconds
Started	Feb 25 12:52:59 PM PST 24
Finished	Feb 25 12:53:00 PM PST 24
Peak memory	201176 kb
Host	smart-c712a6d1-3941-4457-b6a5-a20b191ef32a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668428859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.668428859
Directory	/workspace/13.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2269536871
Short name	T895
Test name
Test status
Simulation time	7690087591 ps
CPU time	20.03 seconds
Started	Feb 25 12:53:01 PM PST 24
Finished	Feb 25 12:53:21 PM PST 24
Peak memory	201152 kb
Host	smart-fc1128c0-e9da-422b-99ef-a94f0a625255
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269536871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i ntg_err.2269536871
Directory	/workspace/13.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2740388458
Short name	T76
Test name
Test status
Simulation time	444811155 ps
CPU time	1.22 seconds
Started	Feb 25 12:53:06 PM PST 24
Finished	Feb 25 12:53:08 PM PST 24
Peak memory	200884 kb
Host	smart-6e909c4c-fc65-4b4a-81e6-79b3281c402d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740388458 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2740388458
Directory	/workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2523140089
Short name	T866
Test name
Test status
Simulation time	482869196 ps
CPU time	0.81 seconds
Started	Feb 25 12:53:03 PM PST 24
Finished	Feb 25 12:53:04 PM PST 24
Peak memory	200896 kb
Host	smart-0169b276-2f60-4e54-ac03-4547fc144d74
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523140089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2523140089
Directory	/workspace/14.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3985436529
Short name	T898
Test name
Test status
Simulation time	435870005 ps
CPU time	0.91 seconds
Started	Feb 25 12:53:04 PM PST 24
Finished	Feb 25 12:53:05 PM PST 24
Peak memory	200700 kb
Host	smart-04e33dfc-ce9e-4c8c-869b-3a496293070c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985436529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3985436529
Directory	/workspace/14.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1599288854
Short name	T871
Test name
Test status
Simulation time	5140517041 ps
CPU time	6.63 seconds
Started	Feb 25 12:53:06 PM PST 24
Finished	Feb 25 12:53:13 PM PST 24
Peak memory	201132 kb
Host	smart-060f5218-7180-4db9-8c25-c8a51a5f4a81
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599288854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ ctrl_same_csr_outstanding.1599288854
Directory	/workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2520844960
Short name	T912
Test name
Test status
Simulation time	312663661 ps
CPU time	3.41 seconds
Started	Feb 25 12:53:04 PM PST 24
Finished	Feb 25 12:53:08 PM PST 24
Peak memory	209376 kb
Host	smart-36aef3a1-109c-4e9e-9b07-2877b8cef6c4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520844960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2520844960
Directory	/workspace/14.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2170882474
Short name	T829
Test name
Test status
Simulation time	9146476087 ps
CPU time	3.93 seconds
Started	Feb 25 12:53:03 PM PST 24
Finished	Feb 25 12:53:07 PM PST 24
Peak memory	201220 kb
Host	smart-41733365-abc8-4383-9826-35a716c08a07
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170882474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i ntg_err.2170882474
Directory	/workspace/14.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2766456610
Short name	T36
Test name
Test status
Simulation time	539257226 ps
CPU time	2.09 seconds
Started	Feb 25 12:53:03 PM PST 24
Finished	Feb 25 12:53:05 PM PST 24
Peak memory	200956 kb
Host	smart-34590903-0b34-4fd6-8c9a-a661da5ee82d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766456610 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2766456610
Directory	/workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.371699872
Short name	T100
Test name
Test status
Simulation time	527283612 ps
CPU time	0.81 seconds
Started	Feb 25 12:53:04 PM PST 24
Finished	Feb 25 12:53:05 PM PST 24
Peak memory	200884 kb
Host	smart-6c2b0b66-c6bc-4e05-94c0-9d5a2e0f85c2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371699872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.371699872
Directory	/workspace/15.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.4289617817
Short name	T880
Test name
Test status
Simulation time	345303382 ps
CPU time	0.95 seconds
Started	Feb 25 12:53:05 PM PST 24
Finished	Feb 25 12:53:06 PM PST 24
Peak memory	200904 kb
Host	smart-551e9ec5-a95b-4369-b969-218fb4a615ad
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289617817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.4289617817
Directory	/workspace/15.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.906620040
Short name	T907
Test name
Test status
Simulation time	2346819514 ps
CPU time	1.44 seconds
Started	Feb 25 12:53:05 PM PST 24
Finished	Feb 25 12:53:07 PM PST 24
Peak memory	200956 kb
Host	smart-bfed5ddf-16b8-4e85-ae62-45399ef99845
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906620040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c trl_same_csr_outstanding.906620040
Directory	/workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.88501053
Short name	T913
Test name
Test status
Simulation time	659339144 ps
CPU time	2 seconds
Started	Feb 25 12:53:03 PM PST 24
Finished	Feb 25 12:53:06 PM PST 24
Peak memory	201196 kb
Host	smart-a593dfaa-c133-422d-84b3-61474286b806
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88501053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.88501053
Directory	/workspace/15.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3069264459
Short name	T896
Test name
Test status
Simulation time	10958490193 ps
CPU time	3.66 seconds
Started	Feb 25 12:53:05 PM PST 24
Finished	Feb 25 12:53:08 PM PST 24
Peak memory	201284 kb
Host	smart-2f3c0ece-9438-4e61-87a4-76124fb4eb0a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069264459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i ntg_err.3069264459
Directory	/workspace/15.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2822822155
Short name	T832
Test name
Test status
Simulation time	506658509 ps
CPU time	1.28 seconds
Started	Feb 25 12:53:04 PM PST 24
Finished	Feb 25 12:53:05 PM PST 24
Peak memory	200884 kb
Host	smart-a214b5f7-b16d-468b-a9e1-b8ffd15c5d8f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822822155 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2822822155
Directory	/workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.295546772
Short name	T102
Test name
Test status
Simulation time	338201410 ps
CPU time	1.04 seconds
Started	Feb 25 12:53:04 PM PST 24
Finished	Feb 25 12:53:05 PM PST 24
Peak memory	200824 kb
Host	smart-94eaee33-2eb4-4b75-89df-6991b3fcbab4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295546772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.295546772
Directory	/workspace/16.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1183988225
Short name	T817
Test name
Test status
Simulation time	545961670 ps
CPU time	1 seconds
Started	Feb 25 12:53:06 PM PST 24
Finished	Feb 25 12:53:07 PM PST 24
Peak memory	200884 kb
Host	smart-d438219f-d8ec-421b-9076-86f31b7d3ef4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183988225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1183988225
Directory	/workspace/16.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.999914334
Short name	T917
Test name
Test status
Simulation time	2073327732 ps
CPU time	2.08 seconds
Started	Feb 25 12:53:08 PM PST 24
Finished	Feb 25 12:53:10 PM PST 24
Peak memory	200912 kb
Host	smart-48e03fe9-35a1-429a-af49-95851cbe23db
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999914334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c trl_same_csr_outstanding.999914334
Directory	/workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.758061739
Short name	T855
Test name
Test status
Simulation time	531451413 ps
CPU time	2.49 seconds
Started	Feb 25 12:53:06 PM PST 24
Finished	Feb 25 12:53:09 PM PST 24
Peak memory	209308 kb
Host	smart-8b6d3f2c-81ea-4e71-8bff-dcc25e0395f5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758061739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.758061739
Directory	/workspace/16.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3757845470
Short name	T876
Test name
Test status
Simulation time	8467896650 ps
CPU time	5.58 seconds
Started	Feb 25 12:53:06 PM PST 24
Finished	Feb 25 12:53:11 PM PST 24
Peak memory	201276 kb
Host	smart-d5bab856-e090-4e25-a707-0b2f7f2d4710
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757845470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i ntg_err.3757845470
Directory	/workspace/16.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2583183185
Short name	T843
Test name
Test status
Simulation time	457807622 ps
CPU time	1.34 seconds
Started	Feb 25 12:53:05 PM PST 24
Finished	Feb 25 12:53:06 PM PST 24
Peak memory	200892 kb
Host	smart-ab0eb139-43b2-4da1-8c8b-becedd3e7734
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583183185 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2583183185
Directory	/workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2677580812
Short name	T85
Test name
Test status
Simulation time	456591784 ps
CPU time	0.91 seconds
Started	Feb 25 12:53:04 PM PST 24
Finished	Feb 25 12:53:05 PM PST 24
Peak memory	200880 kb
Host	smart-3cc98f7f-2d7b-4ab9-9f84-54301cb54cd6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677580812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2677580812
Directory	/workspace/17.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.534484025
Short name	T873
Test name
Test status
Simulation time	453931520 ps
CPU time	1.74 seconds
Started	Feb 25 12:53:05 PM PST 24
Finished	Feb 25 12:53:06 PM PST 24
Peak memory	200624 kb
Host	smart-26289e34-aa3d-4c64-b075-8a48b2720b56
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534484025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.534484025
Directory	/workspace/17.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.327534104
Short name	T27
Test name
Test status
Simulation time	4641389483 ps
CPU time	3.74 seconds
Started	Feb 25 12:53:09 PM PST 24
Finished	Feb 25 12:53:13 PM PST 24
Peak memory	201196 kb
Host	smart-518ec2d6-2c86-4065-b921-70c8bd9b121f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327534104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c trl_same_csr_outstanding.327534104
Directory	/workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1721962318
Short name	T104
Test name
Test status
Simulation time	8482335553 ps
CPU time	23.34 seconds
Started	Feb 25 12:53:04 PM PST 24
Finished	Feb 25 12:53:27 PM PST 24
Peak memory	201192 kb
Host	smart-eb71ebf9-0534-4432-b426-84f92a6411de
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721962318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i ntg_err.1721962318
Directory	/workspace/17.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1974688572
Short name	T850
Test name
Test status
Simulation time	956375664 ps
CPU time	1.24 seconds
Started	Feb 25 12:53:04 PM PST 24
Finished	Feb 25 12:53:05 PM PST 24
Peak memory	200888 kb
Host	smart-ab4647af-6003-4ee6-b09b-eac79b5b7bed
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974688572 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1974688572
Directory	/workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2798731110
Short name	T90
Test name
Test status
Simulation time	443224882 ps
CPU time	1.87 seconds
Started	Feb 25 12:53:03 PM PST 24
Finished	Feb 25 12:53:05 PM PST 24
Peak memory	200884 kb
Host	smart-14bb3d40-8ae0-462f-874f-c82f24c3bfd0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798731110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2798731110
Directory	/workspace/18.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1267899625
Short name	T841
Test name
Test status
Simulation time	478495627 ps
CPU time	0.98 seconds
Started	Feb 25 12:53:03 PM PST 24
Finished	Feb 25 12:53:04 PM PST 24
Peak memory	200892 kb
Host	smart-ad5c3e54-f0d3-4b7a-a297-a8c549cf851f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267899625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1267899625
Directory	/workspace/18.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.910778873
Short name	T901
Test name
Test status
Simulation time	2665791460 ps
CPU time	3.54 seconds
Started	Feb 25 12:53:03 PM PST 24
Finished	Feb 25 12:53:06 PM PST 24
Peak memory	200960 kb
Host	smart-b2703877-3737-409f-8e67-e4d4038479ed
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910778873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c trl_same_csr_outstanding.910778873
Directory	/workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2895982365
Short name	T820
Test name
Test status
Simulation time	679747874 ps
CPU time	2.68 seconds
Started	Feb 25 12:53:09 PM PST 24
Finished	Feb 25 12:53:12 PM PST 24
Peak memory	201156 kb
Host	smart-2f7ab4fa-facd-4f74-8332-6ac4268679a3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895982365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2895982365
Directory	/workspace/18.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.321426900
Short name	T226
Test name
Test status
Simulation time	4214720244 ps
CPU time	6.23 seconds
Started	Feb 25 12:53:03 PM PST 24
Finished	Feb 25 12:53:09 PM PST 24
Peak memory	201092 kb
Host	smart-55474421-8132-435c-9561-6ed4b9d5e10e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321426900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in tg_err.321426900
Directory	/workspace/18.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3924162007
Short name	T834
Test name
Test status
Simulation time	486541359 ps
CPU time	2.18 seconds
Started	Feb 25 12:53:07 PM PST 24
Finished	Feb 25 12:53:10 PM PST 24
Peak memory	200892 kb
Host	smart-dfc11f79-b427-4d18-80c2-90826a268f26
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924162007 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3924162007
Directory	/workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3541293572
Short name	T84
Test name
Test status
Simulation time	384313515 ps
CPU time	1.22 seconds
Started	Feb 25 12:53:07 PM PST 24
Finished	Feb 25 12:53:09 PM PST 24
Peak memory	200764 kb
Host	smart-cea940b3-acb3-4b8d-a580-89cc9fac0513
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541293572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3541293572
Directory	/workspace/19.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1018090771
Short name	T818
Test name
Test status
Simulation time	365187875 ps
CPU time	1.32 seconds
Started	Feb 25 12:53:06 PM PST 24
Finished	Feb 25 12:53:08 PM PST 24
Peak memory	200808 kb
Host	smart-e32f0bff-f74b-4aae-a921-a12b78f15070
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018090771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1018090771
Directory	/workspace/19.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3310066299
Short name	T916
Test name
Test status
Simulation time	2550771399 ps
CPU time	2.26 seconds
Started	Feb 25 12:53:06 PM PST 24
Finished	Feb 25 12:53:08 PM PST 24
Peak memory	200892 kb
Host	smart-887c1480-5fea-4979-ba59-a4ad1c2919e6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310066299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ ctrl_same_csr_outstanding.3310066299
Directory	/workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1757087873
Short name	T844
Test name
Test status
Simulation time	4516463526 ps
CPU time	4.26 seconds
Started	Feb 25 12:53:03 PM PST 24
Finished	Feb 25 12:53:07 PM PST 24
Peak memory	201228 kb
Host	smart-90c58566-c00c-4f1f-a4ac-cb61ddde327c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757087873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i ntg_err.1757087873
Directory	/workspace/19.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.865948015
Short name	T910
Test name
Test status
Simulation time	754467421 ps
CPU time	1.91 seconds
Started	Feb 25 12:52:33 PM PST 24
Finished	Feb 25 12:52:35 PM PST 24
Peak memory	201144 kb
Host	smart-80f7eac1-4c40-44fa-91b1-8ce0b887e55b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865948015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias ing.865948015
Directory	/workspace/2.adc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4194619465
Short name	T101
Test name
Test status
Simulation time	51935857731 ps
CPU time	118.45 seconds
Started	Feb 25 12:52:31 PM PST 24
Finished	Feb 25 12:54:30 PM PST 24
Peak memory	201196 kb
Host	smart-4a554eb9-18f9-40db-8436-dc102ef9734b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194619465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_ bash.4194619465
Directory	/workspace/2.adc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3573571493
Short name	T889
Test name
Test status
Simulation time	1172168515 ps
CPU time	3.53 seconds
Started	Feb 25 12:52:39 PM PST 24
Finished	Feb 25 12:52:43 PM PST 24
Peak memory	200828 kb
Host	smart-3d5b7009-b89b-4fe7-8ff3-1e637780e144
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573571493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r eset.3573571493
Directory	/workspace/2.adc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.494012301
Short name	T914
Test name
Test status
Simulation time	421766158 ps
CPU time	1.76 seconds
Started	Feb 25 12:52:30 PM PST 24
Finished	Feb 25 12:52:32 PM PST 24
Peak memory	200888 kb
Host	smart-096179dd-e81f-45bd-9a55-41e9f4952989
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494012301 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.494012301
Directory	/workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1994204475
Short name	T92
Test name
Test status
Simulation time	561259268 ps
CPU time	1 seconds
Started	Feb 25 12:52:34 PM PST 24
Finished	Feb 25 12:52:36 PM PST 24
Peak memory	200872 kb
Host	smart-cdf7fa37-9daf-4119-92e5-90086bb2f118
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994204475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1994204475
Directory	/workspace/2.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3825830764
Short name	T801
Test name
Test status
Simulation time	501028330 ps
CPU time	0.74 seconds
Started	Feb 25 12:52:38 PM PST 24
Finished	Feb 25 12:52:39 PM PST 24
Peak memory	200648 kb
Host	smart-556caa68-c2a5-4260-aad7-872b2b3ed2c4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825830764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3825830764
Directory	/workspace/2.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2163496578
Short name	T845
Test name
Test status
Simulation time	5198436242 ps
CPU time	11.83 seconds
Started	Feb 25 12:52:32 PM PST 24
Finished	Feb 25 12:52:44 PM PST 24
Peak memory	201252 kb
Host	smart-45d69ad5-969f-4ff4-a29b-513530f12b38
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163496578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c trl_same_csr_outstanding.2163496578
Directory	/workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4218579929
Short name	T32
Test name
Test status
Simulation time	499775312 ps
CPU time	1.36 seconds
Started	Feb 25 12:52:23 PM PST 24
Finished	Feb 25 12:52:25 PM PST 24
Peak memory	201156 kb
Host	smart-4af7fc5b-6113-42da-be78-c201378060ec
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218579929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.4218579929
Directory	/workspace/2.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.12852858
Short name	T105
Test name
Test status
Simulation time	4543993306 ps
CPU time	3.45 seconds
Started	Feb 25 12:52:24 PM PST 24
Finished	Feb 25 12:52:28 PM PST 24
Peak memory	201176 kb
Host	smart-cd502420-f847-4995-8a56-d47e065578b4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12852858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_intg _err.12852858
Directory	/workspace/2.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3000239664
Short name	T846
Test name
Test status
Simulation time	476865540 ps
CPU time	1.21 seconds
Started	Feb 25 12:53:04 PM PST 24
Finished	Feb 25 12:53:05 PM PST 24
Peak memory	200732 kb
Host	smart-3d89c532-2884-458d-8788-cd74ad2fb16d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000239664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3000239664
Directory	/workspace/20.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3335920031
Short name	T869
Test name
Test status
Simulation time	474238481 ps
CPU time	0.93 seconds
Started	Feb 25 12:53:11 PM PST 24
Finished	Feb 25 12:53:12 PM PST 24
Peak memory	200640 kb
Host	smart-b6a39b1c-4659-4cc4-94e1-64943da85229
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335920031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3335920031
Directory	/workspace/21.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.269332307
Short name	T809
Test name
Test status
Simulation time	366675864 ps
CPU time	0.84 seconds
Started	Feb 25 12:53:08 PM PST 24
Finished	Feb 25 12:53:09 PM PST 24
Peak memory	200900 kb
Host	smart-48673aa8-0ec7-4052-9eb7-e0590ff2aead
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269332307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.269332307
Directory	/workspace/22.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3774023200
Short name	T838
Test name
Test status
Simulation time	405889032 ps
CPU time	1.65 seconds
Started	Feb 25 12:53:06 PM PST 24
Finished	Feb 25 12:53:08 PM PST 24
Peak memory	200628 kb
Host	smart-93a6d574-74d5-4eb5-80b9-2c64a14f4b3d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774023200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3774023200
Directory	/workspace/23.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1559226029
Short name	T899
Test name
Test status
Simulation time	388805271 ps
CPU time	1.48 seconds
Started	Feb 25 12:53:11 PM PST 24
Finished	Feb 25 12:53:13 PM PST 24
Peak memory	200796 kb
Host	smart-1de0fa36-ffa5-43dd-b9a3-08264546afb5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559226029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1559226029
Directory	/workspace/24.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2969493721
Short name	T808
Test name
Test status
Simulation time	450281696 ps
CPU time	0.79 seconds
Started	Feb 25 12:53:04 PM PST 24
Finished	Feb 25 12:53:04 PM PST 24
Peak memory	200860 kb
Host	smart-7e276a88-763c-4fdf-8b89-a1b427f0d436
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969493721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2969493721
Directory	/workspace/25.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2477494487
Short name	T859
Test name
Test status
Simulation time	483412423 ps
CPU time	1.16 seconds
Started	Feb 25 12:53:11 PM PST 24
Finished	Feb 25 12:53:12 PM PST 24
Peak memory	200852 kb
Host	smart-ebdd3b7f-91c6-4937-ad28-7029c0d0614f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477494487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2477494487
Directory	/workspace/26.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.4264643196
Short name	T858
Test name
Test status
Simulation time	355243833 ps
CPU time	1.52 seconds
Started	Feb 25 12:53:09 PM PST 24
Finished	Feb 25 12:53:10 PM PST 24
Peak memory	200068 kb
Host	smart-008108c2-25c3-4006-9f6c-b403a681f9bf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264643196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.4264643196
Directory	/workspace/27.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.327975737
Short name	T854
Test name
Test status
Simulation time	456334983 ps
CPU time	1.25 seconds
Started	Feb 25 12:53:09 PM PST 24
Finished	Feb 25 12:53:11 PM PST 24
Peak memory	200816 kb
Host	smart-5e2d148e-c110-4e61-9a35-f520fee126f7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327975737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.327975737
Directory	/workspace/28.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3658785891
Short name	T857
Test name
Test status
Simulation time	407810085 ps
CPU time	1.57 seconds
Started	Feb 25 12:53:09 PM PST 24
Finished	Feb 25 12:53:10 PM PST 24
Peak memory	199796 kb
Host	smart-4868d341-ca89-4465-90ee-b0f7367fe85d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658785891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3658785891
Directory	/workspace/29.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2151155805
Short name	T877
Test name
Test status
Simulation time	925637018 ps
CPU time	1.91 seconds
Started	Feb 25 12:52:38 PM PST 24
Finished	Feb 25 12:52:40 PM PST 24
Peak memory	201080 kb
Host	smart-4a8edd7a-e88e-4ebf-9be4-49ed6f1e3d9f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151155805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia sing.2151155805
Directory	/workspace/3.adc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1462841012
Short name	T93
Test name
Test status
Simulation time	52320807599 ps
CPU time	119.11 seconds
Started	Feb 25 12:52:30 PM PST 24
Finished	Feb 25 12:54:30 PM PST 24
Peak memory	201256 kb
Host	smart-0ce8f068-c43e-43a1-93fd-273fe5ee6f61
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462841012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_ bash.1462841012
Directory	/workspace/3.adc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2167125725
Short name	T88
Test name
Test status
Simulation time	1405173496 ps
CPU time	1.24 seconds
Started	Feb 25 12:52:31 PM PST 24
Finished	Feb 25 12:52:32 PM PST 24
Peak memory	200888 kb
Host	smart-1721c542-00f3-47fa-9392-b7c1690d144f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167125725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r eset.2167125725
Directory	/workspace/3.adc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.57476583
Short name	T810
Test name
Test status
Simulation time	476545308 ps
CPU time	1.88 seconds
Started	Feb 25 12:52:44 PM PST 24
Finished	Feb 25 12:52:46 PM PST 24
Peak memory	200948 kb
Host	smart-75d17840-1638-4649-8fd1-f7eaecd49534
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57476583 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.57476583
Directory	/workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3340913143
Short name	T82
Test name
Test status
Simulation time	523969785 ps
CPU time	1.96 seconds
Started	Feb 25 12:52:33 PM PST 24
Finished	Feb 25 12:52:35 PM PST 24
Peak memory	200828 kb
Host	smart-7edaa72b-9b33-4f4e-83ff-cf8ea1c874be
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340913143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3340913143
Directory	/workspace/3.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3882657923
Short name	T798
Test name
Test status
Simulation time	374435209 ps
CPU time	0.83 seconds
Started	Feb 25 12:52:32 PM PST 24
Finished	Feb 25 12:52:33 PM PST 24
Peak memory	200876 kb
Host	smart-71ef19ed-7659-4c67-b2f2-9a5247664689
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882657923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3882657923
Directory	/workspace/3.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3068117733
Short name	T902
Test name
Test status
Simulation time	2337249058 ps
CPU time	6.04 seconds
Started	Feb 25 12:52:38 PM PST 24
Finished	Feb 25 12:52:44 PM PST 24
Peak memory	200944 kb
Host	smart-85025dc3-4fef-4bce-94b0-41b43c16cc58
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068117733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c trl_same_csr_outstanding.3068117733
Directory	/workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3215067149
Short name	T849
Test name
Test status
Simulation time	484578113 ps
CPU time	2.82 seconds
Started	Feb 25 12:52:33 PM PST 24
Finished	Feb 25 12:52:36 PM PST 24
Peak memory	201236 kb
Host	smart-57906512-3e4b-4bd7-8567-b20377436e8b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215067149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3215067149
Directory	/workspace/3.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1090745199
Short name	T892
Test name
Test status
Simulation time	8396401087 ps
CPU time	23.29 seconds
Started	Feb 25 12:52:30 PM PST 24
Finished	Feb 25 12:52:54 PM PST 24
Peak memory	201268 kb
Host	smart-9eb1d7df-19b6-4124-b1a0-1477004b869c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090745199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in tg_err.1090745199
Directory	/workspace/3.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2420289546
Short name	T865
Test name
Test status
Simulation time	407641154 ps
CPU time	1.6 seconds
Started	Feb 25 12:53:11 PM PST 24
Finished	Feb 25 12:53:12 PM PST 24
Peak memory	201024 kb
Host	smart-158946d1-5a2c-4a57-ac46-dd11b6966434
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420289546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2420289546
Directory	/workspace/30.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.376904122
Short name	T852
Test name
Test status
Simulation time	509029160 ps
CPU time	1.26 seconds
Started	Feb 25 12:53:11 PM PST 24
Finished	Feb 25 12:53:12 PM PST 24
Peak memory	201008 kb
Host	smart-32d4f046-d880-4c2e-a1ea-ea9e6194645d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376904122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.376904122
Directory	/workspace/31.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3465741535
Short name	T890
Test name
Test status
Simulation time	310395738 ps
CPU time	0.98 seconds
Started	Feb 25 12:53:16 PM PST 24
Finished	Feb 25 12:53:17 PM PST 24
Peak memory	200724 kb
Host	smart-e9c610e8-5d9b-4ba6-ae6d-082b9c93b08f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465741535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3465741535
Directory	/workspace/32.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3161609925
Short name	T911
Test name
Test status
Simulation time	404502822 ps
CPU time	0.96 seconds
Started	Feb 25 12:53:16 PM PST 24
Finished	Feb 25 12:53:17 PM PST 24
Peak memory	200556 kb
Host	smart-6b0df284-07b9-4757-a212-1279d7778621
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161609925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3161609925
Directory	/workspace/33.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2316085773
Short name	T816
Test name
Test status
Simulation time	345502319 ps
CPU time	1.37 seconds
Started	Feb 25 12:53:11 PM PST 24
Finished	Feb 25 12:53:12 PM PST 24
Peak memory	200848 kb
Host	smart-2a74614d-f55a-4ac0-a9ab-b6f7d8c8a02b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316085773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2316085773
Directory	/workspace/34.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1984225703
Short name	T804
Test name
Test status
Simulation time	438611748 ps
CPU time	1.15 seconds
Started	Feb 25 12:53:09 PM PST 24
Finished	Feb 25 12:53:10 PM PST 24
Peak memory	200716 kb
Host	smart-495fffcf-70ce-4aea-980a-9579133f74b4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984225703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1984225703
Directory	/workspace/35.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1424566179
Short name	T823
Test name
Test status
Simulation time	436031500 ps
CPU time	1.21 seconds
Started	Feb 25 12:53:11 PM PST 24
Finished	Feb 25 12:53:12 PM PST 24
Peak memory	200640 kb
Host	smart-18d416a0-1dca-4ea3-822a-9bb6d6903565
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424566179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1424566179
Directory	/workspace/36.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1778256758
Short name	T870
Test name
Test status
Simulation time	424900883 ps
CPU time	1.5 seconds
Started	Feb 25 12:53:08 PM PST 24
Finished	Feb 25 12:53:09 PM PST 24
Peak memory	200684 kb
Host	smart-3d2b3205-006b-49a7-b575-f1b15d181bbc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778256758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1778256758
Directory	/workspace/37.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2237001639
Short name	T797
Test name
Test status
Simulation time	391450293 ps
CPU time	1.57 seconds
Started	Feb 25 12:53:16 PM PST 24
Finished	Feb 25 12:53:18 PM PST 24
Peak memory	200696 kb
Host	smart-b5cd5adf-2297-44d4-8627-eb65bf26c7bc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237001639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2237001639
Directory	/workspace/38.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1619913811
Short name	T800
Test name
Test status
Simulation time	502681897 ps
CPU time	1.77 seconds
Started	Feb 25 12:53:16 PM PST 24
Finished	Feb 25 12:53:18 PM PST 24
Peak memory	200876 kb
Host	smart-c58d5b4c-8c1d-4365-946b-a35a9f12c701
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619913811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1619913811
Directory	/workspace/39.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1111638377
Short name	T83
Test name
Test status
Simulation time	1129608701 ps
CPU time	5.21 seconds
Started	Feb 25 12:52:47 PM PST 24
Finished	Feb 25 12:52:52 PM PST 24
Peak memory	201092 kb
Host	smart-e97d3bf2-ba25-4ed7-bb61-4c86dfee8c30
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111638377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia sing.1111638377
Directory	/workspace/4.adc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3699277906
Short name	T95
Test name
Test status
Simulation time	24990344167 ps
CPU time	12.67 seconds
Started	Feb 25 12:52:48 PM PST 24
Finished	Feb 25 12:53:01 PM PST 24
Peak memory	201232 kb
Host	smart-7751644a-7902-43b9-b118-291cdbaa3f5e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699277906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_ bash.3699277906
Directory	/workspace/4.adc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2723350875
Short name	T103
Test name
Test status
Simulation time	1313849092 ps
CPU time	1.6 seconds
Started	Feb 25 12:52:43 PM PST 24
Finished	Feb 25 12:52:45 PM PST 24
Peak memory	200888 kb
Host	smart-a0f5f42f-2728-4428-89df-0c48c3c2e7f3
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723350875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r eset.2723350875
Directory	/workspace/4.adc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1696003139
Short name	T872
Test name
Test status
Simulation time	481604095 ps
CPU time	2.08 seconds
Started	Feb 25 12:52:48 PM PST 24
Finished	Feb 25 12:52:50 PM PST 24
Peak memory	200944 kb
Host	smart-7943c281-a583-46fd-af4a-fc89c7277f71
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696003139 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1696003139
Directory	/workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3450884831
Short name	T30
Test name
Test status
Simulation time	331925217 ps
CPU time	1.53 seconds
Started	Feb 25 12:52:39 PM PST 24
Finished	Feb 25 12:52:41 PM PST 24
Peak memory	200840 kb
Host	smart-33b76aba-a876-488b-8acc-8da01ca39c12
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450884831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3450884831
Directory	/workspace/4.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.864842499
Short name	T799
Test name
Test status
Simulation time	362841875 ps
CPU time	0.72 seconds
Started	Feb 25 12:52:37 PM PST 24
Finished	Feb 25 12:52:38 PM PST 24
Peak memory	200708 kb
Host	smart-6e4cc590-a6a7-4954-a6f4-06250c7e1698
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864842499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.864842499
Directory	/workspace/4.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2321383703
Short name	T885
Test name
Test status
Simulation time	4418887057 ps
CPU time	3.47 seconds
Started	Feb 25 12:52:48 PM PST 24
Finished	Feb 25 12:52:51 PM PST 24
Peak memory	201172 kb
Host	smart-6474fa74-1095-4aec-9fe4-8dfcb1f36642
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321383703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c trl_same_csr_outstanding.2321383703
Directory	/workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2920472102
Short name	T34
Test name
Test status
Simulation time	921676666 ps
CPU time	3.31 seconds
Started	Feb 25 12:52:38 PM PST 24
Finished	Feb 25 12:52:42 PM PST 24
Peak memory	201180 kb
Host	smart-a7e1a23e-0e7e-487b-b8cd-ce39fb662905
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920472102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2920472102
Directory	/workspace/4.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3256569129
Short name	T897
Test name
Test status
Simulation time	8345489245 ps
CPU time	11.96 seconds
Started	Feb 25 12:52:48 PM PST 24
Finished	Feb 25 12:53:00 PM PST 24
Peak memory	201276 kb
Host	smart-1184feb3-6aad-4c91-ae4c-d313d5845198
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256569129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in tg_err.3256569129
Directory	/workspace/4.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3622924300
Short name	T848
Test name
Test status
Simulation time	295718957 ps
CPU time	0.99 seconds
Started	Feb 25 12:53:08 PM PST 24
Finished	Feb 25 12:53:09 PM PST 24
Peak memory	200620 kb
Host	smart-bfe94f01-3c98-43ba-b615-df1fd0e94104
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622924300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3622924300
Directory	/workspace/40.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2399570940
Short name	T803
Test name
Test status
Simulation time	371556644 ps
CPU time	0.81 seconds
Started	Feb 25 12:53:11 PM PST 24
Finished	Feb 25 12:53:12 PM PST 24
Peak memory	200796 kb
Host	smart-db45c1b4-9c28-4aea-90de-39367e87f83a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399570940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2399570940
Directory	/workspace/41.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1497025541
Short name	T904
Test name
Test status
Simulation time	487773812 ps
CPU time	0.69 seconds
Started	Feb 25 12:53:07 PM PST 24
Finished	Feb 25 12:53:08 PM PST 24
Peak memory	200680 kb
Host	smart-c2109504-79f5-4741-850d-dd075302dafb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497025541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1497025541
Directory	/workspace/42.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1282190050
Short name	T796
Test name
Test status
Simulation time	343690466 ps
CPU time	1.48 seconds
Started	Feb 25 12:53:16 PM PST 24
Finished	Feb 25 12:53:18 PM PST 24
Peak memory	200452 kb
Host	smart-4c0410a7-4466-422f-910f-45b12e919611
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282190050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1282190050
Directory	/workspace/43.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.913224890
Short name	T886
Test name
Test status
Simulation time	504703924 ps
CPU time	1.79 seconds
Started	Feb 25 12:53:09 PM PST 24
Finished	Feb 25 12:53:11 PM PST 24
Peak memory	200652 kb
Host	smart-467db6af-d691-4392-a4c7-81bf8e047d50
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913224890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.913224890
Directory	/workspace/44.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.997163159
Short name	T851
Test name
Test status
Simulation time	367503775 ps
CPU time	1.23 seconds
Started	Feb 25 12:53:13 PM PST 24
Finished	Feb 25 12:53:15 PM PST 24
Peak memory	200704 kb
Host	smart-b78673c2-7550-4ee5-a524-a3fd1d1ebf50
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997163159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.997163159
Directory	/workspace/45.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.444500529
Short name	T893
Test name
Test status
Simulation time	357947103 ps
CPU time	1.3 seconds
Started	Feb 25 12:53:13 PM PST 24
Finished	Feb 25 12:53:15 PM PST 24
Peak memory	200712 kb
Host	smart-9cc26772-dd2e-429d-9b61-2c7e04a607df
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444500529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.444500529
Directory	/workspace/46.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3156451385
Short name	T884
Test name
Test status
Simulation time	468845986 ps
CPU time	0.98 seconds
Started	Feb 25 12:53:13 PM PST 24
Finished	Feb 25 12:53:15 PM PST 24
Peak memory	200716 kb
Host	smart-7fc8eb71-f238-4164-990b-ed89c81f03aa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156451385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3156451385
Directory	/workspace/47.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1379722248
Short name	T878
Test name
Test status
Simulation time	522893765 ps
CPU time	0.94 seconds
Started	Feb 25 12:53:13 PM PST 24
Finished	Feb 25 12:53:15 PM PST 24
Peak memory	200720 kb
Host	smart-c80b4695-ddbb-4250-b18d-c4b554407a05
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379722248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1379722248
Directory	/workspace/48.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.446508852
Short name	T802
Test name
Test status
Simulation time	435349609 ps
CPU time	1.14 seconds
Started	Feb 25 12:53:23 PM PST 24
Finished	Feb 25 12:53:24 PM PST 24
Peak memory	200872 kb
Host	smart-f9f436ec-bb92-47ad-a062-6fb9dd2155f0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446508852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.446508852
Directory	/workspace/49.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1631604305
Short name	T905
Test name
Test status
Simulation time	575402466 ps
CPU time	2.29 seconds
Started	Feb 25 12:52:38 PM PST 24
Finished	Feb 25 12:52:40 PM PST 24
Peak memory	200876 kb
Host	smart-f4b1f031-4c0b-49e2-ba8c-eeb577b2547d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631604305 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1631604305
Directory	/workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4137199526
Short name	T860
Test name
Test status
Simulation time	358226480 ps
CPU time	1.5 seconds
Started	Feb 25 12:52:38 PM PST 24
Finished	Feb 25 12:52:40 PM PST 24
Peak memory	200860 kb
Host	smart-af8ffc5f-62be-49ea-956d-0fcee4047e68
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137199526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.4137199526
Directory	/workspace/5.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3340835328
Short name	T836
Test name
Test status
Simulation time	379196570 ps
CPU time	1.53 seconds
Started	Feb 25 12:52:39 PM PST 24
Finished	Feb 25 12:52:41 PM PST 24
Peak memory	200816 kb
Host	smart-69543cfa-147e-46ae-a6af-e77af61c1446
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340835328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3340835328
Directory	/workspace/5.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.620831187
Short name	T900
Test name
Test status
Simulation time	5429177151 ps
CPU time	5.09 seconds
Started	Feb 25 12:52:37 PM PST 24
Finished	Feb 25 12:52:42 PM PST 24
Peak memory	201188 kb
Host	smart-16721ffa-8104-4797-b51f-a69d429510ae
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620831187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct rl_same_csr_outstanding.620831187
Directory	/workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.243817949
Short name	T108
Test name
Test status
Simulation time	616398537 ps
CPU time	3.49 seconds
Started	Feb 25 12:52:37 PM PST 24
Finished	Feb 25 12:52:40 PM PST 24
Peak memory	209356 kb
Host	smart-62423d83-0e7a-4e3a-bfa5-f054f420b1ba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243817949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.243817949
Directory	/workspace/5.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1542063978
Short name	T888
Test name
Test status
Simulation time	511638661 ps
CPU time	1.18 seconds
Started	Feb 25 12:52:37 PM PST 24
Finished	Feb 25 12:52:38 PM PST 24
Peak memory	200944 kb
Host	smart-45b3cb3a-6aa8-434e-b1d2-dea91e6453f6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542063978 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1542063978
Directory	/workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3824676184
Short name	T89
Test name
Test status
Simulation time	507477818 ps
CPU time	0.92 seconds
Started	Feb 25 12:52:39 PM PST 24
Finished	Feb 25 12:52:40 PM PST 24
Peak memory	200788 kb
Host	smart-b42c169d-3216-42a5-887f-a87dd8b58a0a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824676184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3824676184
Directory	/workspace/6.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1142822336
Short name	T812
Test name
Test status
Simulation time	336273277 ps
CPU time	0.71 seconds
Started	Feb 25 12:52:41 PM PST 24
Finished	Feb 25 12:52:42 PM PST 24
Peak memory	200792 kb
Host	smart-14bdafcd-7933-460d-998d-0991715c85d6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142822336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1142822336
Directory	/workspace/6.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.975826377
Short name	T99
Test name
Test status
Simulation time	2241697003 ps
CPU time	1.95 seconds
Started	Feb 25 12:52:43 PM PST 24
Finished	Feb 25 12:52:46 PM PST 24
Peak memory	200944 kb
Host	smart-ef5882ee-f12c-458d-b16c-6bf119b01e53
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975826377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct rl_same_csr_outstanding.975826377
Directory	/workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.205155513
Short name	T806
Test name
Test status
Simulation time	540792169 ps
CPU time	2 seconds
Started	Feb 25 12:52:37 PM PST 24
Finished	Feb 25 12:52:39 PM PST 24
Peak memory	201116 kb
Host	smart-b663be6e-2756-47ab-8f72-5cde84ec01f1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205155513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.205155513
Directory	/workspace/6.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.804418520
Short name	T106
Test name
Test status
Simulation time	5008545197 ps
CPU time	2.2 seconds
Started	Feb 25 12:52:40 PM PST 24
Finished	Feb 25 12:52:42 PM PST 24
Peak memory	201132 kb
Host	smart-ea8e8f0d-4ee9-499f-9a34-d81099407acb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804418520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int g_err.804418520
Directory	/workspace/6.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1814038815
Short name	T811
Test name
Test status
Simulation time	594237290 ps
CPU time	2.02 seconds
Started	Feb 25 12:52:50 PM PST 24
Finished	Feb 25 12:52:52 PM PST 24
Peak memory	200944 kb
Host	smart-937d5afe-d010-4585-a606-0c3c580b22c5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814038815 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1814038815
Directory	/workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4121608718
Short name	T87
Test name
Test status
Simulation time	525948766 ps
CPU time	0.79 seconds
Started	Feb 25 12:52:48 PM PST 24
Finished	Feb 25 12:52:49 PM PST 24
Peak memory	200824 kb
Host	smart-f5993b26-3cb6-47c4-aae5-0ecc4259fd83
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121608718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.4121608718
Directory	/workspace/7.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.4004437875
Short name	T894
Test name
Test status
Simulation time	528618552 ps
CPU time	0.81 seconds
Started	Feb 25 12:52:47 PM PST 24
Finished	Feb 25 12:52:47 PM PST 24
Peak memory	200656 kb
Host	smart-7ae27729-24c2-432b-8462-9e01d7fcd491
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004437875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.4004437875
Directory	/workspace/7.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3608291675
Short name	T28
Test name
Test status
Simulation time	4453604438 ps
CPU time	11.6 seconds
Started	Feb 25 12:52:46 PM PST 24
Finished	Feb 25 12:52:58 PM PST 24
Peak memory	201212 kb
Host	smart-920d68c6-e4db-41f9-a902-be3b9126f7e6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608291675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c trl_same_csr_outstanding.3608291675
Directory	/workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.996128435
Short name	T828
Test name
Test status
Simulation time	358426119 ps
CPU time	2.28 seconds
Started	Feb 25 12:52:37 PM PST 24
Finished	Feb 25 12:52:39 PM PST 24
Peak memory	201216 kb
Host	smart-f51dae29-0ba4-468f-86be-2da4ba6dd4fc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996128435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.996128435
Directory	/workspace/7.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3452838773
Short name	T881
Test name
Test status
Simulation time	4858033247 ps
CPU time	5.1 seconds
Started	Feb 25 12:52:48 PM PST 24
Finished	Feb 25 12:52:53 PM PST 24
Peak memory	201240 kb
Host	smart-9c405794-22ea-4727-87bc-dc20903beff7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452838773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in tg_err.3452838773
Directory	/workspace/7.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1294091767
Short name	T887
Test name
Test status
Simulation time	563930671 ps
CPU time	1.61 seconds
Started	Feb 25 12:52:49 PM PST 24
Finished	Feb 25 12:52:51 PM PST 24
Peak memory	200884 kb
Host	smart-f9eb4c97-6d0a-4d21-9beb-8daffe844f8b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294091767 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1294091767
Directory	/workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1444066939
Short name	T840
Test name
Test status
Simulation time	314040315 ps
CPU time	1.27 seconds
Started	Feb 25 12:52:46 PM PST 24
Finished	Feb 25 12:52:48 PM PST 24
Peak memory	200884 kb
Host	smart-0e8cbcfa-a1b4-4cc3-9dde-47b45787072f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444066939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1444066939
Directory	/workspace/8.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.707858333
Short name	T831
Test name
Test status
Simulation time	370910051 ps
CPU time	1.07 seconds
Started	Feb 25 12:52:48 PM PST 24
Finished	Feb 25 12:52:49 PM PST 24
Peak memory	200820 kb
Host	smart-f98e266f-eeef-4390-8491-3b6d79341d2a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707858333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.707858333
Directory	/workspace/8.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3443324904
Short name	T875
Test name
Test status
Simulation time	2535862511 ps
CPU time	1.48 seconds
Started	Feb 25 12:52:47 PM PST 24
Finished	Feb 25 12:52:48 PM PST 24
Peak memory	200944 kb
Host	smart-7aad56b3-89ff-47fe-81a3-4bde80e1ad6a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443324904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c trl_same_csr_outstanding.3443324904
Directory	/workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.344335680
Short name	T826
Test name
Test status
Simulation time	509966088 ps
CPU time	2.4 seconds
Started	Feb 25 12:52:49 PM PST 24
Finished	Feb 25 12:52:51 PM PST 24
Peak memory	201208 kb
Host	smart-586f313b-0981-44d9-b541-00473aa18c99
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344335680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.344335680
Directory	/workspace/8.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3325630244
Short name	T839
Test name
Test status
Simulation time	4455246201 ps
CPU time	4.01 seconds
Started	Feb 25 12:52:48 PM PST 24
Finished	Feb 25 12:52:52 PM PST 24
Peak memory	201088 kb
Host	smart-7bb1f509-a93c-47bb-a868-27e324960a44
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325630244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in tg_err.3325630244
Directory	/workspace/8.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3677501056
Short name	T868
Test name
Test status
Simulation time	611241805 ps
CPU time	1.13 seconds
Started	Feb 25 12:52:48 PM PST 24
Finished	Feb 25 12:52:50 PM PST 24
Peak memory	200876 kb
Host	smart-5d405f63-0a7a-4cc8-89e1-07a6f36bc3bc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677501056 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3677501056
Directory	/workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.461429634
Short name	T847
Test name
Test status
Simulation time	357907122 ps
CPU time	1.54 seconds
Started	Feb 25 12:52:48 PM PST 24
Finished	Feb 25 12:52:50 PM PST 24
Peak memory	200884 kb
Host	smart-eb85297f-74fc-4606-8d9b-fa9192b1ff05
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461429634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.461429634
Directory	/workspace/9.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2547280867
Short name	T883
Test name
Test status
Simulation time	487981774 ps
CPU time	0.96 seconds
Started	Feb 25 12:52:49 PM PST 24
Finished	Feb 25 12:52:50 PM PST 24
Peak memory	200876 kb
Host	smart-792306aa-65ba-48a9-ae05-2cdeda8c71e0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547280867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2547280867
Directory	/workspace/9.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4269968059
Short name	T97
Test name
Test status
Simulation time	3879687564 ps
CPU time	4.76 seconds
Started	Feb 25 12:52:47 PM PST 24
Finished	Feb 25 12:52:51 PM PST 24
Peak memory	200996 kb
Host	smart-c56d26cb-737d-47fa-86f8-63aace427d1d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269968059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c trl_same_csr_outstanding.4269968059
Directory	/workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3889377130
Short name	T107
Test name
Test status
Simulation time	482584253 ps
CPU time	3.19 seconds
Started	Feb 25 12:52:49 PM PST 24
Finished	Feb 25 12:52:52 PM PST 24
Peak memory	201220 kb
Host	smart-d2f0526b-67e3-4b89-8572-4b760483237d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889377130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3889377130
Directory	/workspace/9.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1428813529
Short name	T856
Test name
Test status
Simulation time	8080527458 ps
CPU time	5.41 seconds
Started	Feb 25 12:52:48 PM PST 24
Finished	Feb 25 12:52:53 PM PST 24
Peak memory	201212 kb
Host	smart-0011e9c3-7996-4553-8eff-fe15ac056264
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428813529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in tg_err.1428813529
Directory	/workspace/9.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_interrupt.1154955061
Short name	T179
Test name
Test status
Simulation time	330190815966 ps
CPU time	189.33 seconds
Started	Feb 25 12:44:35 PM PST 24
Finished	Feb 25 12:47:44 PM PST 24
Peak memory	201528 kb
Host	smart-89fbc9dc-a898-4fc9-b078-e7b6030abf76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1154955061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1154955061
Directory	/workspace/0.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.654690476
Short name	T578
Test name
Test status
Simulation time	164454161634 ps
CPU time	101.17 seconds
Started	Feb 25 12:44:39 PM PST 24
Finished	Feb 25 12:46:20 PM PST 24
Peak memory	201568 kb
Host	smart-df063fe2-dbd0-415b-a53a-32046481a1e8
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=654690476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt _fixed.654690476
Directory	/workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_polled.3662836160
Short name	T461
Test name
Test status
Simulation time	329167733100 ps
CPU time	185.5 seconds
Started	Feb 25 12:44:24 PM PST 24
Finished	Feb 25 12:47:29 PM PST 24
Peak memory	201376 kb
Host	smart-45331ebd-d445-4dff-b280-09c70e3bc8a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3662836160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3662836160
Directory	/workspace/0.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2606530796
Short name	T745
Test name
Test status
Simulation time	497256682302 ps
CPU time	266.62 seconds
Started	Feb 25 12:44:30 PM PST 24
Finished	Feb 25 12:48:57 PM PST 24
Peak memory	201396 kb
Host	smart-f9d7a2a1-f21c-46df-b945-137560f78c7f
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606530796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe d.2606530796
Directory	/workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3677425959
Short name	T399
Test name
Test status
Simulation time	333427603240 ps
CPU time	200.57 seconds
Started	Feb 25 12:44:36 PM PST 24
Finished	Feb 25 12:47:57 PM PST 24
Peak memory	201480 kb
Host	smart-77a8b7ae-e90d-4a49-ab18-3142198b10fc
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677425959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. adc_ctrl_filters_wakeup_fixed.3677425959
Directory	/workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/0.adc_ctrl_lowpower_counter.2754464116
Short name	T750
Test name
Test status
Simulation time	25033590485 ps
CPU time	14.85 seconds
Started	Feb 25 12:44:35 PM PST 24
Finished	Feb 25 12:44:51 PM PST 24
Peak memory	201200 kb
Host	smart-6438f741-cbf1-4d7f-82d2-f73aaf881041
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2754464116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2754464116
Directory	/workspace/0.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/0.adc_ctrl_poweron_counter.723587002
Short name	T777
Test name
Test status
Simulation time	3878535036 ps
CPU time	5.1 seconds
Started	Feb 25 12:44:25 PM PST 24
Finished	Feb 25 12:44:30 PM PST 24
Peak memory	201268 kb
Host	smart-dbaff6f2-b037-40be-b9ba-59ac45cfbec0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=723587002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.723587002
Directory	/workspace/0.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/0.adc_ctrl_smoke.1685851297
Short name	T431
Test name
Test status
Simulation time	5999620307 ps
CPU time	15.35 seconds
Started	Feb 25 12:44:30 PM PST 24
Finished	Feb 25 12:44:46 PM PST 24
Peak memory	201228 kb
Host	smart-78bc90cb-fd37-4b2b-a53a-ae3b6999ff1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1685851297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1685851297
Directory	/workspace/0.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.adc_ctrl_stress_all.3460581049
Short name	T224
Test name
Test status
Simulation time	210160880260 ps
CPU time	222.93 seconds
Started	Feb 25 12:44:24 PM PST 24
Finished	Feb 25 12:48:07 PM PST 24
Peak memory	201480 kb
Host	smart-0c4cfc63-b7dd-4acd-8f2e-9b22ae703c56
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460581049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all. 3460581049
Directory	/workspace/0.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.adc_ctrl_alert_test.1537614284
Short name	T446
Test name
Test status
Simulation time	426550539 ps
CPU time	1.63 seconds
Started	Feb 25 12:44:41 PM PST 24
Finished	Feb 25 12:44:43 PM PST 24
Peak memory	201144 kb
Host	smart-8c6c7e48-bb9f-46b0-a004-ecd37e610841
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537614284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1537614284
Directory	/workspace/1.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.adc_ctrl_clock_gating.560321397
Short name	T310
Test name
Test status
Simulation time	318862086068 ps
CPU time	670.34 seconds
Started	Feb 25 12:44:38 PM PST 24
Finished	Feb 25 12:55:48 PM PST 24
Peak memory	201356 kb
Host	smart-ac90ae4d-59cf-4f7c-a2c4-ea47cc50f17e
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560321397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin g.560321397
Directory	/workspace/1.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_both.3673227450
Short name	T194
Test name
Test status
Simulation time	168456410440 ps
CPU time	371.88 seconds
Started	Feb 25 12:44:41 PM PST 24
Finished	Feb 25 12:50:53 PM PST 24
Peak memory	201440 kb
Host	smart-34951317-ee6c-4284-b615-3bad8d49a836
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3673227450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3673227450
Directory	/workspace/1.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2301514564
Short name	T550
Test name
Test status
Simulation time	157427596593 ps
CPU time	248.33 seconds
Started	Feb 25 12:44:35 PM PST 24
Finished	Feb 25 12:48:44 PM PST 24
Peak memory	201420 kb
Host	smart-b18d08f3-df5b-408f-88aa-d40454ca8d34
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301514564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup t_fixed.2301514564
Directory	/workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_polled.3379203810
Short name	T788
Test name
Test status
Simulation time	327219011727 ps
CPU time	419.01 seconds
Started	Feb 25 12:44:40 PM PST 24
Finished	Feb 25 12:51:39 PM PST 24
Peak memory	201580 kb
Host	smart-6eb08fd7-1bf0-4c33-8cad-61d6fb6b51f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3379203810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3379203810
Directory	/workspace/1.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3236792546
Short name	T369
Test name
Test status
Simulation time	483126551721 ps
CPU time	1011.52 seconds
Started	Feb 25 12:44:35 PM PST 24
Finished	Feb 25 01:01:27 PM PST 24
Peak memory	201484 kb
Host	smart-535ff6ad-a9e0-4079-a34a-8bbc1855eddf
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236792546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe d.3236792546
Directory	/workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_wakeup.683303678
Short name	T269
Test name
Test status
Simulation time	334900223889 ps
CPU time	764.49 seconds
Started	Feb 25 12:44:37 PM PST 24
Finished	Feb 25 12:57:22 PM PST 24
Peak memory	201428 kb
Host	smart-d54c3f71-2f07-43b1-bfc8-0cfaa1cbcf89
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683303678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w akeup.683303678
Directory	/workspace/1.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.4080028839
Short name	T529
Test name
Test status
Simulation time	492497885720 ps
CPU time	544.96 seconds
Started	Feb 25 12:44:40 PM PST 24
Finished	Feb 25 12:53:45 PM PST 24
Peak memory	201488 kb
Host	smart-eb47697d-21f1-49df-b4bb-0e17195370cc
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080028839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. adc_ctrl_filters_wakeup_fixed.4080028839
Directory	/workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/1.adc_ctrl_fsm_reset.4138488740
Short name	T418
Test name
Test status
Simulation time	72151829743 ps
CPU time	241.72 seconds
Started	Feb 25 12:44:33 PM PST 24
Finished	Feb 25 12:48:35 PM PST 24
Peak memory	201764 kb
Host	smart-6d205b48-840e-4dfd-92f3-3727ae0583f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4138488740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.4138488740
Directory	/workspace/1.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/1.adc_ctrl_lowpower_counter.2059034033
Short name	T746
Test name
Test status
Simulation time	32656516328 ps
CPU time	15.47 seconds
Started	Feb 25 12:44:41 PM PST 24
Finished	Feb 25 12:44:56 PM PST 24
Peak memory	201304 kb
Host	smart-446b3cbe-74d6-4fcb-9d2f-f7e57c7c989b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2059034033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2059034033
Directory	/workspace/1.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/1.adc_ctrl_poweron_counter.2023233659
Short name	T471
Test name
Test status
Simulation time	4880589251 ps
CPU time	11.39 seconds
Started	Feb 25 12:44:40 PM PST 24
Finished	Feb 25 12:44:52 PM PST 24
Peak memory	201300 kb
Host	smart-bc693ee9-c2f6-498c-9ffb-a6c8aa242a5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2023233659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2023233659
Directory	/workspace/1.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/1.adc_ctrl_sec_cm.2100896945
Short name	T43
Test name
Test status
Simulation time	4292321827 ps
CPU time	3.36 seconds
Started	Feb 25 12:44:33 PM PST 24
Finished	Feb 25 12:44:37 PM PST 24
Peak memory	216332 kb
Host	smart-70d8d88b-1762-4fbc-8599-40c258936d3c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100896945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2100896945
Directory	/workspace/1.adc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.adc_ctrl_smoke.113423958
Short name	T462
Test name
Test status
Simulation time	5709606428 ps
CPU time	4.9 seconds
Started	Feb 25 12:44:34 PM PST 24
Finished	Feb 25 12:44:39 PM PST 24
Peak memory	201252 kb
Host	smart-1120b2ec-8e5a-46fe-b392-9ca6a1f6b3f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113423958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.113423958
Directory	/workspace/1.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.adc_ctrl_stress_all.1924744664
Short name	T760
Test name
Test status
Simulation time	193520583673 ps
CPU time	113.73 seconds
Started	Feb 25 12:44:35 PM PST 24
Finished	Feb 25 12:46:29 PM PST 24
Peak memory	201372 kb
Host	smart-0e348059-17cf-482c-8138-d2dfb316880c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924744664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all. 1924744664
Directory	/workspace/1.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.4123434211
Short name	T357
Test name
Test status
Simulation time	591638460225 ps
CPU time	337.95 seconds
Started	Feb 25 12:44:38 PM PST 24
Finished	Feb 25 12:50:16 PM PST 24
Peak memory	210124 kb
Host	smart-7dbadb69-ceb9-452f-89e8-0e807362f36f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123434211 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.4123434211
Directory	/workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.adc_ctrl_alert_test.3472252851
Short name	T681
Test name
Test status
Simulation time	541095356 ps
CPU time	1.24 seconds
Started	Feb 25 12:45:09 PM PST 24
Finished	Feb 25 12:45:11 PM PST 24
Peak memory	201136 kb
Host	smart-7f2ad61d-183f-4312-a518-0f2e2e8bcaaf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472252851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3472252851
Directory	/workspace/10.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.825980284
Short name	T652
Test name
Test status
Simulation time	324685971280 ps
CPU time	422.19 seconds
Started	Feb 25 12:45:08 PM PST 24
Finished	Feb 25 12:52:10 PM PST 24
Peak memory	201500 kb
Host	smart-6baeafc1-00a2-4b1e-9424-fbde5f7166ec
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=825980284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup t_fixed.825980284
Directory	/workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_polled.2247903690
Short name	T355
Test name
Test status
Simulation time	493772136846 ps
CPU time	190.93 seconds
Started	Feb 25 12:45:07 PM PST 24
Finished	Feb 25 12:48:19 PM PST 24
Peak memory	201388 kb
Host	smart-98a52522-57b8-4ced-9ee3-16ec6b205cc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2247903690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2247903690
Directory	/workspace/10.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3099663234
Short name	T765
Test name
Test status
Simulation time	488859306095 ps
CPU time	228.99 seconds
Started	Feb 25 12:45:15 PM PST 24
Finished	Feb 25 12:49:04 PM PST 24
Peak memory	201464 kb
Host	smart-06b3664d-60be-4c62-9f89-89cd67a766d7
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099663234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix ed.3099663234
Directory	/workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1044662364
Short name	T625
Test name
Test status
Simulation time	164105403473 ps
CPU time	341.02 seconds
Started	Feb 25 12:45:07 PM PST 24
Finished	Feb 25 12:50:48 PM PST 24
Peak memory	201356 kb
Host	smart-26893972-4bcb-4a19-9510-66b0df45fbfb
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044662364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10 .adc_ctrl_filters_wakeup_fixed.1044662364
Directory	/workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/10.adc_ctrl_lowpower_counter.13394879
Short name	T435
Test name
Test status
Simulation time	41499093926 ps
CPU time	47.79 seconds
Started	Feb 25 12:45:07 PM PST 24
Finished	Feb 25 12:45:55 PM PST 24
Peak memory	201284 kb
Host	smart-a18786e3-bc1e-4e77-9141-9ee54a012ffe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=13394879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.13394879
Directory	/workspace/10.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/10.adc_ctrl_poweron_counter.1878222886
Short name	T379
Test name
Test status
Simulation time	4813422936 ps
CPU time	12.02 seconds
Started	Feb 25 12:45:04 PM PST 24
Finished	Feb 25 12:45:17 PM PST 24
Peak memory	201224 kb
Host	smart-0d78ccb3-627d-4257-8721-967dbf858098
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1878222886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1878222886
Directory	/workspace/10.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/10.adc_ctrl_smoke.1694568171
Short name	T613
Test name
Test status
Simulation time	5883946421 ps
CPU time	14.67 seconds
Started	Feb 25 12:44:56 PM PST 24
Finished	Feb 25 12:45:11 PM PST 24
Peak memory	201176 kb
Host	smart-4b07f07d-31f8-4c2f-ae2c-4b1eb0a209f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1694568171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1694568171
Directory	/workspace/10.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.adc_ctrl_stress_all.847006161
Short name	T248
Test name
Test status
Simulation time	376354138561 ps
CPU time	246.04 seconds
Started	Feb 25 12:45:07 PM PST 24
Finished	Feb 25 12:49:13 PM PST 24
Peak memory	201424 kb
Host	smart-6e3aa13c-e87c-4616-aac6-14d17438d281
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847006161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all. 847006161
Directory	/workspace/10.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.712499552
Short name	T352
Test name
Test status
Simulation time	49899643888 ps
CPU time	140.54 seconds
Started	Feb 25 12:45:16 PM PST 24
Finished	Feb 25 12:47:37 PM PST 24
Peak memory	210200 kb
Host	smart-c1b98397-fcc3-410f-ac2d-fa4e9db1d10f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712499552 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.712499552
Directory	/workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.adc_ctrl_alert_test.188471319
Short name	T761
Test name
Test status
Simulation time	358523554 ps
CPU time	1.47 seconds
Started	Feb 25 12:45:08 PM PST 24
Finished	Feb 25 12:45:10 PM PST 24
Peak memory	201208 kb
Host	smart-950f7741-9198-44dd-bd1d-1e7c9991b069
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188471319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.188471319
Directory	/workspace/11.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.adc_ctrl_clock_gating.1330354293
Short name	T347
Test name
Test status
Simulation time	325786892279 ps
CPU time	391.04 seconds
Started	Feb 25 12:45:07 PM PST 24
Finished	Feb 25 12:51:38 PM PST 24
Peak memory	201444 kb
Host	smart-4257c509-c97c-4617-92ce-5d8a7d0e45d7
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330354293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat ing.1330354293
Directory	/workspace/11.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_interrupt.387641504
Short name	T341
Test name
Test status
Simulation time	321146841577 ps
CPU time	746.64 seconds
Started	Feb 25 12:45:12 PM PST 24
Finished	Feb 25 12:57:39 PM PST 24
Peak memory	201548 kb
Host	smart-bbfa187a-1649-4e53-846b-1afab9ea0934
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=387641504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.387641504
Directory	/workspace/11.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.4065199358
Short name	T611
Test name
Test status
Simulation time	493148313420 ps
CPU time	1128.32 seconds
Started	Feb 25 12:45:11 PM PST 24
Finished	Feb 25 01:04:00 PM PST 24
Peak memory	201528 kb
Host	smart-65a98568-b83d-4a31-a898-01ea3d53926e
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065199358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru pt_fixed.4065199358
Directory	/workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_polled.3034001281
Short name	T135
Test name
Test status
Simulation time	328808183216 ps
CPU time	207.41 seconds
Started	Feb 25 12:45:05 PM PST 24
Finished	Feb 25 12:48:33 PM PST 24
Peak memory	201540 kb
Host	smart-68f55dea-27f3-4195-897f-96e7f0cae0e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3034001281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3034001281
Directory	/workspace/11.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3783872982
Short name	T730
Test name
Test status
Simulation time	162343307295 ps
CPU time	368.93 seconds
Started	Feb 25 12:45:05 PM PST 24
Finished	Feb 25 12:51:14 PM PST 24
Peak memory	201540 kb
Host	smart-cc1d821d-ca5c-4381-b445-724d6c825e8a
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783872982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix ed.3783872982
Directory	/workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_wakeup.1227574671
Short name	T150
Test name
Test status
Simulation time	325585779140 ps
CPU time	382.39 seconds
Started	Feb 25 12:45:08 PM PST 24
Finished	Feb 25 12:51:31 PM PST 24
Peak memory	201464 kb
Host	smart-ed9adb84-17a4-4f91-8cb8-c9c39b96c0d1
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227574671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters _wakeup.1227574671
Directory	/workspace/11.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3177178691
Short name	T683
Test name
Test status
Simulation time	168102305727 ps
CPU time	112.57 seconds
Started	Feb 25 12:45:06 PM PST 24
Finished	Feb 25 12:46:59 PM PST 24
Peak memory	201432 kb
Host	smart-015fe02c-76d8-4906-8cf7-91f0ae9050ed
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177178691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11 .adc_ctrl_filters_wakeup_fixed.3177178691
Directory	/workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/11.adc_ctrl_fsm_reset.331790040
Short name	T623
Test name
Test status
Simulation time	132628868557 ps
CPU time	465.24 seconds
Started	Feb 25 12:45:08 PM PST 24
Finished	Feb 25 12:52:53 PM PST 24
Peak memory	201820 kb
Host	smart-65332d0e-6b41-4d27-8d0a-4ed64d001b4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=331790040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.331790040
Directory	/workspace/11.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/11.adc_ctrl_lowpower_counter.1764584883
Short name	T498
Test name
Test status
Simulation time	45036791828 ps
CPU time	54.8 seconds
Started	Feb 25 12:45:11 PM PST 24
Finished	Feb 25 12:46:06 PM PST 24
Peak memory	201268 kb
Host	smart-49868822-c848-4696-9708-5b9c4d04ccde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764584883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1764584883
Directory	/workspace/11.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/11.adc_ctrl_poweron_counter.3741365068
Short name	T481
Test name
Test status
Simulation time	3853065323 ps
CPU time	5.06 seconds
Started	Feb 25 12:45:07 PM PST 24
Finished	Feb 25 12:45:12 PM PST 24
Peak memory	201228 kb
Host	smart-e313a099-6915-494f-b5c8-ae23e355e749
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3741365068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3741365068
Directory	/workspace/11.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/11.adc_ctrl_smoke.1872027735
Short name	T662
Test name
Test status
Simulation time	5895203248 ps
CPU time	13.78 seconds
Started	Feb 25 12:45:10 PM PST 24
Finished	Feb 25 12:45:24 PM PST 24
Peak memory	201208 kb
Host	smart-12b3d2e1-93b7-429e-8e0c-c57e0aa75de5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1872027735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1872027735
Directory	/workspace/11.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.adc_ctrl_stress_all.590175573
Short name	T501
Test name
Test status
Simulation time	248215436895 ps
CPU time	160.35 seconds
Started	Feb 25 12:45:07 PM PST 24
Finished	Feb 25 12:47:47 PM PST 24
Peak memory	201436 kb
Host	smart-fef5fb5f-bcd8-4054-bba6-707ab8bc41ca
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590175573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all. 590175573
Directory	/workspace/11.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.314830710
Short name	T16
Test name
Test status
Simulation time	65537104593 ps
CPU time	133.58 seconds
Started	Feb 25 12:45:07 PM PST 24
Finished	Feb 25 12:47:21 PM PST 24
Peak memory	210052 kb
Host	smart-167e48be-f1d7-4409-a870-19c7e566ebf2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314830710 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.314830710
Directory	/workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.adc_ctrl_alert_test.2866628261
Short name	T485
Test name
Test status
Simulation time	411838501 ps
CPU time	1.48 seconds
Started	Feb 25 12:45:15 PM PST 24
Finished	Feb 25 12:45:17 PM PST 24
Peak memory	201256 kb
Host	smart-3430b10b-01c0-4fd6-9ffa-3face88d45b3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866628261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2866628261
Directory	/workspace/12.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.adc_ctrl_clock_gating.646963510
Short name	T607
Test name
Test status
Simulation time	166198670636 ps
CPU time	188.43 seconds
Started	Feb 25 12:45:12 PM PST 24
Finished	Feb 25 12:48:21 PM PST 24
Peak memory	201356 kb
Host	smart-feb996da-b04f-45de-8148-5adfb52442b5
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646963510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati ng.646963510
Directory	/workspace/12.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_interrupt.3789906604
Short name	T192
Test name
Test status
Simulation time	162597674949 ps
CPU time	96.79 seconds
Started	Feb 25 12:45:08 PM PST 24
Finished	Feb 25 12:46:45 PM PST 24
Peak memory	201480 kb
Host	smart-0276c682-804d-4547-bf25-a50fad8f2b48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3789906604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3789906604
Directory	/workspace/12.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.711698704
Short name	T477
Test name
Test status
Simulation time	484510290659 ps
CPU time	1174.23 seconds
Started	Feb 25 12:45:08 PM PST 24
Finished	Feb 25 01:04:42 PM PST 24
Peak memory	201464 kb
Host	smart-8da4be85-cc99-43f1-a495-d7b14110394f
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=711698704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup t_fixed.711698704
Directory	/workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_polled.952476361
Short name	T718
Test name
Test status
Simulation time	493206452546 ps
CPU time	314.99 seconds
Started	Feb 25 12:45:10 PM PST 24
Finished	Feb 25 12:50:25 PM PST 24
Peak memory	201536 kb
Host	smart-d7a385ba-7049-4995-93ee-8d5442952f6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=952476361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.952476361
Directory	/workspace/12.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2980429437
Short name	T630
Test name
Test status
Simulation time	338907168968 ps
CPU time	352.65 seconds
Started	Feb 25 12:45:06 PM PST 24
Finished	Feb 25 12:50:58 PM PST 24
Peak memory	201564 kb
Host	smart-da06b2e2-41d0-4213-b514-eeec2a749c04
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980429437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix ed.2980429437
Directory	/workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3772486158
Short name	T651
Test name
Test status
Simulation time	325805695799 ps
CPU time	176.16 seconds
Started	Feb 25 12:45:13 PM PST 24
Finished	Feb 25 12:48:09 PM PST 24
Peak memory	201472 kb
Host	smart-60a5554a-008d-4ce2-98cc-324a3eb0ca40
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772486158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12 .adc_ctrl_filters_wakeup_fixed.3772486158
Directory	/workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/12.adc_ctrl_fsm_reset.2314602522
Short name	T782
Test name
Test status
Simulation time	100685160730 ps
CPU time	427.74 seconds
Started	Feb 25 12:45:16 PM PST 24
Finished	Feb 25 12:52:24 PM PST 24
Peak memory	201784 kb
Host	smart-05fcb115-6bb6-48a4-b538-f8f3a9ec6803
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2314602522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2314602522
Directory	/workspace/12.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/12.adc_ctrl_lowpower_counter.4209167263
Short name	T21
Test name
Test status
Simulation time	32011385993 ps
CPU time	16.94 seconds
Started	Feb 25 12:45:16 PM PST 24
Finished	Feb 25 12:45:33 PM PST 24
Peak memory	201312 kb
Host	smart-5bf5505a-7c21-4254-9ef0-a04ef6958ae3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4209167263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.4209167263
Directory	/workspace/12.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/12.adc_ctrl_poweron_counter.4220010352
Short name	T636
Test name
Test status
Simulation time	4228802156 ps
CPU time	3.16 seconds
Started	Feb 25 12:45:16 PM PST 24
Finished	Feb 25 12:45:20 PM PST 24
Peak memory	201244 kb
Host	smart-ca533a2a-d7ce-4ec9-b1c4-45cbf28ba323
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4220010352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.4220010352
Directory	/workspace/12.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/12.adc_ctrl_smoke.138503676
Short name	T455
Test name
Test status
Simulation time	5923618512 ps
CPU time	4.28 seconds
Started	Feb 25 12:45:09 PM PST 24
Finished	Feb 25 12:45:13 PM PST 24
Peak memory	201304 kb
Host	smart-928af2be-1cf8-49e6-9862-9982d6184ba6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=138503676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.138503676
Directory	/workspace/12.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3567027868
Short name	T72
Test name
Test status
Simulation time	96749290509 ps
CPU time	138.68 seconds
Started	Feb 25 12:45:13 PM PST 24
Finished	Feb 25 12:47:32 PM PST 24
Peak memory	210036 kb
Host	smart-630f6ec4-2501-4010-8fc9-be3823d19dbd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567027868 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3567027868
Directory	/workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.adc_ctrl_alert_test.3606221600
Short name	T385
Test name
Test status
Simulation time	466703034 ps
CPU time	0.91 seconds
Started	Feb 25 12:45:18 PM PST 24
Finished	Feb 25 12:45:20 PM PST 24
Peak memory	201216 kb
Host	smart-7df4fee9-5f49-46c9-80a5-455a718dec2a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606221600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3606221600
Directory	/workspace/13.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.adc_ctrl_clock_gating.4019655577
Short name	T354
Test name
Test status
Simulation time	329714945975 ps
CPU time	307.9 seconds
Started	Feb 25 12:45:12 PM PST 24
Finished	Feb 25 12:50:20 PM PST 24
Peak memory	201468 kb
Host	smart-48a589ed-029d-4abb-af94-887e342dd8f7
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019655577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat ing.4019655577
Directory	/workspace/13.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_interrupt.3709473688
Short name	T300
Test name
Test status
Simulation time	320823835900 ps
CPU time	714.8 seconds
Started	Feb 25 12:45:13 PM PST 24
Finished	Feb 25 12:57:08 PM PST 24
Peak memory	201548 kb
Host	smart-5b43285c-a837-4453-81d6-d8cd6e85b9b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3709473688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3709473688
Directory	/workspace/13.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.611825831
Short name	T657
Test name
Test status
Simulation time	492105866106 ps
CPU time	169.03 seconds
Started	Feb 25 12:45:14 PM PST 24
Finished	Feb 25 12:48:04 PM PST 24
Peak memory	201464 kb
Host	smart-a5326359-e420-4528-954f-80bb814118d0
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=611825831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup t_fixed.611825831
Directory	/workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_polled.2208671565
Short name	T340
Test name
Test status
Simulation time	167320902935 ps
CPU time	204.6 seconds
Started	Feb 25 12:45:11 PM PST 24
Finished	Feb 25 12:48:36 PM PST 24
Peak memory	201524 kb
Host	smart-98f8757a-b2ce-4821-bed7-fa4958d0eb0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2208671565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2208671565
Directory	/workspace/13.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2137384105
Short name	T65
Test name
Test status
Simulation time	327422987328 ps
CPU time	763.57 seconds
Started	Feb 25 12:45:14 PM PST 24
Finished	Feb 25 12:57:57 PM PST 24
Peak memory	201616 kb
Host	smart-cc21a8c9-4a03-4e24-ae5f-b99d6b97e4fe
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137384105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix ed.2137384105
Directory	/workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_wakeup.1960094628
Short name	T160
Test name
Test status
Simulation time	495026581588 ps
CPU time	307.58 seconds
Started	Feb 25 12:45:22 PM PST 24
Finished	Feb 25 12:50:30 PM PST 24
Peak memory	201540 kb
Host	smart-6ad85495-c3fa-4525-bd6e-dca18ccf1039
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960094628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters _wakeup.1960094628
Directory	/workspace/13.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/13.adc_ctrl_fsm_reset.4280307373
Short name	T364
Test name
Test status
Simulation time	79600091084 ps
CPU time	263.64 seconds
Started	Feb 25 12:45:15 PM PST 24
Finished	Feb 25 12:49:39 PM PST 24
Peak memory	201788 kb
Host	smart-ff6fa0fa-9d10-4216-9e17-50dfd6d95ea8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4280307373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.4280307373
Directory	/workspace/13.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/13.adc_ctrl_lowpower_counter.3243102251
Short name	T512
Test name
Test status
Simulation time	44339024784 ps
CPU time	108.95 seconds
Started	Feb 25 12:45:22 PM PST 24
Finished	Feb 25 12:47:11 PM PST 24
Peak memory	201344 kb
Host	smart-13897eb5-c709-4edc-aa80-7666e22fead3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3243102251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3243102251
Directory	/workspace/13.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/13.adc_ctrl_poweron_counter.2656510105
Short name	T439
Test name
Test status
Simulation time	2919743658 ps
CPU time	7.61 seconds
Started	Feb 25 12:45:12 PM PST 24
Finished	Feb 25 12:45:20 PM PST 24
Peak memory	201168 kb
Host	smart-67c07157-81b8-48b0-adc2-90f55dca796e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2656510105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2656510105
Directory	/workspace/13.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/13.adc_ctrl_smoke.1640040632
Short name	T424
Test name
Test status
Simulation time	5824558049 ps
CPU time	11.39 seconds
Started	Feb 25 12:45:16 PM PST 24
Finished	Feb 25 12:45:28 PM PST 24
Peak memory	201236 kb
Host	smart-c6418f13-b314-4ff6-83d1-222d714718e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1640040632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1640040632
Directory	/workspace/13.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2882475705
Short name	T321
Test name
Test status
Simulation time	107168449087 ps
CPU time	105.21 seconds
Started	Feb 25 12:45:21 PM PST 24
Finished	Feb 25 12:47:07 PM PST 24
Peak memory	210288 kb
Host	smart-9cf745f4-1a8b-44c8-a80b-f99e5a438323
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882475705 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2882475705
Directory	/workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.adc_ctrl_alert_test.1664620499
Short name	T539
Test name
Test status
Simulation time	353357768 ps
CPU time	0.81 seconds
Started	Feb 25 12:45:27 PM PST 24
Finished	Feb 25 12:45:28 PM PST 24
Peak memory	201220 kb
Host	smart-b6054a03-0ed6-40c1-ad7c-a5a7f94a1797
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664620499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1664620499
Directory	/workspace/14.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.adc_ctrl_clock_gating.3812989603
Short name	T756
Test name
Test status
Simulation time	322488236028 ps
CPU time	365.62 seconds
Started	Feb 25 12:45:22 PM PST 24
Finished	Feb 25 12:51:28 PM PST 24
Peak memory	201532 kb
Host	smart-af793cb5-9e6a-48f8-8212-831b5514769c
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812989603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat ing.3812989603
Directory	/workspace/14.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_both.3890218889
Short name	T350
Test name
Test status
Simulation time	499174775628 ps
CPU time	1120.56 seconds
Started	Feb 25 12:45:23 PM PST 24
Finished	Feb 25 01:04:03 PM PST 24
Peak memory	201524 kb
Host	smart-9dc8c5b0-a54a-41da-83a0-5d0558dd9749
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3890218889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3890218889
Directory	/workspace/14.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_interrupt.596836995
Short name	T356
Test name
Test status
Simulation time	331612479000 ps
CPU time	220.53 seconds
Started	Feb 25 12:45:17 PM PST 24
Finished	Feb 25 12:48:58 PM PST 24
Peak memory	201468 kb
Host	smart-f4ac9be2-bc3a-4811-ad38-1c123f5f2c9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=596836995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.596836995
Directory	/workspace/14.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.796784893
Short name	T702
Test name
Test status
Simulation time	497572208595 ps
CPU time	299.08 seconds
Started	Feb 25 12:45:21 PM PST 24
Finished	Feb 25 12:50:20 PM PST 24
Peak memory	201524 kb
Host	smart-5f243f42-cd94-4838-9a90-90e9675a3596
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=796784893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup t_fixed.796784893
Directory	/workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_polled.251215870
Short name	T567
Test name
Test status
Simulation time	326197188799 ps
CPU time	815.69 seconds
Started	Feb 25 12:45:17 PM PST 24
Finished	Feb 25 12:58:53 PM PST 24
Peak memory	201480 kb
Host	smart-2cddd8ec-ffc9-47f1-9331-7026d49c1279
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=251215870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.251215870
Directory	/workspace/14.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2022424398
Short name	T560
Test name
Test status
Simulation time	318273273574 ps
CPU time	181.28 seconds
Started	Feb 25 12:45:13 PM PST 24
Finished	Feb 25 12:48:15 PM PST 24
Peak memory	201484 kb
Host	smart-be0065ec-57cb-463c-a387-60e56eef37ca
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022424398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix ed.2022424398
Directory	/workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_wakeup.1337352836
Short name	T329
Test name
Test status
Simulation time	319708172367 ps
CPU time	380.5 seconds
Started	Feb 25 12:45:21 PM PST 24
Finished	Feb 25 12:51:42 PM PST 24
Peak memory	201484 kb
Host	smart-894e5474-1207-4ed0-a6c9-fc21725d5698
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337352836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters _wakeup.1337352836
Directory	/workspace/14.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.658413209
Short name	T376
Test name
Test status
Simulation time	331292236326 ps
CPU time	369.47 seconds
Started	Feb 25 12:45:23 PM PST 24
Finished	Feb 25 12:51:33 PM PST 24
Peak memory	201396 kb
Host	smart-1df5a3b5-0b96-4d9a-b787-28ae3b48173f
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658413209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. adc_ctrl_filters_wakeup_fixed.658413209
Directory	/workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/14.adc_ctrl_fsm_reset.1317115726
Short name	T561
Test name
Test status
Simulation time	124308534998 ps
CPU time	432.36 seconds
Started	Feb 25 12:45:21 PM PST 24
Finished	Feb 25 12:52:34 PM PST 24
Peak memory	201732 kb
Host	smart-ab5a990b-3e5c-4bb4-97ce-0184ea1238a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1317115726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1317115726
Directory	/workspace/14.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/14.adc_ctrl_lowpower_counter.696791736
Short name	T552
Test name
Test status
Simulation time	43635148668 ps
CPU time	18.83 seconds
Started	Feb 25 12:45:27 PM PST 24
Finished	Feb 25 12:45:46 PM PST 24
Peak memory	201288 kb
Host	smart-1eee67cc-f1fe-45ae-9353-99dea7c8126f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=696791736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.696791736
Directory	/workspace/14.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/14.adc_ctrl_poweron_counter.2079836881
Short name	T612
Test name
Test status
Simulation time	3846874512 ps
CPU time	9.63 seconds
Started	Feb 25 12:45:26 PM PST 24
Finished	Feb 25 12:45:37 PM PST 24
Peak memory	201216 kb
Host	smart-02471c64-f06f-4702-83f9-f2adece7d6a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2079836881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2079836881
Directory	/workspace/14.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/14.adc_ctrl_smoke.2696968776
Short name	T417
Test name
Test status
Simulation time	6166874448 ps
CPU time	4.42 seconds
Started	Feb 25 12:45:15 PM PST 24
Finished	Feb 25 12:45:20 PM PST 24
Peak memory	201224 kb
Host	smart-2de9ef1a-ee23-49ac-ac67-852550418be2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2696968776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2696968776
Directory	/workspace/14.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.adc_ctrl_stress_all.3427792852
Short name	T789
Test name
Test status
Simulation time	510667072492 ps
CPU time	1063.66 seconds
Started	Feb 25 12:45:22 PM PST 24
Finished	Feb 25 01:03:06 PM PST 24
Peak memory	201484 kb
Host	smart-68f50cc5-7983-4666-a850-1a7b9bc09834
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427792852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all .3427792852
Directory	/workspace/14.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1481755287
Short name	T660
Test name
Test status
Simulation time	716270196231 ps
CPU time	1060.79 seconds
Started	Feb 25 12:45:23 PM PST 24
Finished	Feb 25 01:03:04 PM PST 24
Peak memory	210112 kb
Host	smart-a912af17-77f5-4bc5-a938-8bce3cb5d42a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481755287 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1481755287
Directory	/workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.adc_ctrl_alert_test.1366422653
Short name	T422
Test name
Test status
Simulation time	494761192 ps
CPU time	1.81 seconds
Started	Feb 25 12:45:27 PM PST 24
Finished	Feb 25 12:45:29 PM PST 24
Peak memory	201236 kb
Host	smart-b1d2cfdd-153f-48a0-8fed-e85355ed2b7c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366422653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1366422653
Directory	/workspace/15.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_both.1420530244
Short name	T51
Test name
Test status
Simulation time	165393756133 ps
CPU time	90.04 seconds
Started	Feb 25 12:45:23 PM PST 24
Finished	Feb 25 12:46:53 PM PST 24
Peak memory	201560 kb
Host	smart-68ca830d-0427-4654-b1b7-5022fc2d6a86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1420530244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1420530244
Directory	/workspace/15.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_interrupt.775096745
Short name	T460
Test name
Test status
Simulation time	326721242474 ps
CPU time	402.38 seconds
Started	Feb 25 12:45:24 PM PST 24
Finished	Feb 25 12:52:06 PM PST 24
Peak memory	201416 kb
Host	smart-928b6616-1278-45f7-bd17-485d2675d924
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=775096745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.775096745
Directory	/workspace/15.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1646301100
Short name	T620
Test name
Test status
Simulation time	483271349704 ps
CPU time	471.72 seconds
Started	Feb 25 12:45:26 PM PST 24
Finished	Feb 25 12:53:19 PM PST 24
Peak memory	201460 kb
Host	smart-72fcad95-2d25-4c48-8448-8feaa361df6f
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646301100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru pt_fixed.1646301100
Directory	/workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_polled.1683221085
Short name	T590
Test name
Test status
Simulation time	163234446080 ps
CPU time	91.77 seconds
Started	Feb 25 12:45:23 PM PST 24
Finished	Feb 25 12:46:55 PM PST 24
Peak memory	201480 kb
Host	smart-1af39b12-4dfd-4946-bb7f-2ed0a8361df5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1683221085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1683221085
Directory	/workspace/15.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1705800801
Short name	T615
Test name
Test status
Simulation time	163916146841 ps
CPU time	348.01 seconds
Started	Feb 25 12:45:26 PM PST 24
Finished	Feb 25 12:51:15 PM PST 24
Peak memory	201520 kb
Host	smart-1b99eef4-e158-4a05-ae95-78b27c089cff
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705800801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix ed.1705800801
Directory	/workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_wakeup.1524632262
Short name	T273
Test name
Test status
Simulation time	167004168545 ps
CPU time	386.66 seconds
Started	Feb 25 12:45:25 PM PST 24
Finished	Feb 25 12:51:51 PM PST 24
Peak memory	201532 kb
Host	smart-3a313aa3-9d64-45aa-a7ba-c209256de9ed
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524632262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters _wakeup.1524632262
Directory	/workspace/15.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.278800625
Short name	T786
Test name
Test status
Simulation time	485462118636 ps
CPU time	114.75 seconds
Started	Feb 25 12:45:26 PM PST 24
Finished	Feb 25 12:47:22 PM PST 24
Peak memory	201428 kb
Host	smart-d3b57c87-4c02-4da6-bdda-b1ee8685301c
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278800625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. adc_ctrl_filters_wakeup_fixed.278800625
Directory	/workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/15.adc_ctrl_fsm_reset.1111381566
Short name	T67
Test name
Test status
Simulation time	80896342090 ps
CPU time	308.38 seconds
Started	Feb 25 12:45:23 PM PST 24
Finished	Feb 25 12:50:32 PM PST 24
Peak memory	201732 kb
Host	smart-80c6ef39-cb84-42b6-bda1-20aae7baee2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1111381566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1111381566
Directory	/workspace/15.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/15.adc_ctrl_lowpower_counter.1302738717
Short name	T136
Test name
Test status
Simulation time	44230875513 ps
CPU time	49.89 seconds
Started	Feb 25 12:45:24 PM PST 24
Finished	Feb 25 12:46:14 PM PST 24
Peak memory	201244 kb
Host	smart-e3abb757-6426-4ebd-90e1-77304d4efd5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1302738717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1302738717
Directory	/workspace/15.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/15.adc_ctrl_poweron_counter.3867616628
Short name	T694
Test name
Test status
Simulation time	5105341565 ps
CPU time	12.88 seconds
Started	Feb 25 12:45:27 PM PST 24
Finished	Feb 25 12:45:40 PM PST 24
Peak memory	201156 kb
Host	smart-5a1852aa-7a04-46f0-826b-a76c0fcb81a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3867616628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3867616628
Directory	/workspace/15.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/15.adc_ctrl_smoke.4182961466
Short name	T409
Test name
Test status
Simulation time	6054333631 ps
CPU time	14.07 seconds
Started	Feb 25 12:45:26 PM PST 24
Finished	Feb 25 12:45:40 PM PST 24
Peak memory	201300 kb
Host	smart-0fbb5070-f526-4884-b97b-8568ccca6e39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4182961466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.4182961466
Directory	/workspace/15.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.adc_ctrl_stress_all.656545298
Short name	T320
Test name
Test status
Simulation time	357347783427 ps
CPU time	440.6 seconds
Started	Feb 25 12:45:27 PM PST 24
Finished	Feb 25 12:52:48 PM PST 24
Peak memory	201404 kb
Host	smart-247f8421-d055-47e3-b477-edf3d8197c7f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656545298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all. 656545298
Directory	/workspace/15.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.306266846
Short name	T221
Test name
Test status
Simulation time	37519870125 ps
CPU time	105.39 seconds
Started	Feb 25 12:45:26 PM PST 24
Finished	Feb 25 12:47:11 PM PST 24
Peak memory	217976 kb
Host	smart-e81924fd-dd14-431d-b7a3-5b362be65eb6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306266846 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.306266846
Directory	/workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.adc_ctrl_alert_test.2447151519
Short name	T463
Test name
Test status
Simulation time	515616411 ps
CPU time	0.86 seconds
Started	Feb 25 12:45:31 PM PST 24
Finished	Feb 25 12:45:32 PM PST 24
Peak memory	201216 kb
Host	smart-5bf9a506-ad1d-4c4a-aa64-ff9e565f6b81
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447151519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2447151519
Directory	/workspace/16.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_both.785493793
Short name	T794
Test name
Test status
Simulation time	162781725669 ps
CPU time	359.64 seconds
Started	Feb 25 12:45:41 PM PST 24
Finished	Feb 25 12:51:40 PM PST 24
Peak memory	201640 kb
Host	smart-a50f130a-3657-48e1-afdb-22d0490682eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=785493793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.785493793
Directory	/workspace/16.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_interrupt.4143889468
Short name	T167
Test name
Test status
Simulation time	161761828807 ps
CPU time	180.74 seconds
Started	Feb 25 12:45:31 PM PST 24
Finished	Feb 25 12:48:32 PM PST 24
Peak memory	201544 kb
Host	smart-b161e2ab-3de4-4d63-9a86-5acf14f0c772
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4143889468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.4143889468
Directory	/workspace/16.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3146964048
Short name	T762
Test name
Test status
Simulation time	323523723621 ps
CPU time	170.58 seconds
Started	Feb 25 12:45:43 PM PST 24
Finished	Feb 25 12:48:34 PM PST 24
Peak memory	201468 kb
Host	smart-a0e0b933-de89-4862-9d6a-13514007ed7f
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146964048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru pt_fixed.3146964048
Directory	/workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_polled.2749280419
Short name	T239
Test name
Test status
Simulation time	493357839753 ps
CPU time	303.99 seconds
Started	Feb 25 12:45:31 PM PST 24
Finished	Feb 25 12:50:35 PM PST 24
Peak memory	201480 kb
Host	smart-36ce005e-818e-42bd-8799-c94d8e12de6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2749280419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2749280419
Directory	/workspace/16.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1881839948
Short name	T427
Test name
Test status
Simulation time	495234728096 ps
CPU time	1210.48 seconds
Started	Feb 25 12:45:28 PM PST 24
Finished	Feb 25 01:05:39 PM PST 24
Peak memory	201552 kb
Host	smart-3a27e93b-e6a5-49b0-ab39-093225309581
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881839948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix ed.1881839948
Directory	/workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_wakeup.2256811401
Short name	T326
Test name
Test status
Simulation time	172917705708 ps
CPU time	32.82 seconds
Started	Feb 25 12:45:43 PM PST 24
Finished	Feb 25 12:46:16 PM PST 24
Peak memory	201476 kb
Host	smart-8c76dd67-9e54-4b0d-a384-520dae7b2cd5
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256811401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters _wakeup.2256811401
Directory	/workspace/16.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1191245019
Short name	T543
Test name
Test status
Simulation time	164037811953 ps
CPU time	102.63 seconds
Started	Feb 25 12:45:30 PM PST 24
Finished	Feb 25 12:47:13 PM PST 24
Peak memory	201472 kb
Host	smart-22e873fc-18ad-4ca4-a41b-913ac8abe3a2
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191245019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16 .adc_ctrl_filters_wakeup_fixed.1191245019
Directory	/workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/16.adc_ctrl_fsm_reset.4217543462
Short name	T628
Test name
Test status
Simulation time	91197089939 ps
CPU time	333.29 seconds
Started	Feb 25 12:45:29 PM PST 24
Finished	Feb 25 12:51:02 PM PST 24
Peak memory	201832 kb
Host	smart-662b29a4-677a-40e3-afab-952d2159cea5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4217543462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.4217543462
Directory	/workspace/16.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/16.adc_ctrl_lowpower_counter.3120560765
Short name	T401
Test name
Test status
Simulation time	34588309120 ps
CPU time	76.93 seconds
Started	Feb 25 12:45:28 PM PST 24
Finished	Feb 25 12:46:45 PM PST 24
Peak memory	201272 kb
Host	smart-bcbd45ec-88fc-41b5-91c2-36bde1ea6438
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3120560765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.3120560765
Directory	/workspace/16.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/16.adc_ctrl_poweron_counter.3705084402
Short name	T66
Test name
Test status
Simulation time	3660943416 ps
CPU time	5.19 seconds
Started	Feb 25 12:45:29 PM PST 24
Finished	Feb 25 12:45:34 PM PST 24
Peak memory	201216 kb
Host	smart-b9d88f4d-c089-4996-a82c-bf60673b3e98
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3705084402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3705084402
Directory	/workspace/16.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/16.adc_ctrl_smoke.725732200
Short name	T380
Test name
Test status
Simulation time	6053837952 ps
CPU time	1.82 seconds
Started	Feb 25 12:45:43 PM PST 24
Finished	Feb 25 12:45:45 PM PST 24
Peak memory	201280 kb
Host	smart-eae705e0-685e-4440-bdf4-7b553aab9037
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=725732200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.725732200
Directory	/workspace/16.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.adc_ctrl_stress_all.1417143926
Short name	T155
Test name
Test status
Simulation time	172114600104 ps
CPU time	133.2 seconds
Started	Feb 25 12:45:29 PM PST 24
Finished	Feb 25 12:47:43 PM PST 24
Peak memory	201400 kb
Host	smart-587760bf-57c3-4250-8666-b2709899a482
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417143926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all .1417143926
Directory	/workspace/16.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1992557103
Short name	T189
Test name
Test status
Simulation time	89017485664 ps
CPU time	77.95 seconds
Started	Feb 25 12:45:27 PM PST 24
Finished	Feb 25 12:46:45 PM PST 24
Peak memory	209800 kb
Host	smart-657eb177-eac9-4f91-8efe-0ddd3ba093f6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992557103 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1992557103
Directory	/workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.adc_ctrl_alert_test.2536688142
Short name	T451
Test name
Test status
Simulation time	486015517 ps
CPU time	0.9 seconds
Started	Feb 25 12:45:33 PM PST 24
Finished	Feb 25 12:45:34 PM PST 24
Peak memory	201216 kb
Host	smart-c7b443d2-3bb0-46c3-99d8-16e36a07c362
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536688142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2536688142
Directory	/workspace/17.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.adc_ctrl_clock_gating.4230794554
Short name	T296
Test name
Test status
Simulation time	493099783113 ps
CPU time	1055.63 seconds
Started	Feb 25 12:45:43 PM PST 24
Finished	Feb 25 01:03:20 PM PST 24
Peak memory	201492 kb
Host	smart-04e432f6-65d1-4c57-a724-897ad94d7b07
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230794554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat ing.4230794554
Directory	/workspace/17.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_interrupt.671967550
Short name	T278
Test name
Test status
Simulation time	494813917108 ps
CPU time	319.52 seconds
Started	Feb 25 12:45:29 PM PST 24
Finished	Feb 25 12:50:49 PM PST 24
Peak memory	201396 kb
Host	smart-0415b503-5bbd-4d7a-84ee-2d6e27424d11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=671967550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.671967550
Directory	/workspace/17.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.4215954204
Short name	T488
Test name
Test status
Simulation time	340603659313 ps
CPU time	726.82 seconds
Started	Feb 25 12:45:43 PM PST 24
Finished	Feb 25 12:57:50 PM PST 24
Peak memory	201468 kb
Host	smart-934dd09c-2741-46dc-8f7b-3c27209262a6
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215954204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru pt_fixed.4215954204
Directory	/workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_polled.1304110213
Short name	T687
Test name
Test status
Simulation time	320270381399 ps
CPU time	99.22 seconds
Started	Feb 25 12:45:28 PM PST 24
Finished	Feb 25 12:47:08 PM PST 24
Peak memory	201424 kb
Host	smart-d8693126-5b0a-4ca5-a720-b0e360d25283
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1304110213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1304110213
Directory	/workspace/17.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1001195537
Short name	T655
Test name
Test status
Simulation time	484434115862 ps
CPU time	1029.43 seconds
Started	Feb 25 12:45:32 PM PST 24
Finished	Feb 25 01:02:42 PM PST 24
Peak memory	201512 kb
Host	smart-82b4bc3e-3f6a-409f-b231-683da4c93b10
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001195537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix ed.1001195537
Directory	/workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_wakeup.2934017775
Short name	T62
Test name
Test status
Simulation time	171299986938 ps
CPU time	91.43 seconds
Started	Feb 25 12:45:42 PM PST 24
Finished	Feb 25 12:47:14 PM PST 24
Peak memory	201536 kb
Host	smart-f81c1bf1-b4b5-4f90-9476-d8c0034f3d0b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934017775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters _wakeup.2934017775
Directory	/workspace/17.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.441328976
Short name	T676
Test name
Test status
Simulation time	336402194318 ps
CPU time	120.45 seconds
Started	Feb 25 12:45:31 PM PST 24
Finished	Feb 25 12:47:31 PM PST 24
Peak memory	201464 kb
Host	smart-e31687c9-bf1e-47ca-be17-30226fc739c4
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441328976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. adc_ctrl_filters_wakeup_fixed.441328976
Directory	/workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/17.adc_ctrl_fsm_reset.3610423777
Short name	T697
Test name
Test status
Simulation time	90426648219 ps
CPU time	392.27 seconds
Started	Feb 25 12:45:41 PM PST 24
Finished	Feb 25 12:52:13 PM PST 24
Peak memory	201880 kb
Host	smart-23f8c4b9-1132-4eee-add1-46ec7f186f81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3610423777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3610423777
Directory	/workspace/17.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/17.adc_ctrl_lowpower_counter.3391028167
Short name	T535
Test name
Test status
Simulation time	30652739311 ps
CPU time	18.05 seconds
Started	Feb 25 12:45:42 PM PST 24
Finished	Feb 25 12:46:01 PM PST 24
Peak memory	201268 kb
Host	smart-ff9447cd-977c-4722-986d-662b17309047
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3391028167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3391028167
Directory	/workspace/17.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/17.adc_ctrl_poweron_counter.1090748877
Short name	T549
Test name
Test status
Simulation time	3432193409 ps
CPU time	7.88 seconds
Started	Feb 25 12:45:29 PM PST 24
Finished	Feb 25 12:45:37 PM PST 24
Peak memory	201212 kb
Host	smart-23d23387-b719-4b29-9d7d-1a4258adc7bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1090748877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1090748877
Directory	/workspace/17.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/17.adc_ctrl_smoke.3711673133
Short name	T577
Test name
Test status
Simulation time	5764598376 ps
CPU time	14.08 seconds
Started	Feb 25 12:45:28 PM PST 24
Finished	Feb 25 12:45:42 PM PST 24
Peak memory	201220 kb
Host	smart-a7d62a09-570b-4540-9bc3-a394e480974a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3711673133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3711673133
Directory	/workspace/17.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.adc_ctrl_stress_all.46929431
Short name	T619
Test name
Test status
Simulation time	269516047946 ps
CPU time	461.45 seconds
Started	Feb 25 12:45:43 PM PST 24
Finished	Feb 25 12:53:24 PM PST 24
Peak memory	201784 kb
Host	smart-f0250b6d-ff68-4796-a001-dd255546d5ff
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46929431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.46929431
Directory	/workspace/17.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.107663483
Short name	T213
Test name
Test status
Simulation time	70211090681 ps
CPU time	170.16 seconds
Started	Feb 25 12:45:28 PM PST 24
Finished	Feb 25 12:48:19 PM PST 24
Peak memory	210104 kb
Host	smart-3bb53e5d-1c62-491a-8513-818d9c7eb94d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107663483 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.107663483
Directory	/workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.adc_ctrl_alert_test.2932260076
Short name	T466
Test name
Test status
Simulation time	467737536 ps
CPU time	1.61 seconds
Started	Feb 25 12:45:38 PM PST 24
Finished	Feb 25 12:45:40 PM PST 24
Peak memory	201160 kb
Host	smart-ed8279bf-0573-4e49-904e-b61053174a03
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932260076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2932260076
Directory	/workspace/18.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.adc_ctrl_clock_gating.3982888353
Short name	T726
Test name
Test status
Simulation time	488956068195 ps
CPU time	229.8 seconds
Started	Feb 25 12:45:39 PM PST 24
Finished	Feb 25 12:49:30 PM PST 24
Peak memory	201460 kb
Host	smart-ecf566f3-68b0-4e64-95a9-fee7fe01218c
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982888353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat ing.3982888353
Directory	/workspace/18.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_both.823103399
Short name	T271
Test name
Test status
Simulation time	165625569442 ps
CPU time	199.26 seconds
Started	Feb 25 12:45:43 PM PST 24
Finished	Feb 25 12:49:03 PM PST 24
Peak memory	201568 kb
Host	smart-f5994491-01a3-4160-8760-fcd9f07bb22a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=823103399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.823103399
Directory	/workspace/18.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_interrupt.234754742
Short name	T199
Test name
Test status
Simulation time	499431130306 ps
CPU time	1055.03 seconds
Started	Feb 25 12:45:38 PM PST 24
Finished	Feb 25 01:03:13 PM PST 24
Peak memory	201480 kb
Host	smart-d469b26d-073c-49df-9f04-25a34bf92960
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=234754742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.234754742
Directory	/workspace/18.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.695922636
Short name	T497
Test name
Test status
Simulation time	336336950677 ps
CPU time	206.6 seconds
Started	Feb 25 12:45:39 PM PST 24
Finished	Feb 25 12:49:06 PM PST 24
Peak memory	201464 kb
Host	smart-eb539542-75bf-4ca9-9f63-862d3d9c56c5
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=695922636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup t_fixed.695922636
Directory	/workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_polled.976082188
Short name	T769
Test name
Test status
Simulation time	172468441329 ps
CPU time	188.32 seconds
Started	Feb 25 12:45:39 PM PST 24
Finished	Feb 25 12:48:47 PM PST 24
Peak memory	201496 kb
Host	smart-e42c891c-2eca-49b0-8307-6a1697532716
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=976082188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.976082188
Directory	/workspace/18.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3788871302
Short name	T768
Test name
Test status
Simulation time	327559735049 ps
CPU time	178.81 seconds
Started	Feb 25 12:45:40 PM PST 24
Finished	Feb 25 12:48:39 PM PST 24
Peak memory	201388 kb
Host	smart-58b76d9c-49ca-40e3-af84-004e85199cdc
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788871302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix ed.3788871302
Directory	/workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_wakeup.2962776289
Short name	T126
Test name
Test status
Simulation time	331469154563 ps
CPU time	211.61 seconds
Started	Feb 25 12:45:39 PM PST 24
Finished	Feb 25 12:49:11 PM PST 24
Peak memory	201408 kb
Host	smart-636a5998-8eb0-4d18-97f2-04bea8c5ee48
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962776289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters _wakeup.2962776289
Directory	/workspace/18.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.50090358
Short name	T724
Test name
Test status
Simulation time	494710337303 ps
CPU time	1115.97 seconds
Started	Feb 25 12:45:39 PM PST 24
Finished	Feb 25 01:04:16 PM PST 24
Peak memory	201464 kb
Host	smart-48187318-79e6-4f78-9e4a-ee4c523a40d3
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50090358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ= adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.a dc_ctrl_filters_wakeup_fixed.50090358
Directory	/workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/18.adc_ctrl_fsm_reset.2257197689
Short name	T673
Test name
Test status
Simulation time	119093420611 ps
CPU time	509.25 seconds
Started	Feb 25 12:45:42 PM PST 24
Finished	Feb 25 12:54:11 PM PST 24
Peak memory	201784 kb
Host	smart-57013359-3363-44c5-95d3-a71d3e94819f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257197689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2257197689
Directory	/workspace/18.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/18.adc_ctrl_lowpower_counter.3672412488
Short name	T419
Test name
Test status
Simulation time	48178196163 ps
CPU time	53.22 seconds
Started	Feb 25 12:45:40 PM PST 24
Finished	Feb 25 12:46:33 PM PST 24
Peak memory	201248 kb
Host	smart-eabe9e39-51fc-4902-af28-258f290ac26d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3672412488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3672412488
Directory	/workspace/18.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/18.adc_ctrl_poweron_counter.960855612
Short name	T644
Test name
Test status
Simulation time	5335691515 ps
CPU time	12.18 seconds
Started	Feb 25 12:45:39 PM PST 24
Finished	Feb 25 12:45:51 PM PST 24
Peak memory	201220 kb
Host	smart-8628b7bf-ed14-42eb-9fc4-b5e8c51cdd9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=960855612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.960855612
Directory	/workspace/18.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/18.adc_ctrl_smoke.3287729365
Short name	T719
Test name
Test status
Simulation time	5818892012 ps
CPU time	4.64 seconds
Started	Feb 25 12:45:41 PM PST 24
Finished	Feb 25 12:45:45 PM PST 24
Peak memory	201348 kb
Host	smart-aeb0300c-cba1-43d5-9230-fbcbca14f387
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3287729365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3287729365
Directory	/workspace/18.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.adc_ctrl_stress_all.1082550173
Short name	T703
Test name
Test status
Simulation time	378983495060 ps
CPU time	895.91 seconds
Started	Feb 25 12:45:43 PM PST 24
Finished	Feb 25 01:00:39 PM PST 24
Peak memory	201552 kb
Host	smart-9190bbed-815d-48b2-bad1-d906a9f3f9cb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082550173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all .1082550173
Directory	/workspace/18.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1800519419
Short name	T60
Test name
Test status
Simulation time	23088787110 ps
CPU time	55.15 seconds
Started	Feb 25 12:45:40 PM PST 24
Finished	Feb 25 12:46:35 PM PST 24
Peak memory	209700 kb
Host	smart-ec2ebc81-d5f8-4aaa-8b83-7abf78b1a6b1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800519419 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1800519419
Directory	/workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.adc_ctrl_alert_test.1538094707
Short name	T38
Test name
Test status
Simulation time	505852369 ps
CPU time	1.14 seconds
Started	Feb 25 12:45:42 PM PST 24
Finished	Feb 25 12:45:43 PM PST 24
Peak memory	201292 kb
Host	smart-d59e5780-3dd3-4fb0-8649-9c30eeba1fa7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538094707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1538094707
Directory	/workspace/19.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.adc_ctrl_clock_gating.1639871654
Short name	T641
Test name
Test status
Simulation time	161326147719 ps
CPU time	356.77 seconds
Started	Feb 25 12:45:41 PM PST 24
Finished	Feb 25 12:51:38 PM PST 24
Peak memory	201480 kb
Host	smart-6eb4343b-dcab-408b-94ec-9acb235b34cb
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639871654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat ing.1639871654
Directory	/workspace/19.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_both.2100716830
Short name	T759
Test name
Test status
Simulation time	160532975867 ps
CPU time	94.4 seconds
Started	Feb 25 12:45:43 PM PST 24
Finished	Feb 25 12:47:17 PM PST 24
Peak memory	201532 kb
Host	smart-047c26b5-0da0-4997-aa9f-07b94ccd381e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2100716830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2100716830
Directory	/workspace/19.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_interrupt.1279870703
Short name	T318
Test name
Test status
Simulation time	163225489503 ps
CPU time	360.63 seconds
Started	Feb 25 12:45:39 PM PST 24
Finished	Feb 25 12:51:40 PM PST 24
Peak memory	201584 kb
Host	smart-1ae543ea-bbd0-4cf7-963e-a2df14f8f58c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1279870703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1279870703
Directory	/workspace/19.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2081374622
Short name	T437
Test name
Test status
Simulation time	162008716879 ps
CPU time	27.3 seconds
Started	Feb 25 12:45:39 PM PST 24
Finished	Feb 25 12:46:06 PM PST 24
Peak memory	201456 kb
Host	smart-a46705f6-4978-49f7-9f6b-d2239142f85e
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081374622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru pt_fixed.2081374622
Directory	/workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_polled.443374924
Short name	T633
Test name
Test status
Simulation time	494170248306 ps
CPU time	1155.15 seconds
Started	Feb 25 12:45:40 PM PST 24
Finished	Feb 25 01:04:55 PM PST 24
Peak memory	201392 kb
Host	smart-5f98e0cc-8ad7-41ae-b021-5ac720e4b14f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=443374924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.443374924
Directory	/workspace/19.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3552900573
Short name	T205
Test name
Test status
Simulation time	324091298582 ps
CPU time	706.03 seconds
Started	Feb 25 12:45:44 PM PST 24
Finished	Feb 25 12:57:30 PM PST 24
Peak memory	201468 kb
Host	smart-d38c92e2-b0a0-4a74-88d8-bc3991e2f6e0
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552900573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix ed.3552900573
Directory	/workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_wakeup.1605637510
Short name	T154
Test name
Test status
Simulation time	167636919081 ps
CPU time	98.79 seconds
Started	Feb 25 12:45:38 PM PST 24
Finished	Feb 25 12:47:17 PM PST 24
Peak memory	201480 kb
Host	smart-22734d9e-e0ad-4395-9976-0c67a246c6a9
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605637510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters _wakeup.1605637510
Directory	/workspace/19.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1617885985
Short name	T426
Test name
Test status
Simulation time	495123895084 ps
CPU time	457.4 seconds
Started	Feb 25 12:45:38 PM PST 24
Finished	Feb 25 12:53:15 PM PST 24
Peak memory	201344 kb
Host	smart-57aa99c0-905d-46f6-ba91-2287c69d1202
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617885985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19 .adc_ctrl_filters_wakeup_fixed.1617885985
Directory	/workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/19.adc_ctrl_fsm_reset.392154615
Short name	T234
Test name
Test status
Simulation time	113608904564 ps
CPU time	371.06 seconds
Started	Feb 25 12:45:41 PM PST 24
Finished	Feb 25 12:51:52 PM PST 24
Peak memory	201808 kb
Host	smart-a878615e-a183-4186-aeff-08995c443c32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=392154615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.392154615
Directory	/workspace/19.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/19.adc_ctrl_lowpower_counter.176825047
Short name	T749
Test name
Test status
Simulation time	24323368308 ps
CPU time	4.4 seconds
Started	Feb 25 12:45:39 PM PST 24
Finished	Feb 25 12:45:43 PM PST 24
Peak memory	201176 kb
Host	smart-9a5452a2-d080-4fe2-83c3-a6c28a4b1c46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=176825047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.176825047
Directory	/workspace/19.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/19.adc_ctrl_poweron_counter.4040253059
Short name	T773
Test name
Test status
Simulation time	4350058256 ps
CPU time	3.53 seconds
Started	Feb 25 12:45:40 PM PST 24
Finished	Feb 25 12:45:44 PM PST 24
Peak memory	201304 kb
Host	smart-ff2efc4d-1204-4550-ab47-32a8a283ee89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4040253059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.4040253059
Directory	/workspace/19.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/19.adc_ctrl_smoke.3849786876
Short name	T110
Test name
Test status
Simulation time	5684564025 ps
CPU time	13.05 seconds
Started	Feb 25 12:45:37 PM PST 24
Finished	Feb 25 12:45:50 PM PST 24
Peak memory	201236 kb
Host	smart-4cc6030f-0133-4c8e-909e-576ffe392bdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3849786876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3849786876
Directory	/workspace/19.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.adc_ctrl_stress_all.4181885069
Short name	T324
Test name
Test status
Simulation time	364165269495 ps
CPU time	892.56 seconds
Started	Feb 25 12:45:40 PM PST 24
Finished	Feb 25 01:00:32 PM PST 24
Peak memory	201412 kb
Host	smart-d5049b66-9a96-4c59-89b5-3ca3ad3469ba
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181885069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all .4181885069
Directory	/workspace/19.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3795199448
Short name	T648
Test name
Test status
Simulation time	24937147345 ps
CPU time	54.15 seconds
Started	Feb 25 12:45:37 PM PST 24
Finished	Feb 25 12:46:32 PM PST 24
Peak memory	201660 kb
Host	smart-591ea083-55af-4a8d-9a23-e82d8e79a488
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795199448 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3795199448
Directory	/workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.adc_ctrl_alert_test.2714468984
Short name	T392
Test name
Test status
Simulation time	448771588 ps
CPU time	1.12 seconds
Started	Feb 25 12:44:38 PM PST 24
Finished	Feb 25 12:44:40 PM PST 24
Peak memory	201140 kb
Host	smart-5e2d7e4d-44e4-46cc-8c57-33fc2bb8e601
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714468984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2714468984
Directory	/workspace/2.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.adc_ctrl_clock_gating.3941605369
Short name	T659
Test name
Test status
Simulation time	331021842504 ps
CPU time	169.1 seconds
Started	Feb 25 12:44:38 PM PST 24
Finished	Feb 25 12:47:28 PM PST 24
Peak memory	201464 kb
Host	smart-1b1d8133-d6e3-4b7f-bd2a-2c3656adad20
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941605369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati ng.3941605369
Directory	/workspace/2.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_both.1157874059
Short name	T264
Test name
Test status
Simulation time	501056862885 ps
CPU time	1112.05 seconds
Started	Feb 25 12:44:38 PM PST 24
Finished	Feb 25 01:03:10 PM PST 24
Peak memory	201584 kb
Host	smart-ea45385f-e970-4118-9bb7-1e3542674eca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1157874059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1157874059
Directory	/workspace/2.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_interrupt.701878700
Short name	T313
Test name
Test status
Simulation time	163381732653 ps
CPU time	379.76 seconds
Started	Feb 25 12:44:41 PM PST 24
Finished	Feb 25 12:51:01 PM PST 24
Peak memory	201672 kb
Host	smart-9f431e41-1bcb-40c6-9c8c-613cd18dc989
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=701878700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.701878700
Directory	/workspace/2.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3748750838
Short name	T384
Test name
Test status
Simulation time	167211161644 ps
CPU time	312.55 seconds
Started	Feb 25 12:44:45 PM PST 24
Finished	Feb 25 12:49:58 PM PST 24
Peak memory	201480 kb
Host	smart-7ea73ca3-9bde-4dac-8349-a2f44b0c8f00
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748750838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup t_fixed.3748750838
Directory	/workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_polled.2575512067
Short name	T530
Test name
Test status
Simulation time	163399916531 ps
CPU time	27.7 seconds
Started	Feb 25 12:44:40 PM PST 24
Finished	Feb 25 12:45:08 PM PST 24
Peak memory	201548 kb
Host	smart-7535295c-32e3-413f-a306-8ef738117c27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2575512067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2575512067
Directory	/workspace/2.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3632028499
Short name	T665
Test name
Test status
Simulation time	320765520569 ps
CPU time	303.26 seconds
Started	Feb 25 12:44:40 PM PST 24
Finished	Feb 25 12:49:43 PM PST 24
Peak memory	201476 kb
Host	smart-3998a0c5-0bce-401b-9923-6d27fee63865
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632028499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe d.3632028499
Directory	/workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_wakeup.3625227677
Short name	T238
Test name
Test status
Simulation time	163273092242 ps
CPU time	80.17 seconds
Started	Feb 25 12:44:38 PM PST 24
Finished	Feb 25 12:45:58 PM PST 24
Peak memory	201476 kb
Host	smart-f37a6f86-264e-44a9-9b6f-b8dad8c0c491
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625227677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_ wakeup.3625227677
Directory	/workspace/2.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.344626618
Short name	T378
Test name
Test status
Simulation time	488365528345 ps
CPU time	358.32 seconds
Started	Feb 25 12:44:49 PM PST 24
Finished	Feb 25 12:50:47 PM PST 24
Peak memory	201592 kb
Host	smart-b6e838e8-d0dd-4e01-a948-87c172ab1464
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344626618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a dc_ctrl_filters_wakeup_fixed.344626618
Directory	/workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/2.adc_ctrl_fsm_reset.119152669
Short name	T23
Test name
Test status
Simulation time	137653777344 ps
CPU time	471.68 seconds
Started	Feb 25 12:44:40 PM PST 24
Finished	Feb 25 12:52:32 PM PST 24
Peak memory	201656 kb
Host	smart-c95c311e-fdd3-4e80-8231-5ffa646b5c9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=119152669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.119152669
Directory	/workspace/2.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/2.adc_ctrl_lowpower_counter.1112748484
Short name	T520
Test name
Test status
Simulation time	44549073632 ps
CPU time	12.43 seconds
Started	Feb 25 12:44:48 PM PST 24
Finished	Feb 25 12:45:00 PM PST 24
Peak memory	201284 kb
Host	smart-03f3200b-1aa2-4260-8107-b1f705d5d9bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112748484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1112748484
Directory	/workspace/2.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/2.adc_ctrl_poweron_counter.1215932
Short name	T608
Test name
Test status
Simulation time	5315375397 ps
CPU time	13.52 seconds
Started	Feb 25 12:44:53 PM PST 24
Finished	Feb 25 12:45:06 PM PST 24
Peak memory	201156 kb
Host	smart-156ef610-f398-4e0c-bad4-7da4c765b72e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1215932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1215932
Directory	/workspace/2.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/2.adc_ctrl_sec_cm.2531217124
Short name	T44
Test name
Test status
Simulation time	8325738354 ps
CPU time	4.21 seconds
Started	Feb 25 12:44:47 PM PST 24
Finished	Feb 25 12:44:51 PM PST 24
Peak memory	217540 kb
Host	smart-b6991f11-a9fb-481e-b8b1-b10d5b2aeedd
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531217124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2531217124
Directory	/workspace/2.adc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.adc_ctrl_smoke.489918605
Short name	T70
Test name
Test status
Simulation time	6153276186 ps
CPU time	7.61 seconds
Started	Feb 25 12:44:44 PM PST 24
Finished	Feb 25 12:44:52 PM PST 24
Peak memory	201264 kb
Host	smart-1a760c43-df00-4043-8a26-18d1816a8f12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=489918605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.489918605
Directory	/workspace/2.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.adc_ctrl_stress_all.1964561022
Short name	T285
Test name
Test status
Simulation time	329798543411 ps
CPU time	807.05 seconds
Started	Feb 25 12:44:38 PM PST 24
Finished	Feb 25 12:58:05 PM PST 24
Peak memory	201540 kb
Host	smart-b687a571-04e3-4eb0-b953-df22ae499282
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964561022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all. 1964561022
Directory	/workspace/2.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1765908819
Short name	T661
Test name
Test status
Simulation time	58107486875 ps
CPU time	65.23 seconds
Started	Feb 25 12:44:39 PM PST 24
Finished	Feb 25 12:45:44 PM PST 24
Peak memory	201576 kb
Host	smart-2c32849f-9d80-4a8b-81d0-d794b4266583
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765908819 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1765908819
Directory	/workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.adc_ctrl_alert_test.916095141
Short name	T537
Test name
Test status
Simulation time	435440777 ps
CPU time	1.65 seconds
Started	Feb 25 12:45:52 PM PST 24
Finished	Feb 25 12:45:54 PM PST 24
Peak memory	201140 kb
Host	smart-8af4a84b-2b0f-47db-b9f3-112f80c4eab9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916095141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.916095141
Directory	/workspace/20.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_interrupt.4184623696
Short name	T201
Test name
Test status
Simulation time	482381580549 ps
CPU time	157.1 seconds
Started	Feb 25 12:45:41 PM PST 24
Finished	Feb 25 12:48:18 PM PST 24
Peak memory	201504 kb
Host	smart-80b87aab-f901-4dd5-b357-77a84041eb51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4184623696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.4184623696
Directory	/workspace/20.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2713728970
Short name	T735
Test name
Test status
Simulation time	325919164487 ps
CPU time	396.43 seconds
Started	Feb 25 12:45:40 PM PST 24
Finished	Feb 25 12:52:16 PM PST 24
Peak memory	201408 kb
Host	smart-5bf7bba3-d807-4915-aa1e-e97d679ed922
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713728970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru pt_fixed.2713728970
Directory	/workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_polled.1401737281
Short name	T162
Test name
Test status
Simulation time	331569483661 ps
CPU time	198.91 seconds
Started	Feb 25 12:45:37 PM PST 24
Finished	Feb 25 12:48:57 PM PST 24
Peak memory	201540 kb
Host	smart-8c119ee8-7792-4fb0-9f13-4e094a014cf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1401737281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1401737281
Directory	/workspace/20.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3454766783
Short name	T185
Test name
Test status
Simulation time	330310019816 ps
CPU time	338.89 seconds
Started	Feb 25 12:45:42 PM PST 24
Finished	Feb 25 12:51:22 PM PST 24
Peak memory	201432 kb
Host	smart-e1c8356f-626a-4407-b700-b973689f62d5
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454766783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix ed.3454766783
Directory	/workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_wakeup.3259869811
Short name	T181
Test name
Test status
Simulation time	517712481406 ps
CPU time	257.81 seconds
Started	Feb 25 12:45:39 PM PST 24
Finished	Feb 25 12:49:57 PM PST 24
Peak memory	201536 kb
Host	smart-5da68a1e-44f4-44e4-9e83-d328c4e0af4b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259869811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters _wakeup.3259869811
Directory	/workspace/20.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3689800285
Short name	T713
Test name
Test status
Simulation time	492832889821 ps
CPU time	1153.59 seconds
Started	Feb 25 12:45:37 PM PST 24
Finished	Feb 25 01:04:51 PM PST 24
Peak memory	201512 kb
Host	smart-8652b2fc-cc73-4216-8507-de7d3a1255e4
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689800285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20 .adc_ctrl_filters_wakeup_fixed.3689800285
Directory	/workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/20.adc_ctrl_fsm_reset.520525881
Short name	T533
Test name
Test status
Simulation time	98432707028 ps
CPU time	482.81 seconds
Started	Feb 25 12:45:51 PM PST 24
Finished	Feb 25 12:53:55 PM PST 24
Peak memory	201732 kb
Host	smart-571480f6-61d1-40c7-9caf-406c64722654
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=520525881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.520525881
Directory	/workspace/20.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/20.adc_ctrl_lowpower_counter.2834530367
Short name	T367
Test name
Test status
Simulation time	23098238925 ps
CPU time	51.84 seconds
Started	Feb 25 12:45:49 PM PST 24
Finished	Feb 25 12:46:41 PM PST 24
Peak memory	201272 kb
Host	smart-01818d85-7e8c-4981-bf64-3ccb294de07e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2834530367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2834530367
Directory	/workspace/20.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/20.adc_ctrl_poweron_counter.3493527864
Short name	T721
Test name
Test status
Simulation time	3633279185 ps
CPU time	2.73 seconds
Started	Feb 25 12:45:39 PM PST 24
Finished	Feb 25 12:45:43 PM PST 24
Peak memory	201288 kb
Host	smart-b22386e6-d64e-42e1-9878-0401611165e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493527864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3493527864
Directory	/workspace/20.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/20.adc_ctrl_smoke.2667481192
Short name	T133
Test name
Test status
Simulation time	5949996031 ps
CPU time	3.96 seconds
Started	Feb 25 12:45:40 PM PST 24
Finished	Feb 25 12:45:44 PM PST 24
Peak memory	201212 kb
Host	smart-64380b22-1844-4fb9-8bce-f191fbdabb09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2667481192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2667481192
Directory	/workspace/20.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/20.adc_ctrl_stress_all.2843481644
Short name	T629
Test name
Test status
Simulation time	6699924589 ps
CPU time	8.18 seconds
Started	Feb 25 12:45:50 PM PST 24
Finished	Feb 25 12:45:59 PM PST 24
Peak memory	201296 kb
Host	smart-3020da1c-0bc4-45b4-8fe1-6746aa7f4567
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843481644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all .2843481644
Directory	/workspace/20.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2280531661
Short name	T780
Test name
Test status
Simulation time	123321624474 ps
CPU time	52.14 seconds
Started	Feb 25 12:45:51 PM PST 24
Finished	Feb 25 12:46:43 PM PST 24
Peak memory	209788 kb
Host	smart-a8031ef9-a027-4b5c-8aeb-dd787f3e1fde
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280531661 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2280531661
Directory	/workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.adc_ctrl_alert_test.1793448201
Short name	T689
Test name
Test status
Simulation time	471954244 ps
CPU time	0.89 seconds
Started	Feb 25 12:45:47 PM PST 24
Finished	Feb 25 12:45:48 PM PST 24
Peak memory	201160 kb
Host	smart-9be76b9b-cb8d-4e04-b39f-b8ae2439836f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793448201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1793448201
Directory	/workspace/21.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.adc_ctrl_clock_gating.579715550
Short name	T291
Test name
Test status
Simulation time	329262422669 ps
CPU time	172.01 seconds
Started	Feb 25 12:45:48 PM PST 24
Finished	Feb 25 12:48:40 PM PST 24
Peak memory	201400 kb
Host	smart-0ef2d664-4d67-4884-9f6f-23e0fbf6b1ec
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579715550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gati ng.579715550
Directory	/workspace/21.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_both.2627234573
Short name	T15
Test name
Test status
Simulation time	319089950685 ps
CPU time	778.84 seconds
Started	Feb 25 12:45:51 PM PST 24
Finished	Feb 25 12:58:50 PM PST 24
Peak memory	201500 kb
Host	smart-bac0d493-7638-42bb-b41d-366f8b155d34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2627234573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2627234573
Directory	/workspace/21.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_interrupt.2139976957
Short name	T311
Test name
Test status
Simulation time	165802665330 ps
CPU time	382.17 seconds
Started	Feb 25 12:45:50 PM PST 24
Finished	Feb 25 12:52:12 PM PST 24
Peak memory	201608 kb
Host	smart-a43b5324-25f3-4312-8372-04531dbf80b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2139976957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2139976957
Directory	/workspace/21.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2786502817
Short name	T682
Test name
Test status
Simulation time	170364963018 ps
CPU time	382.04 seconds
Started	Feb 25 12:45:49 PM PST 24
Finished	Feb 25 12:52:12 PM PST 24
Peak memory	201532 kb
Host	smart-5535c17c-d6cb-4c81-9bef-29f0afc76c15
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786502817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru pt_fixed.2786502817
Directory	/workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_polled.4254456264
Short name	T309
Test name
Test status
Simulation time	318573980265 ps
CPU time	692.33 seconds
Started	Feb 25 12:45:50 PM PST 24
Finished	Feb 25 12:57:22 PM PST 24
Peak memory	201500 kb
Host	smart-825ba3f6-cd54-4c72-a3cb-f1b849e9df6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4254456264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.4254456264
Directory	/workspace/21.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.299135691
Short name	T604
Test name
Test status
Simulation time	335753932434 ps
CPU time	696.84 seconds
Started	Feb 25 12:45:47 PM PST 24
Finished	Feb 25 12:57:24 PM PST 24
Peak memory	201540 kb
Host	smart-eb2e92e2-8471-43a9-84ff-e761e0f123f9
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=299135691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixe d.299135691
Directory	/workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_wakeup.4005962592
Short name	T731
Test name
Test status
Simulation time	491730715700 ps
CPU time	1009.53 seconds
Started	Feb 25 12:45:50 PM PST 24
Finished	Feb 25 01:02:40 PM PST 24
Peak memory	201468 kb
Host	smart-b2690fd2-9cbd-473b-9b63-5f53fad7e9c1
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005962592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters _wakeup.4005962592
Directory	/workspace/21.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1403564233
Short name	T17
Test name
Test status
Simulation time	165760705040 ps
CPU time	333.02 seconds
Started	Feb 25 12:45:48 PM PST 24
Finished	Feb 25 12:51:21 PM PST 24
Peak memory	201408 kb
Host	smart-c6dbaf92-742d-4efa-84c7-1bdc20f85e40
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403564233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21 .adc_ctrl_filters_wakeup_fixed.1403564233
Directory	/workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/21.adc_ctrl_fsm_reset.1240207453
Short name	T227
Test name
Test status
Simulation time	61506081826 ps
CPU time	228.69 seconds
Started	Feb 25 12:45:47 PM PST 24
Finished	Feb 25 12:49:36 PM PST 24
Peak memory	201812 kb
Host	smart-6da556d1-2ad1-4979-bf20-1cccd7a10a07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1240207453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1240207453
Directory	/workspace/21.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/21.adc_ctrl_lowpower_counter.1740839074
Short name	T634
Test name
Test status
Simulation time	26533838022 ps
CPU time	20.83 seconds
Started	Feb 25 12:45:49 PM PST 24
Finished	Feb 25 12:46:10 PM PST 24
Peak memory	201212 kb
Host	smart-11aa4705-3f5d-4bf9-a138-1dda1fe13166
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1740839074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1740839074
Directory	/workspace/21.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/21.adc_ctrl_poweron_counter.4080664895
Short name	T686
Test name
Test status
Simulation time	5132904214 ps
CPU time	3.74 seconds
Started	Feb 25 12:45:50 PM PST 24
Finished	Feb 25 12:45:54 PM PST 24
Peak memory	201288 kb
Host	smart-e80dd9c9-5d64-4e2a-ac3e-2bf8441967dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4080664895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.4080664895
Directory	/workspace/21.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/21.adc_ctrl_smoke.3730996503
Short name	T509
Test name
Test status
Simulation time	5749839683 ps
CPU time	1.61 seconds
Started	Feb 25 12:45:47 PM PST 24
Finished	Feb 25 12:45:49 PM PST 24
Peak memory	201196 kb
Host	smart-6b8d195c-e774-4c1e-99c6-825da9c71dab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730996503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3730996503
Directory	/workspace/21.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.adc_ctrl_stress_all.199399365
Short name	T247
Test name
Test status
Simulation time	507119563585 ps
CPU time	267.41 seconds
Started	Feb 25 12:45:51 PM PST 24
Finished	Feb 25 12:50:18 PM PST 24
Peak memory	201556 kb
Host	smart-6a8de134-ad7b-4462-b65e-ed347586dadf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199399365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all. 199399365
Directory	/workspace/21.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3477294185
Short name	T597
Test name
Test status
Simulation time	248322764934 ps
CPU time	180.82 seconds
Started	Feb 25 12:45:47 PM PST 24
Finished	Feb 25 12:48:48 PM PST 24
Peak memory	210112 kb
Host	smart-62e77839-e96c-43a5-8370-bc81ba9a0947
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477294185 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3477294185
Directory	/workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.adc_ctrl_alert_test.3806223281
Short name	T787
Test name
Test status
Simulation time	457260835 ps
CPU time	1.67 seconds
Started	Feb 25 12:45:56 PM PST 24
Finished	Feb 25 12:45:58 PM PST 24
Peak memory	201140 kb
Host	smart-f37b423c-e2f3-478f-a00c-95b5bc74c25c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806223281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3806223281
Directory	/workspace/22.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.adc_ctrl_clock_gating.1719799561
Short name	T262
Test name
Test status
Simulation time	326129649892 ps
CPU time	388.94 seconds
Started	Feb 25 12:45:49 PM PST 24
Finished	Feb 25 12:52:18 PM PST 24
Peak memory	201396 kb
Host	smart-bfa5703d-df44-4f12-84c4-8494b87787c9
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719799561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat ing.1719799561
Directory	/workspace/22.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_both.3311086926
Short name	T245
Test name
Test status
Simulation time	167532113891 ps
CPU time	57.9 seconds
Started	Feb 25 12:45:54 PM PST 24
Finished	Feb 25 12:46:52 PM PST 24
Peak memory	201524 kb
Host	smart-ad1b9d91-05b9-46f6-9396-e1e834bb83a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3311086926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3311086926
Directory	/workspace/22.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_interrupt.2634777856
Short name	T180
Test name
Test status
Simulation time	489334667778 ps
CPU time	272.64 seconds
Started	Feb 25 12:45:49 PM PST 24
Finished	Feb 25 12:50:21 PM PST 24
Peak memory	201480 kb
Host	smart-a6ee30d3-5633-441c-a1fe-cd067fe28aee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2634777856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2634777856
Directory	/workspace/22.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2103562389
Short name	T507
Test name
Test status
Simulation time	166973158041 ps
CPU time	191.89 seconds
Started	Feb 25 12:45:49 PM PST 24
Finished	Feb 25 12:49:01 PM PST 24
Peak memory	201464 kb
Host	smart-d27a5dd7-ef4d-4859-834c-c33989630676
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103562389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru pt_fixed.2103562389
Directory	/workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_polled.1034692972
Short name	T169
Test name
Test status
Simulation time	168763045771 ps
CPU time	101.89 seconds
Started	Feb 25 12:45:47 PM PST 24
Finished	Feb 25 12:47:29 PM PST 24
Peak memory	201612 kb
Host	smart-38e4d23c-c180-4324-bde6-c08414e10a1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1034692972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1034692972
Directory	/workspace/22.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2236207382
Short name	T443
Test name
Test status
Simulation time	158499124424 ps
CPU time	87.71 seconds
Started	Feb 25 12:45:48 PM PST 24
Finished	Feb 25 12:47:16 PM PST 24
Peak memory	201496 kb
Host	smart-4db999f2-72c8-4397-a550-a4792128c96d
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236207382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix ed.2236207382
Directory	/workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_wakeup.326245733
Short name	T459
Test name
Test status
Simulation time	170935641373 ps
CPU time	410.84 seconds
Started	Feb 25 12:45:52 PM PST 24
Finished	Feb 25 12:52:44 PM PST 24
Peak memory	201472 kb
Host	smart-bfdc009f-6c34-4ac5-8f11-c45b9519b6df
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326245733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_ wakeup.326245733
Directory	/workspace/22.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2220802610
Short name	T669
Test name
Test status
Simulation time	167284324795 ps
CPU time	100.39 seconds
Started	Feb 25 12:45:50 PM PST 24
Finished	Feb 25 12:47:31 PM PST 24
Peak memory	201468 kb
Host	smart-4f7aa380-dd95-4877-bfaa-ae96e47724ae
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220802610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22 .adc_ctrl_filters_wakeup_fixed.2220802610
Directory	/workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/22.adc_ctrl_fsm_reset.1991113624
Short name	T206
Test name
Test status
Simulation time	97207807335 ps
CPU time	386.55 seconds
Started	Feb 25 12:45:55 PM PST 24
Finished	Feb 25 12:52:22 PM PST 24
Peak memory	201916 kb
Host	smart-3282b665-f2ac-4022-8edb-169928359c27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1991113624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1991113624
Directory	/workspace/22.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/22.adc_ctrl_lowpower_counter.1829546918
Short name	T531
Test name
Test status
Simulation time	45241834120 ps
CPU time	19.56 seconds
Started	Feb 25 12:45:53 PM PST 24
Finished	Feb 25 12:46:14 PM PST 24
Peak memory	201204 kb
Host	smart-cd383ce8-6449-4c36-aa3f-1917224d7143
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1829546918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1829546918
Directory	/workspace/22.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/22.adc_ctrl_poweron_counter.2589568672
Short name	T646
Test name
Test status
Simulation time	3645192363 ps
CPU time	8.32 seconds
Started	Feb 25 12:45:51 PM PST 24
Finished	Feb 25 12:46:00 PM PST 24
Peak memory	201284 kb
Host	smart-7c7913d6-544c-4629-a05f-32f236bd3857
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2589568672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2589568672
Directory	/workspace/22.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/22.adc_ctrl_smoke.1272865141
Short name	T514
Test name
Test status
Simulation time	5784670315 ps
CPU time	3.97 seconds
Started	Feb 25 12:45:52 PM PST 24
Finished	Feb 25 12:45:57 PM PST 24
Peak memory	201272 kb
Host	smart-8e13a2e6-29e3-45bc-94ef-6e75b038b478
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1272865141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1272865141
Directory	/workspace/22.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2747755523
Short name	T219
Test name
Test status
Simulation time	272904904125 ps
CPU time	133.21 seconds
Started	Feb 25 12:45:50 PM PST 24
Finished	Feb 25 12:48:04 PM PST 24
Peak memory	210108 kb
Host	smart-bc246b13-c2d1-461a-be9b-d3e0e9c1f813
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747755523 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2747755523
Directory	/workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.adc_ctrl_alert_test.2651814121
Short name	T425
Test name
Test status
Simulation time	480451162 ps
CPU time	1.24 seconds
Started	Feb 25 12:46:07 PM PST 24
Finished	Feb 25 12:46:08 PM PST 24
Peak memory	201360 kb
Host	smart-ebbcc14c-ebf0-403b-b6ee-a59f753cd86e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651814121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2651814121
Directory	/workspace/23.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.adc_ctrl_clock_gating.4154149598
Short name	T290
Test name
Test status
Simulation time	330137993405 ps
CPU time	191.2 seconds
Started	Feb 25 12:46:03 PM PST 24
Finished	Feb 25 12:49:15 PM PST 24
Peak memory	201492 kb
Host	smart-15edf9e5-79ab-422b-aa6b-7b450656f56c
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154149598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat ing.4154149598
Directory	/workspace/23.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_both.354078430
Short name	T345
Test name
Test status
Simulation time	334231223375 ps
CPU time	64.05 seconds
Started	Feb 25 12:46:05 PM PST 24
Finished	Feb 25 12:47:09 PM PST 24
Peak memory	201480 kb
Host	smart-b01ffd14-3363-4250-8f72-b4795d8c10a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=354078430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.354078430
Directory	/workspace/23.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_interrupt.2893748592
Short name	T322
Test name
Test status
Simulation time	157316036828 ps
CPU time	189.06 seconds
Started	Feb 25 12:45:53 PM PST 24
Finished	Feb 25 12:49:02 PM PST 24
Peak memory	201544 kb
Host	smart-ade24dbb-becf-4848-9c29-fb674fceeb82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2893748592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2893748592
Directory	/workspace/23.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.973220076
Short name	T390
Test name
Test status
Simulation time	159928165461 ps
CPU time	366.38 seconds
Started	Feb 25 12:45:52 PM PST 24
Finished	Feb 25 12:51:58 PM PST 24
Peak memory	201432 kb
Host	smart-2091014e-fcb3-44fa-a001-d44a77445f8b
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=973220076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup t_fixed.973220076
Directory	/workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_polled.1785423103
Short name	T624
Test name
Test status
Simulation time	485081078814 ps
CPU time	1147.91 seconds
Started	Feb 25 12:45:55 PM PST 24
Finished	Feb 25 01:05:04 PM PST 24
Peak memory	201484 kb
Host	smart-68315912-8621-404f-b794-3e3ceb16d89a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1785423103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1785423103
Directory	/workspace/23.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.26614660
Short name	T711
Test name
Test status
Simulation time	500347144922 ps
CPU time	98.52 seconds
Started	Feb 25 12:45:57 PM PST 24
Finished	Feb 25 12:47:36 PM PST 24
Peak memory	201372 kb
Host	smart-3aa6d90f-8bb0-4420-a86f-161bfb47307d
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=26614660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixed .26614660
Directory	/workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_wakeup.4160368326
Short name	T146
Test name
Test status
Simulation time	499919587694 ps
CPU time	305.16 seconds
Started	Feb 25 12:45:51 PM PST 24
Finished	Feb 25 12:50:57 PM PST 24
Peak memory	201484 kb
Host	smart-c7d796a6-3d89-41a7-bb83-7152e5ec8dc4
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160368326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters _wakeup.4160368326
Directory	/workspace/23.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1765746753
Short name	T739
Test name
Test status
Simulation time	488212307291 ps
CPU time	1071.82 seconds
Started	Feb 25 12:45:54 PM PST 24
Finished	Feb 25 01:03:46 PM PST 24
Peak memory	201456 kb
Host	smart-52a16243-c3fa-4a77-a843-fc9f01d18f2f
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765746753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23 .adc_ctrl_filters_wakeup_fixed.1765746753
Directory	/workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/23.adc_ctrl_fsm_reset.1452842477
Short name	T231
Test name
Test status
Simulation time	95149289893 ps
CPU time	472.86 seconds
Started	Feb 25 12:46:04 PM PST 24
Finished	Feb 25 12:53:57 PM PST 24
Peak memory	201784 kb
Host	smart-bf58a456-8fcb-4ad9-9953-0613e8805136
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452842477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1452842477
Directory	/workspace/23.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/23.adc_ctrl_lowpower_counter.2703786974
Short name	T744
Test name
Test status
Simulation time	31091612090 ps
CPU time	67.53 seconds
Started	Feb 25 12:46:02 PM PST 24
Finished	Feb 25 12:47:10 PM PST 24
Peak memory	201204 kb
Host	smart-f23c1e72-80d7-4eaf-8030-f3cf36920bd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2703786974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2703786974
Directory	/workspace/23.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/23.adc_ctrl_poweron_counter.1513713975
Short name	T536
Test name
Test status
Simulation time	4901015212 ps
CPU time	1.76 seconds
Started	Feb 25 12:46:03 PM PST 24
Finished	Feb 25 12:46:05 PM PST 24
Peak memory	201284 kb
Host	smart-2f666591-4912-4154-91c8-117517aa4944
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1513713975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1513713975
Directory	/workspace/23.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/23.adc_ctrl_smoke.1470938116
Short name	T776
Test name
Test status
Simulation time	6097034561 ps
CPU time	15.66 seconds
Started	Feb 25 12:45:48 PM PST 24
Finished	Feb 25 12:46:04 PM PST 24
Peak memory	201292 kb
Host	smart-0714bdd9-3a7f-4048-b9ed-5760855afb74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1470938116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1470938116
Directory	/workspace/23.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.adc_ctrl_stress_all.2983768628
Short name	T383
Test name
Test status
Simulation time	5063495723 ps
CPU time	4.09 seconds
Started	Feb 25 12:46:02 PM PST 24
Finished	Feb 25 12:46:07 PM PST 24
Peak memory	201248 kb
Host	smart-946d2697-b001-4b52-9f24-d752df4f2b5f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983768628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all .2983768628
Directory	/workspace/23.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.adc_ctrl_alert_test.1500120760
Short name	T414
Test name
Test status
Simulation time	407534817 ps
CPU time	0.68 seconds
Started	Feb 25 12:45:59 PM PST 24
Finished	Feb 25 12:46:00 PM PST 24
Peak memory	201204 kb
Host	smart-604b67f7-c5a0-45d0-a7e2-00ae1453c9d3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500120760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1500120760
Directory	/workspace/24.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.adc_ctrl_clock_gating.4100583754
Short name	T161
Test name
Test status
Simulation time	334354977791 ps
CPU time	48.97 seconds
Started	Feb 25 12:46:04 PM PST 24
Finished	Feb 25 12:46:53 PM PST 24
Peak memory	201520 kb
Host	smart-c0a7cdbb-f697-4aec-8d62-ea44e825d61e
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100583754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat ing.4100583754
Directory	/workspace/24.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_interrupt.875396644
Short name	T240
Test name
Test status
Simulation time	497556304234 ps
CPU time	1145.34 seconds
Started	Feb 25 12:46:06 PM PST 24
Finished	Feb 25 01:05:12 PM PST 24
Peak memory	201472 kb
Host	smart-4ed5e900-5455-47da-b86c-9e85f8e40a69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=875396644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.875396644
Directory	/workspace/24.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2179532944
Short name	T61
Test name
Test status
Simulation time	165722754028 ps
CPU time	358.71 seconds
Started	Feb 25 12:46:04 PM PST 24
Finished	Feb 25 12:52:03 PM PST 24
Peak memory	201492 kb
Host	smart-ddbc0343-68c4-47e0-91bd-1ec6121f5d49
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179532944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru pt_fixed.2179532944
Directory	/workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_polled.999039979
Short name	T241
Test name
Test status
Simulation time	161700275426 ps
CPU time	366.62 seconds
Started	Feb 25 12:45:56 PM PST 24
Finished	Feb 25 12:52:03 PM PST 24
Peak memory	201400 kb
Host	smart-0a087a5e-56dc-4a3e-8798-2bf5188ceb39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=999039979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.999039979
Directory	/workspace/24.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.4082502664
Short name	T685
Test name
Test status
Simulation time	166975297432 ps
CPU time	371.53 seconds
Started	Feb 25 12:46:04 PM PST 24
Finished	Feb 25 12:52:16 PM PST 24
Peak memory	201524 kb
Host	smart-06eb616f-c537-406c-b126-02be106cd55b
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082502664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix ed.4082502664
Directory	/workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_wakeup.848296502
Short name	T125
Test name
Test status
Simulation time	167843379162 ps
CPU time	190.14 seconds
Started	Feb 25 12:46:04 PM PST 24
Finished	Feb 25 12:49:14 PM PST 24
Peak memory	201552 kb
Host	smart-3c145936-30cb-438e-bff0-1c9793b23a57
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848296502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_ wakeup.848296502
Directory	/workspace/24.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2162999366
Short name	T152
Test name
Test status
Simulation time	483681157516 ps
CPU time	235.45 seconds
Started	Feb 25 12:46:11 PM PST 24
Finished	Feb 25 12:50:08 PM PST 24
Peak memory	201368 kb
Host	smart-b2d21b1f-b82a-494b-ac26-e16f6398fbaf
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162999366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24 .adc_ctrl_filters_wakeup_fixed.2162999366
Directory	/workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/24.adc_ctrl_fsm_reset.1510164943
Short name	T640
Test name
Test status
Simulation time	107627439030 ps
CPU time	417.72 seconds
Started	Feb 25 12:46:00 PM PST 24
Finished	Feb 25 12:52:58 PM PST 24
Peak memory	201736 kb
Host	smart-70ca54b7-b5d2-45a1-9dc3-7a1355d00457
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1510164943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1510164943
Directory	/workspace/24.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/24.adc_ctrl_lowpower_counter.1529270548
Short name	T393
Test name
Test status
Simulation time	35542427517 ps
CPU time	43.21 seconds
Started	Feb 25 12:46:02 PM PST 24
Finished	Feb 25 12:46:45 PM PST 24
Peak memory	201200 kb
Host	smart-31c7c4bc-ddb1-4454-a986-7c032a4d9ab2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1529270548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1529270548
Directory	/workspace/24.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/24.adc_ctrl_poweron_counter.2961125573
Short name	T758
Test name
Test status
Simulation time	4576039514 ps
CPU time	2.19 seconds
Started	Feb 25 12:46:06 PM PST 24
Finished	Feb 25 12:46:09 PM PST 24
Peak memory	201288 kb
Host	smart-3beb0d42-dba5-4db2-bafc-0e5d64edf047
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961125573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2961125573
Directory	/workspace/24.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/24.adc_ctrl_smoke.3493325123
Short name	T436
Test name
Test status
Simulation time	5712931920 ps
CPU time	13.81 seconds
Started	Feb 25 12:45:56 PM PST 24
Finished	Feb 25 12:46:10 PM PST 24
Peak memory	201296 kb
Host	smart-794511d7-325f-4cf9-9bf6-86498fd9f1c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493325123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3493325123
Directory	/workspace/24.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.adc_ctrl_stress_all.1822972550
Short name	T338
Test name
Test status
Simulation time	339817681452 ps
CPU time	199.88 seconds
Started	Feb 25 12:45:57 PM PST 24
Finished	Feb 25 12:49:17 PM PST 24
Peak memory	201476 kb
Host	smart-134da84b-b483-4137-8aff-1af745694933
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822972550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all .1822972550
Directory	/workspace/24.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.adc_ctrl_alert_test.2510284263
Short name	T526
Test name
Test status
Simulation time	412558784 ps
CPU time	1.07 seconds
Started	Feb 25 12:46:11 PM PST 24
Finished	Feb 25 12:46:13 PM PST 24
Peak memory	201224 kb
Host	smart-3df52742-905a-4d77-b16b-c51f9c64821a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510284263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2510284263
Directory	/workspace/25.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.adc_ctrl_clock_gating.2787510507
Short name	T337
Test name
Test status
Simulation time	495898177270 ps
CPU time	118.66 seconds
Started	Feb 25 12:46:04 PM PST 24
Finished	Feb 25 12:48:03 PM PST 24
Peak memory	201552 kb
Host	smart-eb0bcc59-2572-45f9-a90f-c7db40b866f6
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787510507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat ing.2787510507
Directory	/workspace/25.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_both.3966378906
Short name	T130
Test name
Test status
Simulation time	331179335293 ps
CPU time	767.78 seconds
Started	Feb 25 12:45:59 PM PST 24
Finished	Feb 25 12:58:48 PM PST 24
Peak memory	201484 kb
Host	smart-f4824fde-fece-4fef-a6af-8157b5394734
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3966378906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3966378906
Directory	/workspace/25.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_interrupt.2813219877
Short name	T253
Test name
Test status
Simulation time	485755755210 ps
CPU time	1163.32 seconds
Started	Feb 25 12:45:56 PM PST 24
Finished	Feb 25 01:05:19 PM PST 24
Peak memory	201540 kb
Host	smart-1c79e3e1-3ef0-48cc-bfe1-307a15631394
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2813219877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2813219877
Directory	/workspace/25.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.4066839271
Short name	T570
Test name
Test status
Simulation time	165656773456 ps
CPU time	379.41 seconds
Started	Feb 25 12:46:06 PM PST 24
Finished	Feb 25 12:52:26 PM PST 24
Peak memory	201468 kb
Host	smart-ddc328d1-6856-44ea-94ac-d8e494967b0e
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066839271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru pt_fixed.4066839271
Directory	/workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_polled.539945599
Short name	T302
Test name
Test status
Simulation time	499335289874 ps
CPU time	1139.97 seconds
Started	Feb 25 12:46:06 PM PST 24
Finished	Feb 25 01:05:06 PM PST 24
Peak memory	201448 kb
Host	smart-1f4913ec-9f9f-44ac-888c-a4b43a9a02c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=539945599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.539945599
Directory	/workspace/25.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3527220859
Short name	T729
Test name
Test status
Simulation time	488673028350 ps
CPU time	290.85 seconds
Started	Feb 25 12:45:56 PM PST 24
Finished	Feb 25 12:50:47 PM PST 24
Peak memory	201564 kb
Host	smart-9bdc24a8-3d8c-44f5-81fd-a1861a948aca
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527220859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix ed.3527220859
Directory	/workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_wakeup.2276842125
Short name	T242
Test name
Test status
Simulation time	332449264447 ps
CPU time	194.56 seconds
Started	Feb 25 12:46:04 PM PST 24
Finished	Feb 25 12:49:19 PM PST 24
Peak memory	201476 kb
Host	smart-2b6cd90a-8118-4dea-9bc0-c609b37e3145
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276842125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters _wakeup.2276842125
Directory	/workspace/25.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2209888082
Short name	T525
Test name
Test status
Simulation time	488841130390 ps
CPU time	286.81 seconds
Started	Feb 25 12:46:04 PM PST 24
Finished	Feb 25 12:50:51 PM PST 24
Peak memory	201400 kb
Host	smart-502cac2b-cf8b-4112-92ec-b5cc7fa7fe9f
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209888082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25 .adc_ctrl_filters_wakeup_fixed.2209888082
Directory	/workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/25.adc_ctrl_fsm_reset.1964151983
Short name	T654
Test name
Test status
Simulation time	121251869818 ps
CPU time	351.04 seconds
Started	Feb 25 12:46:06 PM PST 24
Finished	Feb 25 12:51:57 PM PST 24
Peak memory	201788 kb
Host	smart-dcc84709-b40b-45d2-8c46-6ce38a5a6460
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1964151983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1964151983
Directory	/workspace/25.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/25.adc_ctrl_lowpower_counter.70514183
Short name	T548
Test name
Test status
Simulation time	27241020696 ps
CPU time	63.24 seconds
Started	Feb 25 12:46:02 PM PST 24
Finished	Feb 25 12:47:06 PM PST 24
Peak memory	201288 kb
Host	smart-76d955f4-8d8c-41c3-bcf8-dbcdf0df9b3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=70514183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.70514183
Directory	/workspace/25.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/25.adc_ctrl_poweron_counter.1405447608
Short name	T480
Test name
Test status
Simulation time	3477567905 ps
CPU time	2.72 seconds
Started	Feb 25 12:46:04 PM PST 24
Finished	Feb 25 12:46:07 PM PST 24
Peak memory	201216 kb
Host	smart-a6f2c398-6f55-4d17-bfbe-0e85f0fa1e57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1405447608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1405447608
Directory	/workspace/25.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/25.adc_ctrl_smoke.3600743838
Short name	T732
Test name
Test status
Simulation time	5721803539 ps
CPU time	13.42 seconds
Started	Feb 25 12:46:04 PM PST 24
Finished	Feb 25 12:46:17 PM PST 24
Peak memory	201224 kb
Host	smart-e059cd9f-fb37-48e8-b3ce-db4ee927deee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3600743838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3600743838
Directory	/workspace/25.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.adc_ctrl_stress_all.2432695868
Short name	T10
Test name
Test status
Simulation time	196849949190 ps
CPU time	85.52 seconds
Started	Feb 25 12:46:08 PM PST 24
Finished	Feb 25 12:47:34 PM PST 24
Peak memory	201476 kb
Host	smart-58c83ab4-1ba1-429f-b4c6-403ec54be96e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432695868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all .2432695868
Directory	/workspace/25.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2879890897
Short name	T222
Test name
Test status
Simulation time	266065143694 ps
CPU time	308.27 seconds
Started	Feb 25 12:46:01 PM PST 24
Finished	Feb 25 12:51:09 PM PST 24
Peak memory	210040 kb
Host	smart-b02b789a-73c5-4cca-962b-ffe011031b45
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879890897 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2879890897
Directory	/workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.adc_ctrl_alert_test.1635722947
Short name	T489
Test name
Test status
Simulation time	470422782 ps
CPU time	1.69 seconds
Started	Feb 25 12:46:04 PM PST 24
Finished	Feb 25 12:46:06 PM PST 24
Peak memory	201204 kb
Host	smart-d0564158-14e7-4b76-88ea-98f1b6865249
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635722947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1635722947
Directory	/workspace/26.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.adc_ctrl_clock_gating.732347356
Short name	T144
Test name
Test status
Simulation time	324877113567 ps
CPU time	336.08 seconds
Started	Feb 25 12:46:06 PM PST 24
Finished	Feb 25 12:51:42 PM PST 24
Peak memory	201456 kb
Host	smart-b16be3a4-8750-43be-8b28-8a9e68db7de2
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732347356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati ng.732347356
Directory	/workspace/26.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_both.47048579
Short name	T45
Test name
Test status
Simulation time	162119958576 ps
CPU time	191.27 seconds
Started	Feb 25 12:46:07 PM PST 24
Finished	Feb 25 12:49:18 PM PST 24
Peak memory	201644 kb
Host	smart-c50f1a02-4da1-4dc9-9b83-6cc8f2946f65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47048579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.47048579
Directory	/workspace/26.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_interrupt.2526542976
Short name	T715
Test name
Test status
Simulation time	165124917204 ps
CPU time	351.68 seconds
Started	Feb 25 12:46:06 PM PST 24
Finished	Feb 25 12:51:58 PM PST 24
Peak memory	201568 kb
Host	smart-ae0b63a6-76be-4f90-945c-3c24fdf37c3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2526542976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2526542976
Directory	/workspace/26.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.143726379
Short name	T207
Test name
Test status
Simulation time	491029000956 ps
CPU time	596.79 seconds
Started	Feb 25 12:46:11 PM PST 24
Finished	Feb 25 12:56:09 PM PST 24
Peak memory	201360 kb
Host	smart-08bf99f3-37e6-4a39-ae82-1258ea1da8bb
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=143726379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup t_fixed.143726379
Directory	/workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_polled.1661926243
Short name	T288
Test name
Test status
Simulation time	493092893189 ps
CPU time	1074.92 seconds
Started	Feb 25 12:46:12 PM PST 24
Finished	Feb 25 01:04:07 PM PST 24
Peak memory	201228 kb
Host	smart-01b56946-c532-4a38-8ff9-35e5c239422f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1661926243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1661926243
Directory	/workspace/26.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3058147659
Short name	T377
Test name
Test status
Simulation time	332821372549 ps
CPU time	150.27 seconds
Started	Feb 25 12:46:06 PM PST 24
Finished	Feb 25 12:48:37 PM PST 24
Peak memory	201468 kb
Host	smart-3f23cc4e-3571-4474-83d7-bb56d76a9dd9
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058147659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix ed.3058147659
Directory	/workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_wakeup.167914924
Short name	T304
Test name
Test status
Simulation time	505329467198 ps
CPU time	1194.19 seconds
Started	Feb 25 12:46:11 PM PST 24
Finished	Feb 25 01:06:06 PM PST 24
Peak memory	201484 kb
Host	smart-0f40f597-9f17-4837-86f9-af063923b1b0
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167914924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_ wakeup.167914924
Directory	/workspace/26.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2097227364
Short name	T674
Test name
Test status
Simulation time	167617764828 ps
CPU time	362.47 seconds
Started	Feb 25 12:46:12 PM PST 24
Finished	Feb 25 12:52:15 PM PST 24
Peak memory	201232 kb
Host	smart-82968621-71d8-4347-992f-8f5b6d6cd9e7
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097227364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26 .adc_ctrl_filters_wakeup_fixed.2097227364
Directory	/workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/26.adc_ctrl_fsm_reset.128331009
Short name	T562
Test name
Test status
Simulation time	71861037222 ps
CPU time	277.16 seconds
Started	Feb 25 12:46:06 PM PST 24
Finished	Feb 25 12:50:43 PM PST 24
Peak memory	201780 kb
Host	smart-0b0ad135-1c2d-418d-ab62-150dd49a2ef3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=128331009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.128331009
Directory	/workspace/26.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/26.adc_ctrl_lowpower_counter.2344680132
Short name	T494
Test name
Test status
Simulation time	26717396525 ps
CPU time	16.85 seconds
Started	Feb 25 12:46:06 PM PST 24
Finished	Feb 25 12:46:23 PM PST 24
Peak memory	201272 kb
Host	smart-5d27e16e-4861-4142-b7de-2d2e210946fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2344680132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2344680132
Directory	/workspace/26.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/26.adc_ctrl_poweron_counter.1092439534
Short name	T408
Test name
Test status
Simulation time	4902809472 ps
CPU time	1.87 seconds
Started	Feb 25 12:46:11 PM PST 24
Finished	Feb 25 12:46:13 PM PST 24
Peak memory	201300 kb
Host	smart-d99a9e73-72e9-4c08-b946-7543e3cc7566
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1092439534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1092439534
Directory	/workspace/26.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/26.adc_ctrl_smoke.1022713146
Short name	T541
Test name
Test status
Simulation time	5752165580 ps
CPU time	4.12 seconds
Started	Feb 25 12:46:08 PM PST 24
Finished	Feb 25 12:46:13 PM PST 24
Peak memory	201176 kb
Host	smart-696b01b3-47cf-4e96-a3d9-f0f36ccbc3e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1022713146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1022713146
Directory	/workspace/26.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.adc_ctrl_stress_all.349365483
Short name	T22
Test name
Test status
Simulation time	153377099987 ps
CPU time	843.83 seconds
Started	Feb 25 12:46:11 PM PST 24
Finished	Feb 25 01:00:15 PM PST 24
Peak memory	201864 kb
Host	smart-1fbf91f2-3430-4afe-b053-4ec8e8857cba
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349365483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all. 349365483
Directory	/workspace/26.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1868806746
Short name	T709
Test name
Test status
Simulation time	181570475520 ps
CPU time	374.82 seconds
Started	Feb 25 12:46:06 PM PST 24
Finished	Feb 25 12:52:22 PM PST 24
Peak memory	210300 kb
Host	smart-cef3e470-6b17-429b-b841-f691531cb11c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868806746 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1868806746
Directory	/workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.adc_ctrl_alert_test.3498129764
Short name	T522
Test name
Test status
Simulation time	323900212 ps
CPU time	1.07 seconds
Started	Feb 25 12:46:10 PM PST 24
Finished	Feb 25 12:46:11 PM PST 24
Peak memory	201204 kb
Host	smart-bf6382bf-edf6-4a52-98aa-e95dd05a918a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498129764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3498129764
Directory	/workspace/27.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.adc_ctrl_clock_gating.2278786114
Short name	T246
Test name
Test status
Simulation time	497318386112 ps
CPU time	253.85 seconds
Started	Feb 25 12:46:08 PM PST 24
Finished	Feb 25 12:50:23 PM PST 24
Peak memory	201464 kb
Host	smart-ae78fa79-77e9-4be7-b554-7ae20a9fe144
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278786114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat ing.2278786114
Directory	/workspace/27.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_both.3447527174
Short name	T191
Test name
Test status
Simulation time	171920518383 ps
CPU time	102.64 seconds
Started	Feb 25 12:46:08 PM PST 24
Finished	Feb 25 12:47:51 PM PST 24
Peak memory	201424 kb
Host	smart-fb03bfa5-0177-4fee-8fa0-34e4b720356c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3447527174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3447527174
Directory	/workspace/27.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2891605882
Short name	T452
Test name
Test status
Simulation time	491513126362 ps
CPU time	1129.61 seconds
Started	Feb 25 12:46:11 PM PST 24
Finished	Feb 25 01:05:01 PM PST 24
Peak memory	201404 kb
Host	smart-7d7a3c9a-8c88-40a8-a2ba-4562b0173791
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891605882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru pt_fixed.2891605882
Directory	/workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_polled.3899482484
Short name	T743
Test name
Test status
Simulation time	320483085925 ps
CPU time	204.73 seconds
Started	Feb 25 12:46:09 PM PST 24
Finished	Feb 25 12:49:34 PM PST 24
Peak memory	201528 kb
Host	smart-12ab0748-89ee-4891-9117-f63eb5a52c32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3899482484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3899482484
Directory	/workspace/27.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2359319713
Short name	T754
Test name
Test status
Simulation time	169520543356 ps
CPU time	205.4 seconds
Started	Feb 25 12:46:09 PM PST 24
Finished	Feb 25 12:49:35 PM PST 24
Peak memory	201404 kb
Host	smart-0d72d158-d33d-4c05-853c-2f1316b7b4ac
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359319713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix ed.2359319713
Directory	/workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_wakeup.3489883596
Short name	T267
Test name
Test status
Simulation time	365171240666 ps
CPU time	60.19 seconds
Started	Feb 25 12:46:07 PM PST 24
Finished	Feb 25 12:47:07 PM PST 24
Peak memory	201552 kb
Host	smart-898673d3-0150-429f-9a6d-ab34ec224828
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489883596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters _wakeup.3489883596
Directory	/workspace/27.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.4084865170
Short name	T134
Test name
Test status
Simulation time	329028970439 ps
CPU time	152.84 seconds
Started	Feb 25 12:46:09 PM PST 24
Finished	Feb 25 12:48:43 PM PST 24
Peak memory	201404 kb
Host	smart-a2dfe694-1b32-4983-9f26-0cfca928dee5
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084865170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27 .adc_ctrl_filters_wakeup_fixed.4084865170
Directory	/workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/27.adc_ctrl_fsm_reset.1777969808
Short name	T361
Test name
Test status
Simulation time	101355396144 ps
CPU time	475.52 seconds
Started	Feb 25 12:46:10 PM PST 24
Finished	Feb 25 12:54:05 PM PST 24
Peak memory	201724 kb
Host	smart-478432ff-6398-40f6-b06b-d422b3c959da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1777969808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1777969808
Directory	/workspace/27.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/27.adc_ctrl_lowpower_counter.1608509838
Short name	T492
Test name
Test status
Simulation time	44206567528 ps
CPU time	47.71 seconds
Started	Feb 25 12:46:08 PM PST 24
Finished	Feb 25 12:46:56 PM PST 24
Peak memory	201272 kb
Host	smart-973129b6-c0aa-4232-b474-22c815824ac9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608509838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1608509838
Directory	/workspace/27.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/27.adc_ctrl_poweron_counter.1475494477
Short name	T627
Test name
Test status
Simulation time	3615126057 ps
CPU time	2.65 seconds
Started	Feb 25 12:46:09 PM PST 24
Finished	Feb 25 12:46:12 PM PST 24
Peak memory	201224 kb
Host	smart-48b02a8e-39eb-4773-b178-8fa46d98d71b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1475494477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1475494477
Directory	/workspace/27.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/27.adc_ctrl_smoke.2802767964
Short name	T583
Test name
Test status
Simulation time	5593314638 ps
CPU time	12.94 seconds
Started	Feb 25 12:46:07 PM PST 24
Finished	Feb 25 12:46:21 PM PST 24
Peak memory	201124 kb
Host	smart-ead6de14-41cb-47c1-aeb9-ceb171178981
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2802767964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2802767964
Directory	/workspace/27.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.adc_ctrl_stress_all.4262064552
Short name	T792
Test name
Test status
Simulation time	170037442439 ps
CPU time	96.86 seconds
Started	Feb 25 12:46:10 PM PST 24
Finished	Feb 25 12:47:47 PM PST 24
Peak memory	201552 kb
Host	smart-3c04c428-025d-42e7-964e-f9dca08541bc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262064552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all .4262064552
Directory	/workspace/27.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.42385495
Short name	T208
Test name
Test status
Simulation time	64978785244 ps
CPU time	65.73 seconds
Started	Feb 25 12:46:11 PM PST 24
Finished	Feb 25 12:47:17 PM PST 24
Peak memory	210172 kb
Host	smart-94d98053-6623-4ec1-8041-f654aab4beff
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42385495 -assert nopos tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.42385495
Directory	/workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.adc_ctrl_alert_test.2737054194
Short name	T775
Test name
Test status
Simulation time	449982470 ps
CPU time	1.26 seconds
Started	Feb 25 12:46:16 PM PST 24
Finished	Feb 25 12:46:18 PM PST 24
Peak memory	201220 kb
Host	smart-d3b978f5-33ab-47c0-90c3-ff1a72b02eed
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737054194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2737054194
Directory	/workspace/28.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_both.3890300849
Short name	T778
Test name
Test status
Simulation time	333470456911 ps
CPU time	146.47 seconds
Started	Feb 25 12:46:16 PM PST 24
Finished	Feb 25 12:48:42 PM PST 24
Peak memory	201572 kb
Host	smart-b71550c2-5c86-4582-ba9b-d19539f3b146
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3890300849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3890300849
Directory	/workspace/28.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_interrupt.3896876724
Short name	T115
Test name
Test status
Simulation time	325600228860 ps
CPU time	156.07 seconds
Started	Feb 25 12:46:18 PM PST 24
Finished	Feb 25 12:48:54 PM PST 24
Peak memory	201480 kb
Host	smart-db497ddc-86d5-475e-a1c6-4138ddd3324d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3896876724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3896876724
Directory	/workspace/28.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1953486752
Short name	T517
Test name
Test status
Simulation time	324009612837 ps
CPU time	302.83 seconds
Started	Feb 25 12:46:15 PM PST 24
Finished	Feb 25 12:51:18 PM PST 24
Peak memory	201408 kb
Host	smart-3c0a6b2d-aeef-4d61-8034-afa738fd467a
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953486752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru pt_fixed.1953486752
Directory	/workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_polled.1841580700
Short name	T752
Test name
Test status
Simulation time	159696428042 ps
CPU time	84.01 seconds
Started	Feb 25 12:46:10 PM PST 24
Finished	Feb 25 12:47:34 PM PST 24
Peak memory	201552 kb
Host	smart-7230bf96-c1b5-4781-aeed-6eab8e4eb2f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1841580700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1841580700
Directory	/workspace/28.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.686500237
Short name	T138
Test name
Test status
Simulation time	165484069010 ps
CPU time	168.03 seconds
Started	Feb 25 12:46:11 PM PST 24
Finished	Feb 25 12:49:00 PM PST 24
Peak memory	201404 kb
Host	smart-3ffb2b3c-86e8-493b-b580-2c09863180ba
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=686500237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe d.686500237
Directory	/workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_wakeup.134890675
Short name	T148
Test name
Test status
Simulation time	502712231264 ps
CPU time	177.73 seconds
Started	Feb 25 12:46:17 PM PST 24
Finished	Feb 25 12:49:15 PM PST 24
Peak memory	201416 kb
Host	smart-406f654d-4162-40f8-86da-4ca4c9448323
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134890675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_ wakeup.134890675
Directory	/workspace/28.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2103824149
Short name	T395
Test name
Test status
Simulation time	492562350921 ps
CPU time	301.02 seconds
Started	Feb 25 12:46:18 PM PST 24
Finished	Feb 25 12:51:19 PM PST 24
Peak memory	201468 kb
Host	smart-c35c8ce9-8791-408a-94e4-2ccfb4b0821c
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103824149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28 .adc_ctrl_filters_wakeup_fixed.2103824149
Directory	/workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/28.adc_ctrl_fsm_reset.1398755792
Short name	T236
Test name
Test status
Simulation time	105428609855 ps
CPU time	532.72 seconds
Started	Feb 25 12:46:20 PM PST 24
Finished	Feb 25 12:55:13 PM PST 24
Peak memory	201848 kb
Host	smart-c43be715-2739-48a9-bedd-3f9ae8a91acb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1398755792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1398755792
Directory	/workspace/28.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/28.adc_ctrl_lowpower_counter.3312212409
Short name	T420
Test name
Test status
Simulation time	32908360234 ps
CPU time	78.85 seconds
Started	Feb 25 12:46:17 PM PST 24
Finished	Feb 25 12:47:36 PM PST 24
Peak memory	201148 kb
Host	smart-6f911080-b108-493e-8668-4aa15cfde9ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3312212409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3312212409
Directory	/workspace/28.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/28.adc_ctrl_poweron_counter.1750369822
Short name	T635
Test name
Test status
Simulation time	4709698097 ps
CPU time	6.25 seconds
Started	Feb 25 12:46:17 PM PST 24
Finished	Feb 25 12:46:23 PM PST 24
Peak memory	201304 kb
Host	smart-04d5c5ca-f296-4434-835b-a1165dc38e67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1750369822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1750369822
Directory	/workspace/28.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/28.adc_ctrl_smoke.3805524721
Short name	T400
Test name
Test status
Simulation time	5895903012 ps
CPU time	3.35 seconds
Started	Feb 25 12:46:07 PM PST 24
Finished	Feb 25 12:46:11 PM PST 24
Peak memory	201180 kb
Host	smart-67fc063a-f083-4ae2-8d10-e6e1bb38901a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3805524721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3805524721
Directory	/workspace/28.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1454671584
Short name	T14
Test name
Test status
Simulation time	348076862091 ps
CPU time	408.98 seconds
Started	Feb 25 12:46:18 PM PST 24
Finished	Feb 25 12:53:07 PM PST 24
Peak memory	210156 kb
Host	smart-13bd6d4c-4042-4112-8bdf-268f965edb02
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454671584 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1454671584
Directory	/workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.adc_ctrl_alert_test.2791732251
Short name	T37
Test name
Test status
Simulation time	308690734 ps
CPU time	1.32 seconds
Started	Feb 25 12:46:23 PM PST 24
Finished	Feb 25 12:46:25 PM PST 24
Peak memory	201232 kb
Host	smart-821ba2c9-333a-47ef-afea-f245c9c8e68b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791732251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2791732251
Directory	/workspace/29.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_both.3614834932
Short name	T707
Test name
Test status
Simulation time	490330759531 ps
CPU time	1143.04 seconds
Started	Feb 25 12:46:21 PM PST 24
Finished	Feb 25 01:05:24 PM PST 24
Peak memory	201572 kb
Host	smart-1b49efd4-5e8f-4574-a214-6df40e91ccce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3614834932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3614834932
Directory	/workspace/29.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_interrupt.1890876307
Short name	T532
Test name
Test status
Simulation time	323418425847 ps
CPU time	799.32 seconds
Started	Feb 25 12:46:22 PM PST 24
Finished	Feb 25 12:59:41 PM PST 24
Peak memory	201476 kb
Host	smart-00512dff-31ff-4771-8a7f-7038a900b2ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1890876307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1890876307
Directory	/workspace/29.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2532118123
Short name	T785
Test name
Test status
Simulation time	316737016394 ps
CPU time	716.1 seconds
Started	Feb 25 12:46:19 PM PST 24
Finished	Feb 25 12:58:16 PM PST 24
Peak memory	201400 kb
Host	smart-f6dad123-0eb6-4c84-9906-b3a16b359220
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532118123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru pt_fixed.2532118123
Directory	/workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_polled.4172688248
Short name	T299
Test name
Test status
Simulation time	325726367291 ps
CPU time	394.02 seconds
Started	Feb 25 12:46:20 PM PST 24
Finished	Feb 25 12:52:54 PM PST 24
Peak memory	201668 kb
Host	smart-5da17376-e35f-4d6e-b0d2-b2d33a0bc2da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4172688248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.4172688248
Directory	/workspace/29.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1796435156
Short name	T668
Test name
Test status
Simulation time	487851249839 ps
CPU time	1064.67 seconds
Started	Feb 25 12:46:19 PM PST 24
Finished	Feb 25 01:04:04 PM PST 24
Peak memory	201400 kb
Host	smart-894636e3-eb20-4787-ab72-6cc07bcc6135
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796435156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix ed.1796435156
Directory	/workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_wakeup.1031779539
Short name	T579
Test name
Test status
Simulation time	167701626408 ps
CPU time	365.37 seconds
Started	Feb 25 12:46:17 PM PST 24
Finished	Feb 25 12:52:24 PM PST 24
Peak memory	201412 kb
Host	smart-5e3308ee-02dd-4449-955a-1a15a1e00689
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031779539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters _wakeup.1031779539
Directory	/workspace/29.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3341641229
Short name	T406
Test name
Test status
Simulation time	324942178880 ps
CPU time	676.81 seconds
Started	Feb 25 12:46:28 PM PST 24
Finished	Feb 25 12:57:45 PM PST 24
Peak memory	201480 kb
Host	smart-4576e11f-6468-4df5-b373-ea098632f2cf
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341641229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29 .adc_ctrl_filters_wakeup_fixed.3341641229
Directory	/workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/29.adc_ctrl_fsm_reset.941679
Short name	T233
Test name
Test status
Simulation time	89769711844 ps
CPU time	449.55 seconds
Started	Feb 25 12:46:24 PM PST 24
Finished	Feb 25 12:53:54 PM PST 24
Peak memory	201792 kb
Host	smart-b77589b2-5030-42f1-af79-af549c8eb477
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=941679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.941679
Directory	/workspace/29.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/29.adc_ctrl_lowpower_counter.1178765278
Short name	T783
Test name
Test status
Simulation time	30874793539 ps
CPU time	17.29 seconds
Started	Feb 25 12:46:23 PM PST 24
Finished	Feb 25 12:46:40 PM PST 24
Peak memory	201248 kb
Host	smart-543a701f-d6c7-452d-9e6c-479420f0b6ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1178765278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1178765278
Directory	/workspace/29.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/29.adc_ctrl_poweron_counter.4094136735
Short name	T515
Test name
Test status
Simulation time	3885845559 ps
CPU time	5.35 seconds
Started	Feb 25 12:46:22 PM PST 24
Finished	Feb 25 12:46:28 PM PST 24
Peak memory	201284 kb
Host	smart-7cc8a867-ecb3-4b96-9296-33123051c6cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4094136735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.4094136735
Directory	/workspace/29.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/29.adc_ctrl_smoke.2032676468
Short name	T421
Test name
Test status
Simulation time	5573060803 ps
CPU time	4.43 seconds
Started	Feb 25 12:46:19 PM PST 24
Finished	Feb 25 12:46:23 PM PST 24
Peak memory	201168 kb
Host	smart-4341c59c-232a-42a2-8e46-55b68441ff48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2032676468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2032676468
Directory	/workspace/29.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.adc_ctrl_stress_all.2875022322
Short name	T618
Test name
Test status
Simulation time	172009051926 ps
CPU time	206.94 seconds
Started	Feb 25 12:46:26 PM PST 24
Finished	Feb 25 12:49:53 PM PST 24
Peak memory	201420 kb
Host	smart-bb25bedf-117c-400f-abee-8bf5b6659a61
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875022322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all .2875022322
Directory	/workspace/29.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.adc_ctrl_alert_test.2247115072
Short name	T596
Test name
Test status
Simulation time	454048944 ps
CPU time	1.6 seconds
Started	Feb 25 12:44:54 PM PST 24
Finished	Feb 25 12:44:56 PM PST 24
Peak memory	201156 kb
Host	smart-7296c371-7461-40b2-a6c9-32960f8e5865
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247115072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2247115072
Directory	/workspace/3.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_interrupt.368203827
Short name	T591
Test name
Test status
Simulation time	163125652360 ps
CPU time	360.57 seconds
Started	Feb 25 12:44:44 PM PST 24
Finished	Feb 25 12:50:45 PM PST 24
Peak memory	201416 kb
Host	smart-1f9bbb3e-f6d0-445a-8074-7d23fc20ee51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=368203827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.368203827
Directory	/workspace/3.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1127451925
Short name	T368
Test name
Test status
Simulation time	487842346431 ps
CPU time	558.76 seconds
Started	Feb 25 12:44:43 PM PST 24
Finished	Feb 25 12:54:02 PM PST 24
Peak memory	201376 kb
Host	smart-a1085528-fd42-40b0-b645-b27afcca5804
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127451925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup t_fixed.1127451925
Directory	/workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_polled.2858344609
Short name	T141
Test name
Test status
Simulation time	487833843010 ps
CPU time	1164.22 seconds
Started	Feb 25 12:44:41 PM PST 24
Finished	Feb 25 01:04:05 PM PST 24
Peak memory	201460 kb
Host	smart-eb57d29f-194c-4ab9-a6cd-a942a54bd779
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2858344609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2858344609
Directory	/workspace/3.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.845553193
Short name	T793
Test name
Test status
Simulation time	321962919432 ps
CPU time	177.39 seconds
Started	Feb 25 12:44:42 PM PST 24
Finished	Feb 25 12:47:39 PM PST 24
Peak memory	201464 kb
Host	smart-02c405a5-89e3-4cfa-9246-1d59e542bbbe
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=845553193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed .845553193
Directory	/workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_wakeup.3321511751
Short name	T274
Test name
Test status
Simulation time	486084128548 ps
CPU time	521.21 seconds
Started	Feb 25 12:44:43 PM PST 24
Finished	Feb 25 12:53:24 PM PST 24
Peak memory	201412 kb
Host	smart-8d9e02d7-998f-4e28-803b-88004c942144
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321511751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_ wakeup.3321511751
Directory	/workspace/3.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1182167236
Short name	T748
Test name
Test status
Simulation time	499718395591 ps
CPU time	270.48 seconds
Started	Feb 25 12:44:37 PM PST 24
Finished	Feb 25 12:49:07 PM PST 24
Peak memory	201544 kb
Host	smart-ca091dc4-58bf-46e7-90ef-210be53a7f54
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182167236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. adc_ctrl_filters_wakeup_fixed.1182167236
Directory	/workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/3.adc_ctrl_fsm_reset.156176188
Short name	T363
Test name
Test status
Simulation time	118962964246 ps
CPU time	610.39 seconds
Started	Feb 25 12:44:46 PM PST 24
Finished	Feb 25 12:54:56 PM PST 24
Peak memory	201836 kb
Host	smart-6a794d8a-bb65-46fc-a34c-4ac03316a8c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=156176188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.156176188
Directory	/workspace/3.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/3.adc_ctrl_lowpower_counter.2392979527
Short name	T434
Test name
Test status
Simulation time	27993665626 ps
CPU time	32.63 seconds
Started	Feb 25 12:44:45 PM PST 24
Finished	Feb 25 12:45:18 PM PST 24
Peak memory	201284 kb
Host	smart-1ddf0967-156b-47e6-8f81-5138898b45d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2392979527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2392979527
Directory	/workspace/3.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/3.adc_ctrl_poweron_counter.3330289933
Short name	T449
Test name
Test status
Simulation time	3218289222 ps
CPU time	2.82 seconds
Started	Feb 25 12:44:40 PM PST 24
Finished	Feb 25 12:44:43 PM PST 24
Peak memory	201288 kb
Host	smart-f2ff9788-93b6-4fec-9328-80f010d7313b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3330289933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3330289933
Directory	/workspace/3.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/3.adc_ctrl_sec_cm.1973698562
Short name	T41
Test name
Test status
Simulation time	4165074958 ps
CPU time	7.21 seconds
Started	Feb 25 12:44:54 PM PST 24
Finished	Feb 25 12:45:01 PM PST 24
Peak memory	216424 kb
Host	smart-b933cc10-31b2-402d-a471-225fa0009791
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973698562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1973698562
Directory	/workspace/3.adc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.adc_ctrl_smoke.3036056854
Short name	T679
Test name
Test status
Simulation time	5961692703 ps
CPU time	14.69 seconds
Started	Feb 25 12:44:42 PM PST 24
Finished	Feb 25 12:44:56 PM PST 24
Peak memory	201276 kb
Host	smart-3664a6d1-fed0-4578-8307-4de50482c688
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3036056854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3036056854
Directory	/workspace/3.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.adc_ctrl_stress_all.2975980487
Short name	T360
Test name
Test status
Simulation time	246143741361 ps
CPU time	748.03 seconds
Started	Feb 25 12:44:49 PM PST 24
Finished	Feb 25 12:57:17 PM PST 24
Peak memory	211136 kb
Host	smart-9d63852b-4368-4d98-b489-31d4bff32765
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975980487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all. 2975980487
Directory	/workspace/3.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3443065341
Short name	T73
Test name
Test status
Simulation time	200807705683 ps
CPU time	249.66 seconds
Started	Feb 25 12:44:37 PM PST 24
Finished	Feb 25 12:48:47 PM PST 24
Peak memory	217524 kb
Host	smart-22d35e41-b484-4a86-811d-b9e0c5c4a540
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443065341 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3443065341
Directory	/workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.adc_ctrl_alert_test.2595698309
Short name	T476
Test name
Test status
Simulation time	430279948 ps
CPU time	1.06 seconds
Started	Feb 25 12:46:35 PM PST 24
Finished	Feb 25 12:46:36 PM PST 24
Peak memory	201148 kb
Host	smart-735e4c2c-8f0d-4d04-9fff-17104b908ad2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595698309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2595698309
Directory	/workspace/30.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.adc_ctrl_clock_gating.4258952192
Short name	T639
Test name
Test status
Simulation time	484840059457 ps
CPU time	399.6 seconds
Started	Feb 25 12:46:24 PM PST 24
Finished	Feb 25 12:53:04 PM PST 24
Peak memory	201484 kb
Host	smart-b80bb9c6-fd22-40ca-8919-4adb1d52979a
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258952192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat ing.4258952192
Directory	/workspace/30.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_interrupt.3254405883
Short name	T282
Test name
Test status
Simulation time	492921041805 ps
CPU time	1104.12 seconds
Started	Feb 25 12:46:23 PM PST 24
Finished	Feb 25 01:04:47 PM PST 24
Peak memory	201368 kb
Host	smart-029fa33c-0d76-412d-ae67-aec7ae975004
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3254405883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3254405883
Directory	/workspace/30.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1096903911
Short name	T528
Test name
Test status
Simulation time	170593658542 ps
CPU time	195.43 seconds
Started	Feb 25 12:46:28 PM PST 24
Finished	Feb 25 12:49:44 PM PST 24
Peak memory	201528 kb
Host	smart-770c03f3-f69f-4d26-84a3-5d8c384eba13
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096903911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru pt_fixed.1096903911
Directory	/workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_polled.1448112611
Short name	T312
Test name
Test status
Simulation time	480588391054 ps
CPU time	1077.04 seconds
Started	Feb 25 12:46:24 PM PST 24
Finished	Feb 25 01:04:21 PM PST 24
Peak memory	201472 kb
Host	smart-4a9c923f-7a17-44f3-b0b2-b1c2c4d623af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1448112611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1448112611
Directory	/workspace/30.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.412719277
Short name	T594
Test name
Test status
Simulation time	327188151319 ps
CPU time	293.42 seconds
Started	Feb 25 12:46:27 PM PST 24
Finished	Feb 25 12:51:21 PM PST 24
Peak memory	201460 kb
Host	smart-b92f1464-cc1a-4010-b384-17082fbd2577
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=412719277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe d.412719277
Directory	/workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_wakeup.3413457439
Short name	T156
Test name
Test status
Simulation time	323812441143 ps
CPU time	379.83 seconds
Started	Feb 25 12:46:28 PM PST 24
Finished	Feb 25 12:52:48 PM PST 24
Peak memory	201532 kb
Host	smart-d23df566-bbaa-4020-827b-198d23f64fe0
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413457439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters _wakeup.3413457439
Directory	/workspace/30.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3102430472
Short name	T184
Test name
Test status
Simulation time	327637906612 ps
CPU time	193.73 seconds
Started	Feb 25 12:46:24 PM PST 24
Finished	Feb 25 12:49:38 PM PST 24
Peak memory	201416 kb
Host	smart-4d9a63e9-8529-4484-a597-1c5d014c17b8
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102430472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30 .adc_ctrl_filters_wakeup_fixed.3102430472
Directory	/workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/30.adc_ctrl_fsm_reset.2110298478
Short name	T693
Test name
Test status
Simulation time	129846773099 ps
CPU time	418.57 seconds
Started	Feb 25 12:46:33 PM PST 24
Finished	Feb 25 12:53:32 PM PST 24
Peak memory	201832 kb
Host	smart-a7bc1da6-d2e1-457c-96c5-8dc6811c152f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2110298478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2110298478
Directory	/workspace/30.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/30.adc_ctrl_lowpower_counter.2714454810
Short name	T580
Test name
Test status
Simulation time	47344543492 ps
CPU time	6.13 seconds
Started	Feb 25 12:46:33 PM PST 24
Finished	Feb 25 12:46:39 PM PST 24
Peak memory	201268 kb
Host	smart-e7ebcde8-e7ed-48f1-94f1-a908ed80b0f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2714454810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2714454810
Directory	/workspace/30.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/30.adc_ctrl_poweron_counter.2825334456
Short name	T487
Test name
Test status
Simulation time	5259917741 ps
CPU time	11.85 seconds
Started	Feb 25 12:46:35 PM PST 24
Finished	Feb 25 12:46:47 PM PST 24
Peak memory	201200 kb
Host	smart-78bc8de0-fe2b-4145-81f1-e67d3e0b47c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2825334456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2825334456
Directory	/workspace/30.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/30.adc_ctrl_smoke.3652906660
Short name	T396
Test name
Test status
Simulation time	5934414817 ps
CPU time	7.89 seconds
Started	Feb 25 12:46:22 PM PST 24
Finished	Feb 25 12:46:30 PM PST 24
Peak memory	201244 kb
Host	smart-cb486933-adb8-4a3d-9963-a42c246ca258
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3652906660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3652906660
Directory	/workspace/30.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.adc_ctrl_stress_all.3853070049
Short name	T479
Test name
Test status
Simulation time	462368884897 ps
CPU time	1389.66 seconds
Started	Feb 25 12:46:33 PM PST 24
Finished	Feb 25 01:09:44 PM PST 24
Peak memory	209988 kb
Host	smart-50b61e0e-7c24-417a-be56-8578fdb4bc4e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853070049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all .3853070049
Directory	/workspace/30.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.adc_ctrl_alert_test.3389357653
Short name	T653
Test name
Test status
Simulation time	351741234 ps
CPU time	0.97 seconds
Started	Feb 25 12:46:40 PM PST 24
Finished	Feb 25 12:46:41 PM PST 24
Peak memory	201220 kb
Host	smart-d70d61fe-6fe1-4ee4-a127-ebbb4146f27a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389357653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3389357653
Directory	/workspace/31.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.adc_ctrl_clock_gating.2889506730
Short name	T283
Test name
Test status
Simulation time	488844307356 ps
CPU time	397.88 seconds
Started	Feb 25 12:46:42 PM PST 24
Finished	Feb 25 12:53:21 PM PST 24
Peak memory	201552 kb
Host	smart-e3e37441-e09b-4ba6-a80e-68dbfeb412c4
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889506730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat ing.2889506730
Directory	/workspace/31.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_both.479733221
Short name	T678
Test name
Test status
Simulation time	508376719270 ps
CPU time	1074.83 seconds
Started	Feb 25 12:46:40 PM PST 24
Finished	Feb 25 01:04:35 PM PST 24
Peak memory	201544 kb
Host	smart-c8224c55-994d-4b42-8a01-0b8bb3d9b442
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=479733221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.479733221
Directory	/workspace/31.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_interrupt.3718662174
Short name	T588
Test name
Test status
Simulation time	158124265902 ps
CPU time	144.42 seconds
Started	Feb 25 12:46:34 PM PST 24
Finished	Feb 25 12:48:59 PM PST 24
Peak memory	201480 kb
Host	smart-76584a93-2449-402e-983f-17bcb9068b1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3718662174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3718662174
Directory	/workspace/31.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2557667506
Short name	T382
Test name
Test status
Simulation time	484660449259 ps
CPU time	289.21 seconds
Started	Feb 25 12:46:34 PM PST 24
Finished	Feb 25 12:51:23 PM PST 24
Peak memory	201468 kb
Host	smart-bda91e06-cca6-49d3-bc3d-a02455adca05
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557667506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru pt_fixed.2557667506
Directory	/workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_polled.2016540952
Short name	T330
Test name
Test status
Simulation time	323193744337 ps
CPU time	186.63 seconds
Started	Feb 25 12:46:32 PM PST 24
Finished	Feb 25 12:49:39 PM PST 24
Peak memory	201460 kb
Host	smart-a528f591-b2f6-48db-85dc-de69e4f51138
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2016540952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2016540952
Directory	/workspace/31.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.936209171
Short name	T524
Test name
Test status
Simulation time	163825261564 ps
CPU time	348.79 seconds
Started	Feb 25 12:46:40 PM PST 24
Finished	Feb 25 12:52:29 PM PST 24
Peak memory	201460 kb
Host	smart-9a25e8b9-f47e-4a89-bcd6-64c787e8ebfe
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=936209171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe d.936209171
Directory	/workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_wakeup.4284716048
Short name	T720
Test name
Test status
Simulation time	344820163025 ps
CPU time	773.26 seconds
Started	Feb 25 12:46:41 PM PST 24
Finished	Feb 25 12:59:34 PM PST 24
Peak memory	201408 kb
Host	smart-ebc21cf7-4abe-4110-8875-c6305590c3cc
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284716048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters _wakeup.4284716048
Directory	/workspace/31.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3805001166
Short name	T411
Test name
Test status
Simulation time	164562474605 ps
CPU time	63.66 seconds
Started	Feb 25 12:46:40 PM PST 24
Finished	Feb 25 12:47:43 PM PST 24
Peak memory	201532 kb
Host	smart-f2907596-2f67-44f9-b9f1-32878cdf88f9
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805001166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31 .adc_ctrl_filters_wakeup_fixed.3805001166
Directory	/workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/31.adc_ctrl_fsm_reset.4014449024
Short name	T513
Test name
Test status
Simulation time	108054758005 ps
CPU time	382.16 seconds
Started	Feb 25 12:46:43 PM PST 24
Finished	Feb 25 12:53:06 PM PST 24
Peak memory	201784 kb
Host	smart-c4115d67-ade7-4621-8ce9-0897fb23bc65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4014449024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.4014449024
Directory	/workspace/31.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/31.adc_ctrl_lowpower_counter.4057295073
Short name	T626
Test name
Test status
Simulation time	31179679172 ps
CPU time	18 seconds
Started	Feb 25 12:46:40 PM PST 24
Finished	Feb 25 12:46:58 PM PST 24
Peak memory	201268 kb
Host	smart-7de1c080-9e5b-4c81-8fcd-cd57950a437e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4057295073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.4057295073
Directory	/workspace/31.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/31.adc_ctrl_poweron_counter.3949757378
Short name	T563
Test name
Test status
Simulation time	4476568366 ps
CPU time	10.07 seconds
Started	Feb 25 12:46:39 PM PST 24
Finished	Feb 25 12:46:49 PM PST 24
Peak memory	201288 kb
Host	smart-14e79797-48ef-4d74-aacb-60726aaab5c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3949757378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3949757378
Directory	/workspace/31.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/31.adc_ctrl_smoke.3501191394
Short name	T404
Test name
Test status
Simulation time	5696541259 ps
CPU time	7.26 seconds
Started	Feb 25 12:46:34 PM PST 24
Finished	Feb 25 12:46:42 PM PST 24
Peak memory	201272 kb
Host	smart-48e98c12-66f8-472c-ab7f-cc5a5cbd4a44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3501191394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3501191394
Directory	/workspace/31.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3308869758
Short name	T211
Test name
Test status
Simulation time	43448982130 ps
CPU time	51.39 seconds
Started	Feb 25 12:46:44 PM PST 24
Finished	Feb 25 12:47:36 PM PST 24
Peak memory	209852 kb
Host	smart-8db5b3cc-642a-421b-8e92-9c95e1a20330
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308869758 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3308869758
Directory	/workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.adc_ctrl_alert_test.1580828540
Short name	T398
Test name
Test status
Simulation time	532280269 ps
CPU time	1.83 seconds
Started	Feb 25 12:46:49 PM PST 24
Finished	Feb 25 12:46:51 PM PST 24
Peak memory	201120 kb
Host	smart-1e5ce6af-db91-4bf6-af5f-b7d0fbba4225
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580828540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1580828540
Directory	/workspace/32.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_interrupt.3211433530
Short name	T147
Test name
Test status
Simulation time	157812272062 ps
CPU time	94.25 seconds
Started	Feb 25 12:46:43 PM PST 24
Finished	Feb 25 12:48:18 PM PST 24
Peak memory	201540 kb
Host	smart-0e032dac-a803-4c4c-9094-9949d668eeaf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3211433530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3211433530
Directory	/workspace/32.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3833457681
Short name	T767
Test name
Test status
Simulation time	488173418836 ps
CPU time	294.96 seconds
Started	Feb 25 12:46:50 PM PST 24
Finished	Feb 25 12:51:45 PM PST 24
Peak memory	201468 kb
Host	smart-0d41b7af-3025-43cc-9565-8f66917bde02
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833457681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru pt_fixed.3833457681
Directory	/workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_polled.154314229
Short name	T177
Test name
Test status
Simulation time	326116288898 ps
CPU time	136.73 seconds
Started	Feb 25 12:46:43 PM PST 24
Finished	Feb 25 12:49:01 PM PST 24
Peak memory	201476 kb
Host	smart-8d65f90b-77b7-4438-bc8d-0a955b72d9b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=154314229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.154314229
Directory	/workspace/32.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2119243540
Short name	T733
Test name
Test status
Simulation time	162281555292 ps
CPU time	196.85 seconds
Started	Feb 25 12:46:39 PM PST 24
Finished	Feb 25 12:49:56 PM PST 24
Peak memory	201524 kb
Host	smart-adf14631-0969-4874-b889-5c67296875fc
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119243540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix ed.2119243540
Directory	/workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_wakeup.2146761714
Short name	T643
Test name
Test status
Simulation time	161294597949 ps
CPU time	191.86 seconds
Started	Feb 25 12:46:48 PM PST 24
Finished	Feb 25 12:50:01 PM PST 24
Peak memory	201416 kb
Host	smart-211b1fa6-a31c-4ec9-81cd-919bc07c4adc
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146761714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters _wakeup.2146761714
Directory	/workspace/32.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1950567441
Short name	T667
Test name
Test status
Simulation time	492507563455 ps
CPU time	1051.76 seconds
Started	Feb 25 12:46:51 PM PST 24
Finished	Feb 25 01:04:23 PM PST 24
Peak memory	201404 kb
Host	smart-017a5640-cdf7-4264-8c86-9772279386d2
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950567441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32 .adc_ctrl_filters_wakeup_fixed.1950567441
Directory	/workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/32.adc_ctrl_fsm_reset.984187254
Short name	T235
Test name
Test status
Simulation time	90467001083 ps
CPU time	288.74 seconds
Started	Feb 25 12:46:50 PM PST 24
Finished	Feb 25 12:51:39 PM PST 24
Peak memory	201800 kb
Host	smart-deff0b44-945b-4d54-b3d8-ca4ddef5ad90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=984187254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.984187254
Directory	/workspace/32.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/32.adc_ctrl_lowpower_counter.3395696110
Short name	T568
Test name
Test status
Simulation time	34324263673 ps
CPU time	77.25 seconds
Started	Feb 25 12:46:50 PM PST 24
Finished	Feb 25 12:48:08 PM PST 24
Peak memory	201272 kb
Host	smart-3196b953-a1df-451c-868a-90aa061ce5ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3395696110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3395696110
Directory	/workspace/32.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/32.adc_ctrl_poweron_counter.233876053
Short name	T448
Test name
Test status
Simulation time	5182747046 ps
CPU time	12.56 seconds
Started	Feb 25 12:46:50 PM PST 24
Finished	Feb 25 12:47:03 PM PST 24
Peak memory	201348 kb
Host	smart-583b7eb4-ef58-41ac-991b-dce6a3f663cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=233876053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.233876053
Directory	/workspace/32.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/32.adc_ctrl_smoke.650102902
Short name	T510
Test name
Test status
Simulation time	5785904172 ps
CPU time	9.16 seconds
Started	Feb 25 12:46:42 PM PST 24
Finished	Feb 25 12:46:51 PM PST 24
Peak memory	201224 kb
Host	smart-aec5c987-3aac-4d91-b986-b9fdd663daef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=650102902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.650102902
Directory	/workspace/32.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.adc_ctrl_stress_all.3993833430
Short name	T139
Test name
Test status
Simulation time	487015840367 ps
CPU time	558.46 seconds
Started	Feb 25 12:46:47 PM PST 24
Finished	Feb 25 12:56:06 PM PST 24
Peak memory	201460 kb
Host	smart-6a49c1ba-1876-4a70-8628-ad2c8416b177
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993833430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all .3993833430
Directory	/workspace/32.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.42204953
Short name	T56
Test name
Test status
Simulation time	114539796057 ps
CPU time	113.79 seconds
Started	Feb 25 12:46:51 PM PST 24
Finished	Feb 25 12:48:44 PM PST 24
Peak memory	210184 kb
Host	smart-f9c94abe-69c3-4816-a52f-5afee4c52629
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42204953 -assert nopos tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.42204953
Directory	/workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.adc_ctrl_alert_test.3951287649
Short name	T616
Test name
Test status
Simulation time	352450409 ps
CPU time	1.02 seconds
Started	Feb 25 12:46:56 PM PST 24
Finished	Feb 25 12:46:57 PM PST 24
Peak memory	201156 kb
Host	smart-74f80dd4-761d-46ae-83e6-f8ba5526b783
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951287649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3951287649
Directory	/workspace/33.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_interrupt.223543287
Short name	T738
Test name
Test status
Simulation time	327360526214 ps
CPU time	387.41 seconds
Started	Feb 25 12:46:50 PM PST 24
Finished	Feb 25 12:53:17 PM PST 24
Peak memory	201536 kb
Host	smart-45c81e4e-eba1-4500-8511-3321d697cb69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=223543287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.223543287
Directory	/workspace/33.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1388289760
Short name	T645
Test name
Test status
Simulation time	500969381341 ps
CPU time	1261.63 seconds
Started	Feb 25 12:46:48 PM PST 24
Finished	Feb 25 01:07:50 PM PST 24
Peak memory	201608 kb
Host	smart-32f39a8f-b6dd-4059-b924-bd89bb9405a6
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388289760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru pt_fixed.1388289760
Directory	/workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_polled.3016352151
Short name	T308
Test name
Test status
Simulation time	329859241708 ps
CPU time	787.26 seconds
Started	Feb 25 12:46:48 PM PST 24
Finished	Feb 25 12:59:56 PM PST 24
Peak memory	201416 kb
Host	smart-db7142b2-3199-4974-a15b-94e293294d75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3016352151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3016352151
Directory	/workspace/33.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.656438757
Short name	T11
Test name
Test status
Simulation time	493739125783 ps
CPU time	1049.26 seconds
Started	Feb 25 12:46:50 PM PST 24
Finished	Feb 25 01:04:20 PM PST 24
Peak memory	201464 kb
Host	smart-f2a5d439-9bfe-4b74-aa67-2fc4c911e132
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=656438757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe d.656438757
Directory	/workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_wakeup.214342827
Short name	T572
Test name
Test status
Simulation time	164669196395 ps
CPU time	183.24 seconds
Started	Feb 25 12:46:50 PM PST 24
Finished	Feb 25 12:49:53 PM PST 24
Peak memory	201396 kb
Host	smart-77e040d8-c7ee-4ccc-90bb-10d612142a91
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214342827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_ wakeup.214342827
Directory	/workspace/33.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1257541250
Short name	T467
Test name
Test status
Simulation time	166302507184 ps
CPU time	311.78 seconds
Started	Feb 25 12:46:50 PM PST 24
Finished	Feb 25 12:52:02 PM PST 24
Peak memory	201444 kb
Host	smart-ffff1032-fb1a-4a30-8735-371cd9723400
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257541250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33 .adc_ctrl_filters_wakeup_fixed.1257541250
Directory	/workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/33.adc_ctrl_fsm_reset.1017462526
Short name	T631
Test name
Test status
Simulation time	82970767822 ps
CPU time	494.78 seconds
Started	Feb 25 12:46:50 PM PST 24
Finished	Feb 25 12:55:05 PM PST 24
Peak memory	201860 kb
Host	smart-0643c944-1d88-4642-8272-4ddf935dcbc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1017462526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1017462526
Directory	/workspace/33.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/33.adc_ctrl_lowpower_counter.1437485709
Short name	T599
Test name
Test status
Simulation time	30717051887 ps
CPU time	64.99 seconds
Started	Feb 25 12:46:50 PM PST 24
Finished	Feb 25 12:47:56 PM PST 24
Peak memory	201280 kb
Host	smart-a1f0c31b-95e7-4abf-830f-15edf1ed36dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1437485709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1437485709
Directory	/workspace/33.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/33.adc_ctrl_poweron_counter.3153932516
Short name	T186
Test name
Test status
Simulation time	2987039291 ps
CPU time	7.13 seconds
Started	Feb 25 12:46:50 PM PST 24
Finished	Feb 25 12:46:57 PM PST 24
Peak memory	201168 kb
Host	smart-c5432e61-132c-43ff-b5f3-9ab645bc9185
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3153932516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3153932516
Directory	/workspace/33.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/33.adc_ctrl_smoke.4208000117
Short name	T546
Test name
Test status
Simulation time	5650526619 ps
CPU time	12.67 seconds
Started	Feb 25 12:46:49 PM PST 24
Finished	Feb 25 12:47:02 PM PST 24
Peak memory	201212 kb
Host	smart-c7aa7592-fd89-4ef1-90b5-a1c8501b0b19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4208000117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.4208000117
Directory	/workspace/33.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.adc_ctrl_stress_all.4009997272
Short name	T151
Test name
Test status
Simulation time	171876943821 ps
CPU time	344.44 seconds
Started	Feb 25 12:46:59 PM PST 24
Finished	Feb 25 12:52:44 PM PST 24
Peak memory	201472 kb
Host	smart-2a9b4c0c-9d36-4d3b-81b1-5394b4cb3ead
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009997272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all .4009997272
Directory	/workspace/33.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3665376790
Short name	T220
Test name
Test status
Simulation time	77468828541 ps
CPU time	61.39 seconds
Started	Feb 25 12:47:13 PM PST 24
Finished	Feb 25 12:48:14 PM PST 24
Peak memory	218208 kb
Host	smart-b45a0d90-a5c0-47d3-9066-721c01a55d7d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665376790 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3665376790
Directory	/workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.adc_ctrl_alert_test.4096558330
Short name	T664
Test name
Test status
Simulation time	356493774 ps
CPU time	1.37 seconds
Started	Feb 25 12:46:58 PM PST 24
Finished	Feb 25 12:47:00 PM PST 24
Peak memory	201212 kb
Host	smart-a57afbe4-a89f-453e-b8a1-2cc678c5f364
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096558330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.4096558330
Directory	/workspace/34.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_interrupt.3620440424
Short name	T772
Test name
Test status
Simulation time	484250042934 ps
CPU time	353.06 seconds
Started	Feb 25 12:46:59 PM PST 24
Finished	Feb 25 12:52:52 PM PST 24
Peak memory	201480 kb
Host	smart-fcaa82c0-5bc2-4ee3-89e9-6903c0eaa821
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3620440424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3620440424
Directory	/workspace/34.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.4242910021
Short name	T412
Test name
Test status
Simulation time	484015320795 ps
CPU time	881.64 seconds
Started	Feb 25 12:46:58 PM PST 24
Finished	Feb 25 01:01:40 PM PST 24
Peak memory	201464 kb
Host	smart-0823c1e3-a48d-465d-a1ca-2e0924ab907a
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242910021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru pt_fixed.4242910021
Directory	/workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_polled.2027691598
Short name	T334
Test name
Test status
Simulation time	320857626218 ps
CPU time	765.84 seconds
Started	Feb 25 12:46:57 PM PST 24
Finished	Feb 25 12:59:43 PM PST 24
Peak memory	201580 kb
Host	smart-d5a83aca-24f5-4955-8d07-b17455d33e8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027691598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2027691598
Directory	/workspace/34.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3167011368
Short name	T188
Test name
Test status
Simulation time	163121852884 ps
CPU time	194.97 seconds
Started	Feb 25 12:47:01 PM PST 24
Finished	Feb 25 12:50:16 PM PST 24
Peak memory	201444 kb
Host	smart-0c5eae7e-61af-4fbe-bc4a-98e1d73afc00
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167011368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix ed.3167011368
Directory	/workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_wakeup.3488864591
Short name	T175
Test name
Test status
Simulation time	332477802668 ps
CPU time	183.59 seconds
Started	Feb 25 12:46:58 PM PST 24
Finished	Feb 25 12:50:02 PM PST 24
Peak memory	201536 kb
Host	smart-248d1adf-7f9e-4dd9-813b-3fd9ff28de71
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488864591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters _wakeup.3488864591
Directory	/workspace/34.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3817183394
Short name	T764
Test name
Test status
Simulation time	163809118949 ps
CPU time	376.26 seconds
Started	Feb 25 12:46:58 PM PST 24
Finished	Feb 25 12:53:14 PM PST 24
Peak memory	201556 kb
Host	smart-83aa4a26-a033-4700-ae3b-46317bb660f3
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817183394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34 .adc_ctrl_filters_wakeup_fixed.3817183394
Directory	/workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/34.adc_ctrl_fsm_reset.910729222
Short name	T228
Test name
Test status
Simulation time	72916212945 ps
CPU time	255.96 seconds
Started	Feb 25 12:46:59 PM PST 24
Finished	Feb 25 12:51:15 PM PST 24
Peak memory	201720 kb
Host	smart-70c4cb26-7aef-4ea3-ab42-d5db398b1814
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=910729222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.910729222
Directory	/workspace/34.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/34.adc_ctrl_lowpower_counter.3288618484
Short name	T519
Test name
Test status
Simulation time	29382215116 ps
CPU time	16.46 seconds
Started	Feb 25 12:47:13 PM PST 24
Finished	Feb 25 12:47:29 PM PST 24
Peak memory	201288 kb
Host	smart-2c2b7561-459f-44db-9a3f-4fee2755b18c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3288618484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3288618484
Directory	/workspace/34.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/34.adc_ctrl_poweron_counter.2685050092
Short name	T464
Test name
Test status
Simulation time	4801907397 ps
CPU time	5.4 seconds
Started	Feb 25 12:47:13 PM PST 24
Finished	Feb 25 12:47:18 PM PST 24
Peak memory	200824 kb
Host	smart-b0956c81-7686-4d8a-9ac3-4d49030f576f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2685050092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2685050092
Directory	/workspace/34.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/34.adc_ctrl_smoke.3674196274
Short name	T444
Test name
Test status
Simulation time	5733769273 ps
CPU time	4.17 seconds
Started	Feb 25 12:46:56 PM PST 24
Finished	Feb 25 12:47:01 PM PST 24
Peak memory	201236 kb
Host	smart-c5a95378-6641-4a22-b3e5-e44d528a3a99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3674196274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3674196274
Directory	/workspace/34.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2441366134
Short name	T223
Test name
Test status
Simulation time	126549348036 ps
CPU time	371.41 seconds
Started	Feb 25 12:46:59 PM PST 24
Finished	Feb 25 12:53:11 PM PST 24
Peak memory	210164 kb
Host	smart-129d8466-8b0b-472a-8d29-86ac6a75c361
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441366134 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2441366134
Directory	/workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.adc_ctrl_alert_test.2482663904
Short name	T484
Test name
Test status
Simulation time	509558220 ps
CPU time	0.82 seconds
Started	Feb 25 12:47:05 PM PST 24
Finished	Feb 25 12:47:06 PM PST 24
Peak memory	201212 kb
Host	smart-150809f6-3e17-431b-8829-8721ca8d621f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482663904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2482663904
Directory	/workspace/35.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_both.1653892346
Short name	T143
Test name
Test status
Simulation time	327522127432 ps
CPU time	116.66 seconds
Started	Feb 25 12:47:08 PM PST 24
Finished	Feb 25 12:49:06 PM PST 24
Peak memory	201540 kb
Host	smart-ecd750bf-5c21-4d7c-9f6b-2f5f4a3be36b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1653892346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1653892346
Directory	/workspace/35.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_interrupt.3765932126
Short name	T445
Test name
Test status
Simulation time	160529476386 ps
CPU time	184.6 seconds
Started	Feb 25 12:47:06 PM PST 24
Finished	Feb 25 12:50:11 PM PST 24
Peak memory	201412 kb
Host	smart-d45ac8a7-3f52-4600-a704-2e93ae928f75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3765932126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3765932126
Directory	/workspace/35.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1185813238
Short name	T470
Test name
Test status
Simulation time	486550816794 ps
CPU time	1041.78 seconds
Started	Feb 25 12:47:03 PM PST 24
Finished	Feb 25 01:04:26 PM PST 24
Peak memory	201524 kb
Host	smart-ca3d75f7-381d-4afe-885f-f4938804b4eb
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185813238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru pt_fixed.1185813238
Directory	/workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_polled.2232862425
Short name	T402
Test name
Test status
Simulation time	167660390451 ps
CPU time	196.4 seconds
Started	Feb 25 12:46:58 PM PST 24
Finished	Feb 25 12:50:14 PM PST 24
Peak memory	201480 kb
Host	smart-e9791641-1bab-4cc8-8d3f-2a0656d9969d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2232862425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2232862425
Directory	/workspace/35.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.345824766
Short name	T410
Test name
Test status
Simulation time	162201488625 ps
CPU time	36.56 seconds
Started	Feb 25 12:47:04 PM PST 24
Finished	Feb 25 12:47:41 PM PST 24
Peak memory	201504 kb
Host	smart-051d9149-6a5d-4fd2-bb37-9aa8c3b98a67
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=345824766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe d.345824766
Directory	/workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_wakeup.3908884964
Short name	T600
Test name
Test status
Simulation time	161141345034 ps
CPU time	362.89 seconds
Started	Feb 25 12:47:07 PM PST 24
Finished	Feb 25 12:53:10 PM PST 24
Peak memory	201404 kb
Host	smart-1fc39a60-555b-4c8e-afaa-86a1992c3960
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908884964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters _wakeup.3908884964
Directory	/workspace/35.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2186246431
Short name	T397
Test name
Test status
Simulation time	499999690858 ps
CPU time	278.06 seconds
Started	Feb 25 12:47:14 PM PST 24
Finished	Feb 25 12:51:53 PM PST 24
Peak memory	201488 kb
Host	smart-77754447-cf82-4d0e-9349-705b43e2d2d3
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186246431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35 .adc_ctrl_filters_wakeup_fixed.2186246431
Directory	/workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/35.adc_ctrl_lowpower_counter.2592834316
Short name	T469
Test name
Test status
Simulation time	31556470878 ps
CPU time	9.52 seconds
Started	Feb 25 12:47:05 PM PST 24
Finished	Feb 25 12:47:15 PM PST 24
Peak memory	201184 kb
Host	smart-428d936a-8996-42db-afc5-7f3ee100ce27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2592834316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2592834316
Directory	/workspace/35.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/35.adc_ctrl_poweron_counter.3100428214
Short name	T672
Test name
Test status
Simulation time	4855091398 ps
CPU time	3.44 seconds
Started	Feb 25 12:47:04 PM PST 24
Finished	Feb 25 12:47:08 PM PST 24
Peak memory	201200 kb
Host	smart-f2eff54a-c4bc-4339-9c48-76db2c153f4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3100428214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3100428214
Directory	/workspace/35.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/35.adc_ctrl_smoke.2726568013
Short name	T677
Test name
Test status
Simulation time	5541114041 ps
CPU time	14.55 seconds
Started	Feb 25 12:46:57 PM PST 24
Finished	Feb 25 12:47:12 PM PST 24
Peak memory	201204 kb
Host	smart-bac124a8-cc66-4d0a-8f97-3c47e6aef6e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2726568013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2726568013
Directory	/workspace/35.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.adc_ctrl_stress_all.2980453133
Short name	T547
Test name
Test status
Simulation time	56490770326 ps
CPU time	31.62 seconds
Started	Feb 25 12:47:03 PM PST 24
Finished	Feb 25 12:47:35 PM PST 24
Peak memory	201276 kb
Host	smart-fd325d41-92ee-4b93-be85-3fd9e3949b3b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980453133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all .2980453133
Directory	/workspace/35.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.616697707
Short name	T569
Test name
Test status
Simulation time	186184728642 ps
CPU time	516.78 seconds
Started	Feb 25 12:47:14 PM PST 24
Finished	Feb 25 12:55:52 PM PST 24
Peak memory	210168 kb
Host	smart-8121bba2-8622-4b14-9799-31c37068c249
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616697707 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.616697707
Directory	/workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.adc_ctrl_alert_test.648873568
Short name	T670
Test name
Test status
Simulation time	437564338 ps
CPU time	0.87 seconds
Started	Feb 25 12:47:13 PM PST 24
Finished	Feb 25 12:47:15 PM PST 24
Peak memory	201348 kb
Host	smart-6321e792-af67-4fa5-bec8-e314e413b1ac
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648873568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.648873568
Directory	/workspace/36.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_both.1846151072
Short name	T698
Test name
Test status
Simulation time	338620646765 ps
CPU time	375.07 seconds
Started	Feb 25 12:47:17 PM PST 24
Finished	Feb 25 12:53:32 PM PST 24
Peak memory	201476 kb
Host	smart-12340ff2-0400-40b3-9763-8d61df060cba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1846151072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1846151072
Directory	/workspace/36.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_interrupt.203282881
Short name	T755
Test name
Test status
Simulation time	490605000270 ps
CPU time	297.51 seconds
Started	Feb 25 12:47:28 PM PST 24
Finished	Feb 25 12:52:26 PM PST 24
Peak memory	201544 kb
Host	smart-bb2c7406-0a54-4b3f-b67c-ef26755b5202
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=203282881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.203282881
Directory	/workspace/36.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1957281949
Short name	T375
Test name
Test status
Simulation time	493842666937 ps
CPU time	1150.86 seconds
Started	Feb 25 12:47:15 PM PST 24
Finished	Feb 25 01:06:26 PM PST 24
Peak memory	201444 kb
Host	smart-84d43774-2dbc-4ffb-b983-0348e661a8cf
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957281949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru pt_fixed.1957281949
Directory	/workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_polled.856551019
Short name	T701
Test name
Test status
Simulation time	331122970926 ps
CPU time	197.26 seconds
Started	Feb 25 12:47:13 PM PST 24
Finished	Feb 25 12:50:30 PM PST 24
Peak memory	201408 kb
Host	smart-7af0c2a5-7896-422e-bc46-3da63a900761
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=856551019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.856551019
Directory	/workspace/36.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3500500858
Short name	T3
Test name
Test status
Simulation time	161204252907 ps
CPU time	106.65 seconds
Started	Feb 25 12:47:14 PM PST 24
Finished	Feb 25 12:49:02 PM PST 24
Peak memory	201404 kb
Host	smart-549aab4b-6077-45e0-b270-31d9eba0751b
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500500858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix ed.3500500858
Directory	/workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_wakeup.1720948791
Short name	T339
Test name
Test status
Simulation time	504958136389 ps
CPU time	1051.8 seconds
Started	Feb 25 12:47:17 PM PST 24
Finished	Feb 25 01:04:49 PM PST 24
Peak memory	201560 kb
Host	smart-69b81673-9b87-4aa9-8f11-42551bb620d4
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720948791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters _wakeup.1720948791
Directory	/workspace/36.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.637138157
Short name	T214
Test name
Test status
Simulation time	335797071968 ps
CPU time	184.77 seconds
Started	Feb 25 12:47:15 PM PST 24
Finished	Feb 25 12:50:20 PM PST 24
Peak memory	201464 kb
Host	smart-bb43515a-641e-4bbc-857c-fbae4940b6a8
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637138157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36. adc_ctrl_filters_wakeup_fixed.637138157
Directory	/workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/36.adc_ctrl_fsm_reset.875396305
Short name	T2
Test name
Test status
Simulation time	104643417412 ps
CPU time	387.31 seconds
Started	Feb 25 12:47:28 PM PST 24
Finished	Feb 25 12:53:56 PM PST 24
Peak memory	201796 kb
Host	smart-df3221d0-6d48-4670-89a3-977a78cad2d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=875396305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.875396305
Directory	/workspace/36.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/36.adc_ctrl_lowpower_counter.3957109801
Short name	T691
Test name
Test status
Simulation time	34167135893 ps
CPU time	76.07 seconds
Started	Feb 25 12:47:14 PM PST 24
Finished	Feb 25 12:48:32 PM PST 24
Peak memory	201268 kb
Host	smart-509c4205-782b-406d-8394-b6d3646aa21e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3957109801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3957109801
Directory	/workspace/36.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/36.adc_ctrl_poweron_counter.429723503
Short name	T387
Test name
Test status
Simulation time	3746406071 ps
CPU time	2.86 seconds
Started	Feb 25 12:47:13 PM PST 24
Finished	Feb 25 12:47:16 PM PST 24
Peak memory	201168 kb
Host	smart-05748bc7-75ac-403e-aad0-05cf5f30d7df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=429723503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.429723503
Directory	/workspace/36.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/36.adc_ctrl_smoke.1405362265
Short name	T472
Test name
Test status
Simulation time	5815732641 ps
CPU time	16.24 seconds
Started	Feb 25 12:47:05 PM PST 24
Finished	Feb 25 12:47:21 PM PST 24
Peak memory	201232 kb
Host	smart-ba9c0a5f-b959-4b22-9667-7037d43f6dfd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1405362265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1405362265
Directory	/workspace/36.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.adc_ctrl_stress_all.3099351986
Short name	T260
Test name
Test status
Simulation time	341742778258 ps
CPU time	193.93 seconds
Started	Feb 25 12:47:14 PM PST 24
Finished	Feb 25 12:50:29 PM PST 24
Peak memory	201488 kb
Host	smart-10880fe4-40d0-42ef-b9e1-d37e43fc5a74
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099351986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all .3099351986
Directory	/workspace/36.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1688230823
Short name	T53
Test name
Test status
Simulation time	99601063340 ps
CPU time	134.96 seconds
Started	Feb 25 12:47:16 PM PST 24
Finished	Feb 25 12:49:31 PM PST 24
Peak memory	210140 kb
Host	smart-c433e45c-ba47-4d09-ac11-e72aef1204f8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688230823 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1688230823
Directory	/workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.adc_ctrl_alert_test.2485778765
Short name	T502
Test name
Test status
Simulation time	282827411 ps
CPU time	1.24 seconds
Started	Feb 25 12:47:28 PM PST 24
Finished	Feb 25 12:47:30 PM PST 24
Peak memory	201216 kb
Host	smart-f05d4591-43e4-462e-bae1-15e575666ca0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485778765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2485778765
Directory	/workspace/37.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.adc_ctrl_clock_gating.637181025
Short name	T306
Test name
Test status
Simulation time	496434613650 ps
CPU time	191.81 seconds
Started	Feb 25 12:47:24 PM PST 24
Finished	Feb 25 12:50:36 PM PST 24
Peak memory	201476 kb
Host	smart-e1490139-1549-41aa-aaf6-431ea3ef3e40
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637181025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gati ng.637181025
Directory	/workspace/37.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3556367923
Short name	T458
Test name
Test status
Simulation time	161598843469 ps
CPU time	355.48 seconds
Started	Feb 25 12:47:21 PM PST 24
Finished	Feb 25 12:53:17 PM PST 24
Peak memory	201460 kb
Host	smart-028d7e91-a073-453e-a774-891674fe2452
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556367923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru pt_fixed.3556367923
Directory	/workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_polled.3759058796
Short name	T714
Test name
Test status
Simulation time	496260360719 ps
CPU time	98.07 seconds
Started	Feb 25 12:47:20 PM PST 24
Finished	Feb 25 12:48:58 PM PST 24
Peak memory	201460 kb
Host	smart-ea0c7604-991c-4eb3-ab9d-55daf865afe1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3759058796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3759058796
Directory	/workspace/37.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2878569022
Short name	T1
Test name
Test status
Simulation time	330460296263 ps
CPU time	188.39 seconds
Started	Feb 25 12:47:24 PM PST 24
Finished	Feb 25 12:50:33 PM PST 24
Peak memory	201460 kb
Host	smart-e2a1039d-f562-45df-997a-ce97b5045412
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878569022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix ed.2878569022
Directory	/workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_wakeup.2839052344
Short name	T581
Test name
Test status
Simulation time	165132991868 ps
CPU time	363.87 seconds
Started	Feb 25 12:47:20 PM PST 24
Finished	Feb 25 12:53:24 PM PST 24
Peak memory	201556 kb
Host	smart-bcfc4a8e-0e76-4acf-9f1f-d6f0ebc79827
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839052344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters _wakeup.2839052344
Directory	/workspace/37.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3872792319
Short name	T373
Test name
Test status
Simulation time	330868087039 ps
CPU time	796.87 seconds
Started	Feb 25 12:47:19 PM PST 24
Finished	Feb 25 01:00:36 PM PST 24
Peak memory	201460 kb
Host	smart-8a619c45-e9e0-40f4-be99-3d494e5f1807
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872792319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37 .adc_ctrl_filters_wakeup_fixed.3872792319
Directory	/workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/37.adc_ctrl_fsm_reset.941471419
Short name	T544
Test name
Test status
Simulation time	117994861221 ps
CPU time	570.85 seconds
Started	Feb 25 12:47:27 PM PST 24
Finished	Feb 25 12:56:58 PM PST 24
Peak memory	201868 kb
Host	smart-a8dfad2d-068c-485a-bf86-ee2e63573266
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=941471419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.941471419
Directory	/workspace/37.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/37.adc_ctrl_lowpower_counter.1080311778
Short name	T671
Test name
Test status
Simulation time	34867210681 ps
CPU time	79.79 seconds
Started	Feb 25 12:47:27 PM PST 24
Finished	Feb 25 12:48:47 PM PST 24
Peak memory	201288 kb
Host	smart-a8ba817e-6454-45b2-8e9d-15146825d8d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080311778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1080311778
Directory	/workspace/37.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/37.adc_ctrl_poweron_counter.1249718633
Short name	T621
Test name
Test status
Simulation time	4492592470 ps
CPU time	1.91 seconds
Started	Feb 25 12:47:20 PM PST 24
Finished	Feb 25 12:47:22 PM PST 24
Peak memory	201288 kb
Host	smart-caf7ff29-35bf-48c8-af81-1418c7d76281
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249718633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1249718633
Directory	/workspace/37.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/37.adc_ctrl_smoke.2921621358
Short name	T545
Test name
Test status
Simulation time	5821347022 ps
CPU time	14.49 seconds
Started	Feb 25 12:47:24 PM PST 24
Finished	Feb 25 12:47:39 PM PST 24
Peak memory	201136 kb
Host	smart-ae67f52d-d7ee-4381-8574-c3307f117d02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921621358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2921621358
Directory	/workspace/37.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.adc_ctrl_stress_all.3091643948
Short name	T592
Test name
Test status
Simulation time	31208239570 ps
CPU time	18.45 seconds
Started	Feb 25 12:47:31 PM PST 24
Finished	Feb 25 12:47:49 PM PST 24
Peak memory	201276 kb
Host	smart-85540f9f-98bd-447d-bce3-15ccd7aec319
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091643948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all .3091643948
Directory	/workspace/37.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.697167144
Short name	T71
Test name
Test status
Simulation time	363144772830 ps
CPU time	226.39 seconds
Started	Feb 25 12:47:27 PM PST 24
Finished	Feb 25 12:51:14 PM PST 24
Peak memory	210164 kb
Host	smart-243ac703-e92e-4dce-878c-f974efbfab66
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697167144 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.697167144
Directory	/workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.adc_ctrl_alert_test.2964001391
Short name	T394
Test name
Test status
Simulation time	463282329 ps
CPU time	1.57 seconds
Started	Feb 25 12:47:35 PM PST 24
Finished	Feb 25 12:47:37 PM PST 24
Peak memory	201208 kb
Host	smart-5afaf6a5-0192-4907-9079-5da6aeac600a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964001391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2964001391
Directory	/workspace/38.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.adc_ctrl_clock_gating.2624619503
Short name	T237
Test name
Test status
Simulation time	327645911552 ps
CPU time	698.51 seconds
Started	Feb 25 12:47:28 PM PST 24
Finished	Feb 25 12:59:07 PM PST 24
Peak memory	201400 kb
Host	smart-84a5a757-1e98-4049-926e-3f3982155b30
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624619503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat ing.2624619503
Directory	/workspace/38.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_both.3229127437
Short name	T564
Test name
Test status
Simulation time	180065569808 ps
CPU time	108.6 seconds
Started	Feb 25 12:47:26 PM PST 24
Finished	Feb 25 12:49:16 PM PST 24
Peak memory	201388 kb
Host	smart-ad8f094e-aa4e-4c8e-bfef-dfc49d84820d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3229127437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3229127437
Directory	/workspace/38.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_interrupt.4075792085
Short name	T190
Test name
Test status
Simulation time	490846145697 ps
CPU time	1109.97 seconds
Started	Feb 25 12:47:26 PM PST 24
Finished	Feb 25 01:05:57 PM PST 24
Peak memory	201508 kb
Host	smart-ace83d95-7ae8-47b1-8ef0-129ede5996b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4075792085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.4075792085
Directory	/workspace/38.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.656976221
Short name	T511
Test name
Test status
Simulation time	310374965290 ps
CPU time	211.45 seconds
Started	Feb 25 12:47:27 PM PST 24
Finished	Feb 25 12:50:59 PM PST 24
Peak memory	201460 kb
Host	smart-a5b3fcd7-53e5-42f8-b100-443f82d8d659
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=656976221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup t_fixed.656976221
Directory	/workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_polled.1317913831
Short name	T243
Test name
Test status
Simulation time	170446403270 ps
CPU time	400.43 seconds
Started	Feb 25 12:47:29 PM PST 24
Finished	Feb 25 12:54:09 PM PST 24
Peak memory	201496 kb
Host	smart-446e5756-f67c-4342-bc1f-aa051b38f756
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1317913831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1317913831
Directory	/workspace/38.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2956685346
Short name	T617
Test name
Test status
Simulation time	165263924924 ps
CPU time	35.85 seconds
Started	Feb 25 12:47:27 PM PST 24
Finished	Feb 25 12:48:04 PM PST 24
Peak memory	201528 kb
Host	smart-9e375083-a586-432d-bd79-2da757a5dfe5
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956685346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix ed.2956685346
Directory	/workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_wakeup.3190766169
Short name	T747
Test name
Test status
Simulation time	163186277906 ps
CPU time	101.59 seconds
Started	Feb 25 12:47:29 PM PST 24
Finished	Feb 25 12:49:11 PM PST 24
Peak memory	201448 kb
Host	smart-93cd6b4e-32a6-46d9-84da-c86bc6185ade
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190766169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters _wakeup.3190766169
Directory	/workspace/38.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3780708711
Short name	T736
Test name
Test status
Simulation time	509379494443 ps
CPU time	1024.43 seconds
Started	Feb 25 12:47:29 PM PST 24
Finished	Feb 25 01:04:33 PM PST 24
Peak memory	201376 kb
Host	smart-6ca4b915-acc3-47f4-aac2-f01de2cda274
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780708711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38 .adc_ctrl_filters_wakeup_fixed.3780708711
Directory	/workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/38.adc_ctrl_fsm_reset.219454855
Short name	T365
Test name
Test status
Simulation time	106301381284 ps
CPU time	340.09 seconds
Started	Feb 25 12:47:35 PM PST 24
Finished	Feb 25 12:53:15 PM PST 24
Peak memory	201844 kb
Host	smart-7bd11395-28eb-44d7-b317-ab3b94c8b4e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219454855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.219454855
Directory	/workspace/38.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/38.adc_ctrl_lowpower_counter.3859708650
Short name	T649
Test name
Test status
Simulation time	44350477937 ps
CPU time	94.16 seconds
Started	Feb 25 12:47:35 PM PST 24
Finished	Feb 25 12:49:09 PM PST 24
Peak memory	201232 kb
Host	smart-057bb195-fea8-4439-aac0-35013c7cadc0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3859708650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3859708650
Directory	/workspace/38.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/38.adc_ctrl_poweron_counter.904131434
Short name	T465
Test name
Test status
Simulation time	4306912914 ps
CPU time	2.07 seconds
Started	Feb 25 12:47:28 PM PST 24
Finished	Feb 25 12:47:31 PM PST 24
Peak memory	201284 kb
Host	smart-a8a40ac6-d7f0-4fa5-8e98-2e42747d4bc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=904131434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.904131434
Directory	/workspace/38.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/38.adc_ctrl_smoke.534575962
Short name	T704
Test name
Test status
Simulation time	5786565377 ps
CPU time	4.1 seconds
Started	Feb 25 12:47:28 PM PST 24
Finished	Feb 25 12:47:32 PM PST 24
Peak memory	201188 kb
Host	smart-b6986a07-f242-41fe-949d-14517acb6d76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=534575962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.534575962
Directory	/workspace/38.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.adc_ctrl_stress_all.4065318210
Short name	T303
Test name
Test status
Simulation time	498353701739 ps
CPU time	144.82 seconds
Started	Feb 25 12:47:35 PM PST 24
Finished	Feb 25 12:50:00 PM PST 24
Peak memory	201556 kb
Host	smart-9f68d527-22f5-4733-9606-737112439ecb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065318210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all .4065318210
Directory	/workspace/38.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2209859539
Short name	T538
Test name
Test status
Simulation time	77709231234 ps
CPU time	294.63 seconds
Started	Feb 25 12:47:36 PM PST 24
Finished	Feb 25 12:52:30 PM PST 24
Peak memory	202180 kb
Host	smart-c1f76ead-d4d7-4659-88b8-7caf9963cb1e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209859539 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2209859539
Directory	/workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.adc_ctrl_alert_test.3481596013
Short name	T696
Test name
Test status
Simulation time	351954535 ps
CPU time	1.3 seconds
Started	Feb 25 12:47:42 PM PST 24
Finished	Feb 25 12:47:43 PM PST 24
Peak memory	201100 kb
Host	smart-7e515bc3-3d09-491b-9d7c-cc7201877b1e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481596013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3481596013
Directory	/workspace/39.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.adc_ctrl_clock_gating.1071717525
Short name	T716
Test name
Test status
Simulation time	167125819833 ps
CPU time	90.61 seconds
Started	Feb 25 12:47:44 PM PST 24
Finished	Feb 25 12:49:15 PM PST 24
Peak memory	201520 kb
Host	smart-5c0695d2-5826-4606-aa21-38429a990216
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071717525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat ing.1071717525
Directory	/workspace/39.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_both.3360375526
Short name	T795
Test name
Test status
Simulation time	338242226539 ps
CPU time	416.48 seconds
Started	Feb 25 12:47:42 PM PST 24
Finished	Feb 25 12:54:39 PM PST 24
Peak memory	201548 kb
Host	smart-c2bf164c-fcae-4591-8501-56faf761ff80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3360375526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3360375526
Directory	/workspace/39.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_interrupt.2425733488
Short name	T737
Test name
Test status
Simulation time	492176641706 ps
CPU time	279.24 seconds
Started	Feb 25 12:47:34 PM PST 24
Finished	Feb 25 12:52:14 PM PST 24
Peak memory	201420 kb
Host	smart-8df12bd5-6abd-4a34-860f-d153897e2966
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2425733488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2425733488
Directory	/workspace/39.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3088572349
Short name	T791
Test name
Test status
Simulation time	165785889067 ps
CPU time	378.25 seconds
Started	Feb 25 12:47:42 PM PST 24
Finished	Feb 25 12:54:01 PM PST 24
Peak memory	201460 kb
Host	smart-653587d9-0a9f-4da0-bbc0-f15b72c45dfa
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088572349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru pt_fixed.3088572349
Directory	/workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_polled.3981013389
Short name	T316
Test name
Test status
Simulation time	510253939041 ps
CPU time	574.96 seconds
Started	Feb 25 12:47:36 PM PST 24
Finished	Feb 25 12:57:11 PM PST 24
Peak memory	201480 kb
Host	smart-271e3727-577d-4350-8dd4-bb0cc3336c71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3981013389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3981013389
Directory	/workspace/39.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3193285106
Short name	T516
Test name
Test status
Simulation time	166472740225 ps
CPU time	388.62 seconds
Started	Feb 25 12:47:34 PM PST 24
Finished	Feb 25 12:54:03 PM PST 24
Peak memory	201404 kb
Host	smart-63eee701-ae75-440e-bb06-47f722b798fa
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193285106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix ed.3193285106
Directory	/workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_wakeup.1491912237
Short name	T172
Test name
Test status
Simulation time	331076961872 ps
CPU time	46.87 seconds
Started	Feb 25 12:47:42 PM PST 24
Finished	Feb 25 12:48:29 PM PST 24
Peak memory	201416 kb
Host	smart-10f08406-53d0-4eb8-84db-078cf2637a1a
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491912237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters _wakeup.1491912237
Directory	/workspace/39.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1848232282
Short name	T753
Test name
Test status
Simulation time	328680466793 ps
CPU time	673.19 seconds
Started	Feb 25 12:47:50 PM PST 24
Finished	Feb 25 12:59:03 PM PST 24
Peak memory	201216 kb
Host	smart-805e01a6-9d72-4177-bf9d-964702681030
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848232282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39 .adc_ctrl_filters_wakeup_fixed.1848232282
Directory	/workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/39.adc_ctrl_fsm_reset.3113143242
Short name	T605
Test name
Test status
Simulation time	124663934156 ps
CPU time	628.09 seconds
Started	Feb 25 12:47:43 PM PST 24
Finished	Feb 25 12:58:11 PM PST 24
Peak memory	201692 kb
Host	smart-cbffa09e-b4b8-436f-b8dc-00b6399cb9f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3113143242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3113143242
Directory	/workspace/39.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/39.adc_ctrl_lowpower_counter.2018801769
Short name	T712
Test name
Test status
Simulation time	36799798664 ps
CPU time	81.47 seconds
Started	Feb 25 12:47:50 PM PST 24
Finished	Feb 25 12:49:12 PM PST 24
Peak memory	200944 kb
Host	smart-f78d283f-f9f0-4208-98dd-ad5b22b5156e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2018801769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2018801769
Directory	/workspace/39.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/39.adc_ctrl_poweron_counter.694170471
Short name	T725
Test name
Test status
Simulation time	4977060674 ps
CPU time	12.66 seconds
Started	Feb 25 12:47:42 PM PST 24
Finished	Feb 25 12:47:55 PM PST 24
Peak memory	201288 kb
Host	smart-64f94b63-b7ef-4129-97df-86dddf9c4254
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=694170471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.694170471
Directory	/workspace/39.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/39.adc_ctrl_smoke.54161804
Short name	T558
Test name
Test status
Simulation time	5937457781 ps
CPU time	4.35 seconds
Started	Feb 25 12:47:38 PM PST 24
Finished	Feb 25 12:47:42 PM PST 24
Peak memory	201220 kb
Host	smart-dea9f779-6169-4dbd-9f39-a28da734b4c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54161804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.54161804
Directory	/workspace/39.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.adc_ctrl_stress_all.482292653
Short name	T202
Test name
Test status
Simulation time	337257064218 ps
CPU time	432.1 seconds
Started	Feb 25 12:47:45 PM PST 24
Finished	Feb 25 12:54:57 PM PST 24
Peak memory	201480 kb
Host	smart-b9af2733-25f4-42c9-bc6d-2f9a30e57eaa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482292653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all. 482292653
Directory	/workspace/39.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.adc_ctrl_alert_test.116175826
Short name	T575
Test name
Test status
Simulation time	468558382 ps
CPU time	1.63 seconds
Started	Feb 25 12:44:53 PM PST 24
Finished	Feb 25 12:44:55 PM PST 24
Peak memory	201208 kb
Host	smart-222c5b78-0090-4149-bdb0-cbe0e0e4e439
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116175826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.116175826
Directory	/workspace/4.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.adc_ctrl_clock_gating.2126979283
Short name	T268
Test name
Test status
Simulation time	323397944129 ps
CPU time	46.46 seconds
Started	Feb 25 12:44:56 PM PST 24
Finished	Feb 25 12:45:43 PM PST 24
Peak memory	201448 kb
Host	smart-ea5b77ea-dd83-4c47-9d08-10f979819df5
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126979283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati ng.2126979283
Directory	/workspace/4.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_both.1083410767
Short name	T249
Test name
Test status
Simulation time	162832676578 ps
CPU time	185.9 seconds
Started	Feb 25 12:44:52 PM PST 24
Finished	Feb 25 12:47:58 PM PST 24
Peak memory	201440 kb
Host	smart-b02c7a39-8258-418c-af96-98d62befee68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1083410767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1083410767
Directory	/workspace/4.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_interrupt.2246291075
Short name	T195
Test name
Test status
Simulation time	490676722301 ps
CPU time	242.33 seconds
Started	Feb 25 12:44:50 PM PST 24
Finished	Feb 25 12:48:52 PM PST 24
Peak memory	201468 kb
Host	smart-08519459-2be2-457e-9357-99cbab81e1f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2246291075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2246291075
Directory	/workspace/4.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_polled.3144831871
Short name	T142
Test name
Test status
Simulation time	162001870534 ps
CPU time	91.68 seconds
Started	Feb 25 12:44:50 PM PST 24
Finished	Feb 25 12:46:22 PM PST 24
Peak memory	201424 kb
Host	smart-04bbfbd4-d7d5-48e1-984f-5607ef12d002
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3144831871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3144831871
Directory	/workspace/4.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2416627675
Short name	T204
Test name
Test status
Simulation time	486128976635 ps
CPU time	1056.77 seconds
Started	Feb 25 12:44:52 PM PST 24
Finished	Feb 25 01:02:29 PM PST 24
Peak memory	201464 kb
Host	smart-a088fc15-ee51-4d3c-9629-ba0574d6e6dd
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416627675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe d.2416627675
Directory	/workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3734662909
Short name	T475
Test name
Test status
Simulation time	159751114302 ps
CPU time	335.87 seconds
Started	Feb 25 12:44:49 PM PST 24
Finished	Feb 25 12:50:25 PM PST 24
Peak memory	201596 kb
Host	smart-11b200ed-93cc-42f0-bc83-634429ada116
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734662909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4. adc_ctrl_filters_wakeup_fixed.3734662909
Directory	/workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/4.adc_ctrl_fsm_reset.1083649225
Short name	T757
Test name
Test status
Simulation time	74737572359 ps
CPU time	322.47 seconds
Started	Feb 25 12:44:49 PM PST 24
Finished	Feb 25 12:50:12 PM PST 24
Peak memory	201748 kb
Host	smart-1f418f4e-5c89-44b1-a709-51b1c34a76ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1083649225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1083649225
Directory	/workspace/4.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/4.adc_ctrl_lowpower_counter.491820836
Short name	T554
Test name
Test status
Simulation time	38651950916 ps
CPU time	22.45 seconds
Started	Feb 25 12:44:50 PM PST 24
Finished	Feb 25 12:45:12 PM PST 24
Peak memory	201328 kb
Host	smart-2fdf7e0c-b7e9-4f73-8c7e-d5d5fb1c1239
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=491820836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.491820836
Directory	/workspace/4.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/4.adc_ctrl_poweron_counter.3991749959
Short name	T49
Test name
Test status
Simulation time	5072593144 ps
CPU time	5.37 seconds
Started	Feb 25 12:44:52 PM PST 24
Finished	Feb 25 12:44:57 PM PST 24
Peak memory	201288 kb
Host	smart-4d93300e-d731-44a6-a183-a898353d6c71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3991749959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3991749959
Directory	/workspace/4.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/4.adc_ctrl_sec_cm.1641804596
Short name	T42
Test name
Test status
Simulation time	7322393643 ps
CPU time	16.67 seconds
Started	Feb 25 12:44:49 PM PST 24
Finished	Feb 25 12:45:06 PM PST 24
Peak memory	216488 kb
Host	smart-29a147ee-d96e-4f0c-aee7-0f892a724539
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641804596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1641804596
Directory	/workspace/4.adc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.adc_ctrl_smoke.3539136008
Short name	T606
Test name
Test status
Simulation time	5892111787 ps
CPU time	14.08 seconds
Started	Feb 25 12:44:51 PM PST 24
Finished	Feb 25 12:45:05 PM PST 24
Peak memory	201228 kb
Host	smart-6e7c76b4-5dc0-48bf-9b82-e3f1f32879aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3539136008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3539136008
Directory	/workspace/4.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.adc_ctrl_stress_all.95970738
Short name	T413
Test name
Test status
Simulation time	22476883340 ps
CPU time	52.72 seconds
Started	Feb 25 12:44:54 PM PST 24
Finished	Feb 25 12:45:47 PM PST 24
Peak memory	201288 kb
Host	smart-33c72f6b-6cd9-43ea-b322-136442db8dd7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95970738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.95970738
Directory	/workspace/4.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.196802685
Short name	T212
Test name
Test status
Simulation time	162474939586 ps
CPU time	500.87 seconds
Started	Feb 25 12:44:48 PM PST 24
Finished	Feb 25 12:53:09 PM PST 24
Peak memory	210176 kb
Host	smart-761e9750-59a3-4d28-901f-35a6d16fc85d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196802685 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.196802685
Directory	/workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.adc_ctrl_alert_test.798989690
Short name	T710
Test name
Test status
Simulation time	422300416 ps
CPU time	0.83 seconds
Started	Feb 25 12:47:54 PM PST 24
Finished	Feb 25 12:47:55 PM PST 24
Peak memory	201136 kb
Host	smart-b53534f1-f45b-44a6-b40a-36f6a6ee5a55
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798989690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.798989690
Directory	/workspace/40.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_both.1918181096
Short name	T298
Test name
Test status
Simulation time	173236809211 ps
CPU time	138.34 seconds
Started	Feb 25 12:47:54 PM PST 24
Finished	Feb 25 12:50:13 PM PST 24
Peak memory	201408 kb
Host	smart-d0838937-ba2b-4eb2-8d76-f6b68675da40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1918181096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1918181096
Directory	/workspace/40.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_interrupt.2324851093
Short name	T164
Test name
Test status
Simulation time	495229786113 ps
CPU time	281.38 seconds
Started	Feb 25 12:47:40 PM PST 24
Finished	Feb 25 12:52:22 PM PST 24
Peak memory	201544 kb
Host	smart-7635eb6c-7e32-41bf-8083-2b69ff11970d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2324851093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2324851093
Directory	/workspace/40.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2635000686
Short name	T430
Test name
Test status
Simulation time	321999491911 ps
CPU time	110.31 seconds
Started	Feb 25 12:47:56 PM PST 24
Finished	Feb 25 12:49:47 PM PST 24
Peak memory	201404 kb
Host	smart-4bdf125d-bff6-4f05-b20f-2764afb625df
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635000686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru pt_fixed.2635000686
Directory	/workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_polled.97284432
Short name	T343
Test name
Test status
Simulation time	158951939279 ps
CPU time	100.2 seconds
Started	Feb 25 12:47:41 PM PST 24
Finished	Feb 25 12:49:22 PM PST 24
Peak memory	201492 kb
Host	smart-3d7286d8-5ba3-4c53-af07-fce1f83ef0ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=97284432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.97284432
Directory	/workspace/40.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2152971563
Short name	T658
Test name
Test status
Simulation time	333116073287 ps
CPU time	744.92 seconds
Started	Feb 25 12:47:45 PM PST 24
Finished	Feb 25 01:00:10 PM PST 24
Peak memory	201464 kb
Host	smart-8bc0f911-ea49-4f51-9c3e-9406e3c27ae9
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152971563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix ed.2152971563
Directory	/workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_wakeup.176712448
Short name	T114
Test name
Test status
Simulation time	335276165883 ps
CPU time	94.87 seconds
Started	Feb 25 12:47:55 PM PST 24
Finished	Feb 25 12:49:30 PM PST 24
Peak memory	201536 kb
Host	smart-7ae59c1d-3925-405f-8c09-758d414bacf7
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176712448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_ wakeup.176712448
Directory	/workspace/40.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2120947192
Short name	T601
Test name
Test status
Simulation time	166789225851 ps
CPU time	348.96 seconds
Started	Feb 25 12:47:54 PM PST 24
Finished	Feb 25 12:53:44 PM PST 24
Peak memory	201484 kb
Host	smart-b6b83d72-fb9c-4ab0-aba0-02912dd37082
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120947192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40 .adc_ctrl_filters_wakeup_fixed.2120947192
Directory	/workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/40.adc_ctrl_fsm_reset.133331008
Short name	T362
Test name
Test status
Simulation time	120733413527 ps
CPU time	663.82 seconds
Started	Feb 25 12:47:55 PM PST 24
Finished	Feb 25 12:59:00 PM PST 24
Peak memory	201880 kb
Host	smart-b0324971-f65d-4b4f-9563-307f0321c1c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=133331008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.133331008
Directory	/workspace/40.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/40.adc_ctrl_lowpower_counter.2890021436
Short name	T722
Test name
Test status
Simulation time	40751064574 ps
CPU time	16.35 seconds
Started	Feb 25 12:47:55 PM PST 24
Finished	Feb 25 12:48:11 PM PST 24
Peak memory	201204 kb
Host	smart-f24ba8c7-8263-4204-aeec-f2b0663e2a08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2890021436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2890021436
Directory	/workspace/40.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/40.adc_ctrl_poweron_counter.1140801139
Short name	T441
Test name
Test status
Simulation time	4619123217 ps
CPU time	11.08 seconds
Started	Feb 25 12:47:53 PM PST 24
Finished	Feb 25 12:48:04 PM PST 24
Peak memory	201228 kb
Host	smart-7970a872-a575-43b3-8bb0-30784e79d3f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1140801139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1140801139
Directory	/workspace/40.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/40.adc_ctrl_smoke.1035886584
Short name	T454
Test name
Test status
Simulation time	5999702643 ps
CPU time	7.95 seconds
Started	Feb 25 12:47:41 PM PST 24
Finished	Feb 25 12:47:49 PM PST 24
Peak memory	201276 kb
Host	smart-1f5942f9-8d76-47f8-800e-5c748850d12c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1035886584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1035886584
Directory	/workspace/40.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.adc_ctrl_stress_all.2157641723
Short name	T314
Test name
Test status
Simulation time	368686574832 ps
CPU time	206.18 seconds
Started	Feb 25 12:47:54 PM PST 24
Finished	Feb 25 12:51:20 PM PST 24
Peak memory	201452 kb
Host	smart-14619e7d-30e2-49d9-92bf-e3962c08ae4a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157641723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all .2157641723
Directory	/workspace/40.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.135641282
Short name	T699
Test name
Test status
Simulation time	15114119544 ps
CPU time	32.62 seconds
Started	Feb 25 12:47:54 PM PST 24
Finished	Feb 25 12:48:26 PM PST 24
Peak memory	201792 kb
Host	smart-934511b8-cb8e-4085-8674-ad2df9994abb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135641282 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.135641282
Directory	/workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.adc_ctrl_alert_test.2715527512
Short name	T700
Test name
Test status
Simulation time	358579691 ps
CPU time	0.81 seconds
Started	Feb 25 12:48:14 PM PST 24
Finished	Feb 25 12:48:15 PM PST 24
Peak memory	201152 kb
Host	smart-6af4e2e4-82ca-4426-b1e2-a125da009858
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715527512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2715527512
Directory	/workspace/41.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_both.2229560671
Short name	T478
Test name
Test status
Simulation time	331281618613 ps
CPU time	744.07 seconds
Started	Feb 25 12:47:57 PM PST 24
Finished	Feb 25 01:00:21 PM PST 24
Peak memory	201540 kb
Host	smart-ae257efe-63c8-4406-8105-1954242398eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2229560671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2229560671
Directory	/workspace/41.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_interrupt.3634901117
Short name	T325
Test name
Test status
Simulation time	492350184589 ps
CPU time	1067.32 seconds
Started	Feb 25 12:47:54 PM PST 24
Finished	Feb 25 01:05:42 PM PST 24
Peak memory	201480 kb
Host	smart-592433c2-5705-450e-a42e-f8dd48bb275e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3634901117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3634901117
Directory	/workspace/41.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2867346473
Short name	T602
Test name
Test status
Simulation time	166881019817 ps
CPU time	182.21 seconds
Started	Feb 25 12:48:02 PM PST 24
Finished	Feb 25 12:51:05 PM PST 24
Peak memory	201524 kb
Host	smart-d21f8490-91df-4240-8a76-9277ea4a2c3b
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867346473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru pt_fixed.2867346473
Directory	/workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_polled.1594134284
Short name	T196
Test name
Test status
Simulation time	331626765561 ps
CPU time	195.39 seconds
Started	Feb 25 12:47:52 PM PST 24
Finished	Feb 25 12:51:07 PM PST 24
Peak memory	201452 kb
Host	smart-3f1b43a3-18b9-4dcd-8f86-d85e1168c2f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1594134284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1594134284
Directory	/workspace/41.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3134034025
Short name	T708
Test name
Test status
Simulation time	171763350168 ps
CPU time	425.92 seconds
Started	Feb 25 12:47:54 PM PST 24
Finished	Feb 25 12:55:00 PM PST 24
Peak memory	201564 kb
Host	smart-239972c5-654b-4481-9c17-7e4983eba24b
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134034025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix ed.3134034025
Directory	/workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1280533338
Short name	T540
Test name
Test status
Simulation time	162963094110 ps
CPU time	208.78 seconds
Started	Feb 25 12:48:01 PM PST 24
Finished	Feb 25 12:51:31 PM PST 24
Peak memory	201568 kb
Host	smart-19dda27c-13c2-412c-b50c-0be523fc0312
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280533338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41 .adc_ctrl_filters_wakeup_fixed.1280533338
Directory	/workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/41.adc_ctrl_fsm_reset.1899468192
Short name	T741
Test name
Test status
Simulation time	73440460501 ps
CPU time	415.93 seconds
Started	Feb 25 12:48:14 PM PST 24
Finished	Feb 25 12:55:10 PM PST 24
Peak memory	201812 kb
Host	smart-530d88a1-d2c2-4f9c-ae6b-44642710d358
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1899468192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1899468192
Directory	/workspace/41.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/41.adc_ctrl_lowpower_counter.3477764359
Short name	T496
Test name
Test status
Simulation time	35674603317 ps
CPU time	83.61 seconds
Started	Feb 25 12:48:13 PM PST 24
Finished	Feb 25 12:49:37 PM PST 24
Peak memory	201212 kb
Host	smart-b47b5213-1f9c-436e-ad03-aeab4fe10f85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3477764359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3477764359
Directory	/workspace/41.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/41.adc_ctrl_poweron_counter.1705029777
Short name	T215
Test name
Test status
Simulation time	4442308550 ps
CPU time	3.15 seconds
Started	Feb 25 12:48:13 PM PST 24
Finished	Feb 25 12:48:17 PM PST 24
Peak memory	201228 kb
Host	smart-69463853-60f9-44f4-9ded-a10b12db60ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1705029777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1705029777
Directory	/workspace/41.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/41.adc_ctrl_smoke.3533428481
Short name	T523
Test name
Test status
Simulation time	5703617239 ps
CPU time	7.6 seconds
Started	Feb 25 12:47:53 PM PST 24
Finished	Feb 25 12:48:01 PM PST 24
Peak memory	201280 kb
Host	smart-01c0cda8-2aef-4d38-ae3d-880f139062cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3533428481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3533428481
Directory	/workspace/41.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1717322925
Short name	T75
Test name
Test status
Simulation time	172117175814 ps
CPU time	177.45 seconds
Started	Feb 25 12:48:00 PM PST 24
Finished	Feb 25 12:50:58 PM PST 24
Peak memory	217328 kb
Host	smart-dad2a9f7-e514-4870-9a69-9c97c2035062
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717322925 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1717322925
Directory	/workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.adc_ctrl_alert_test.1846513691
Short name	T784
Test name
Test status
Simulation time	368576473 ps
CPU time	0.81 seconds
Started	Feb 25 12:48:11 PM PST 24
Finished	Feb 25 12:48:12 PM PST 24
Peak memory	201132 kb
Host	smart-9cf92cdb-625c-4a74-9ec3-7a30ea8f15c9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846513691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1846513691
Directory	/workspace/42.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.adc_ctrl_clock_gating.936176328
Short name	T614
Test name
Test status
Simulation time	497483264592 ps
CPU time	386.66 seconds
Started	Feb 25 12:48:10 PM PST 24
Finished	Feb 25 12:54:37 PM PST 24
Peak memory	201460 kb
Host	smart-95a38d33-ec0b-4218-b7bf-49c0e8e443ae
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936176328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gati ng.936176328
Directory	/workspace/42.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_both.3376702018
Short name	T333
Test name
Test status
Simulation time	497184972459 ps
CPU time	300.61 seconds
Started	Feb 25 12:48:12 PM PST 24
Finished	Feb 25 12:53:13 PM PST 24
Peak memory	201636 kb
Host	smart-7e0eb45a-742c-4894-8310-a4913faab4df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376702018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3376702018
Directory	/workspace/42.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_interrupt.1046957337
Short name	T63
Test name
Test status
Simulation time	163511712776 ps
CPU time	40.21 seconds
Started	Feb 25 12:47:57 PM PST 24
Finished	Feb 25 12:48:37 PM PST 24
Peak memory	201480 kb
Host	smart-641c2b7b-a211-4b31-bb7f-79647ffeafb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1046957337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1046957337
Directory	/workspace/42.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.114697370
Short name	T763
Test name
Test status
Simulation time	329272305272 ps
CPU time	333.42 seconds
Started	Feb 25 12:48:13 PM PST 24
Finished	Feb 25 12:53:46 PM PST 24
Peak memory	201460 kb
Host	smart-aeb187eb-ae0f-4295-9e27-6eafd9adc7c5
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=114697370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup t_fixed.114697370
Directory	/workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_polled.1669012559
Short name	T740
Test name
Test status
Simulation time	322813664310 ps
CPU time	379.86 seconds
Started	Feb 25 12:47:59 PM PST 24
Finished	Feb 25 12:54:19 PM PST 24
Peak memory	201448 kb
Host	smart-0d80ffa5-2876-4acc-bcb1-9da96f0802ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1669012559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1669012559
Directory	/workspace/42.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3380387481
Short name	T174
Test name
Test status
Simulation time	327795572092 ps
CPU time	178.68 seconds
Started	Feb 25 12:47:58 PM PST 24
Finished	Feb 25 12:50:57 PM PST 24
Peak memory	201440 kb
Host	smart-5091f9e9-7502-47c0-948e-0a307b66b64b
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380387481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix ed.3380387481
Directory	/workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3150978067
Short name	T706
Test name
Test status
Simulation time	491249628935 ps
CPU time	292.4 seconds
Started	Feb 25 12:48:11 PM PST 24
Finished	Feb 25 12:53:03 PM PST 24
Peak memory	201484 kb
Host	smart-f1e83877-72b6-4aba-97ef-476b16c02573
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150978067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42 .adc_ctrl_filters_wakeup_fixed.3150978067
Directory	/workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/42.adc_ctrl_fsm_reset.2337747217
Short name	T456
Test name
Test status
Simulation time	111731848167 ps
CPU time	407.1 seconds
Started	Feb 25 12:48:10 PM PST 24
Finished	Feb 25 12:54:57 PM PST 24
Peak memory	201728 kb
Host	smart-ef3a9eb3-8e65-4139-b7a7-23fa220c4fd3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2337747217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2337747217
Directory	/workspace/42.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/42.adc_ctrl_lowpower_counter.3025500357
Short name	T751
Test name
Test status
Simulation time	35787825234 ps
CPU time	22.09 seconds
Started	Feb 25 12:48:10 PM PST 24
Finished	Feb 25 12:48:33 PM PST 24
Peak memory	201224 kb
Host	smart-f7870c77-f3ef-4c29-a043-1ca2485f6d66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3025500357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3025500357
Directory	/workspace/42.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/42.adc_ctrl_poweron_counter.1344197982
Short name	T370
Test name
Test status
Simulation time	4217282962 ps
CPU time	3 seconds
Started	Feb 25 12:48:13 PM PST 24
Finished	Feb 25 12:48:17 PM PST 24
Peak memory	201284 kb
Host	smart-547d4057-9241-4ac1-8456-9a1d79332e03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1344197982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1344197982
Directory	/workspace/42.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/42.adc_ctrl_smoke.4290615475
Short name	T403
Test name
Test status
Simulation time	5511362387 ps
CPU time	1.76 seconds
Started	Feb 25 12:48:04 PM PST 24
Finished	Feb 25 12:48:06 PM PST 24
Peak memory	201280 kb
Host	smart-6ca49c8a-325d-4809-842f-21cde20736bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4290615475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.4290615475
Directory	/workspace/42.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.adc_ctrl_stress_all.62298369
Short name	T332
Test name
Test status
Simulation time	210454054762 ps
CPU time	499.39 seconds
Started	Feb 25 12:48:10 PM PST 24
Finished	Feb 25 12:56:30 PM PST 24
Peak memory	201508 kb
Host	smart-88a235a3-e9c2-4cd7-943c-7647d9efe8d2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62298369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.62298369
Directory	/workspace/42.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1570679574
Short name	T209
Test name
Test status
Simulation time	22170006577 ps
CPU time	25.84 seconds
Started	Feb 25 12:48:10 PM PST 24
Finished	Feb 25 12:48:36 PM PST 24
Peak memory	201652 kb
Host	smart-35992646-ad1f-4ca1-aa6a-f38e7e16e747
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570679574 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1570679574
Directory	/workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.adc_ctrl_alert_test.2244930464
Short name	T433
Test name
Test status
Simulation time	495601833 ps
CPU time	1.71 seconds
Started	Feb 25 12:48:20 PM PST 24
Finished	Feb 25 12:48:22 PM PST 24
Peak memory	201216 kb
Host	smart-deb18504-0fc1-4dda-9329-c27b99a599b2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244930464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2244930464
Directory	/workspace/43.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.adc_ctrl_clock_gating.2702535417
Short name	T193
Test name
Test status
Simulation time	166279996406 ps
CPU time	84.63 seconds
Started	Feb 25 12:48:18 PM PST 24
Finished	Feb 25 12:49:43 PM PST 24
Peak memory	201400 kb
Host	smart-85c6ea6f-2354-4421-b3d7-e16fd293faa6
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702535417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat ing.2702535417
Directory	/workspace/43.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_both.3444737005
Short name	T165
Test name
Test status
Simulation time	496624689183 ps
CPU time	516.97 seconds
Started	Feb 25 12:48:20 PM PST 24
Finished	Feb 25 12:56:57 PM PST 24
Peak memory	201588 kb
Host	smart-981756b3-70ea-4c74-bbca-05ee6d895e1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3444737005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3444737005
Directory	/workspace/43.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_interrupt.3473124755
Short name	T781
Test name
Test status
Simulation time	326700906096 ps
CPU time	760.11 seconds
Started	Feb 25 12:48:23 PM PST 24
Finished	Feb 25 01:01:04 PM PST 24
Peak memory	201484 kb
Host	smart-21b8f307-d336-47a5-a728-419cca877dad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3473124755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3473124755
Directory	/workspace/43.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3409116408
Short name	T428
Test name
Test status
Simulation time	491597480567 ps
CPU time	316.24 seconds
Started	Feb 25 12:48:19 PM PST 24
Finished	Feb 25 12:53:35 PM PST 24
Peak memory	201460 kb
Host	smart-1c01c96c-2f06-4d54-925f-7d37554af5fd
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409116408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru pt_fixed.3409116408
Directory	/workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_polled.2014827441
Short name	T576
Test name
Test status
Simulation time	330426847734 ps
CPU time	371.77 seconds
Started	Feb 25 12:48:09 PM PST 24
Finished	Feb 25 12:54:21 PM PST 24
Peak memory	201544 kb
Host	smart-5b60f2a2-2219-439a-9073-045aa188fd76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2014827441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2014827441
Directory	/workspace/43.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.288966885
Short name	T442
Test name
Test status
Simulation time	164084636614 ps
CPU time	193.51 seconds
Started	Feb 25 12:48:20 PM PST 24
Finished	Feb 25 12:51:34 PM PST 24
Peak memory	201472 kb
Host	smart-56e942cb-e772-4820-99d8-01d0de784f14
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=288966885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe d.288966885
Directory	/workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_wakeup.3667663754
Short name	T351
Test name
Test status
Simulation time	492832345169 ps
CPU time	1174.78 seconds
Started	Feb 25 12:48:20 PM PST 24
Finished	Feb 25 01:07:55 PM PST 24
Peak memory	201476 kb
Host	smart-1e25a990-6e82-4c64-9bc7-b2fcc19c28f6
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667663754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters _wakeup.3667663754
Directory	/workspace/43.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.825493966
Short name	T656
Test name
Test status
Simulation time	163812176088 ps
CPU time	370.94 seconds
Started	Feb 25 12:48:20 PM PST 24
Finished	Feb 25 12:54:32 PM PST 24
Peak memory	201428 kb
Host	smart-10d77afb-034d-49c0-b181-b2afb55ff9e4
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825493966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. adc_ctrl_filters_wakeup_fixed.825493966
Directory	/workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/43.adc_ctrl_fsm_reset.2436264523
Short name	T595
Test name
Test status
Simulation time	98148689266 ps
CPU time	351.44 seconds
Started	Feb 25 12:48:19 PM PST 24
Finished	Feb 25 12:54:11 PM PST 24
Peak memory	201916 kb
Host	smart-29203448-8f3c-48b1-b043-ac2944b3559e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2436264523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2436264523
Directory	/workspace/43.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/43.adc_ctrl_lowpower_counter.899898197
Short name	T766
Test name
Test status
Simulation time	40482498155 ps
CPU time	20.5 seconds
Started	Feb 25 12:48:20 PM PST 24
Finished	Feb 25 12:48:40 PM PST 24
Peak memory	201224 kb
Host	smart-db9fb248-12d6-4f4f-9f78-677b0087b3a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=899898197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.899898197
Directory	/workspace/43.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/43.adc_ctrl_poweron_counter.3600369080
Short name	T688
Test name
Test status
Simulation time	2802595094 ps
CPU time	3.85 seconds
Started	Feb 25 12:48:28 PM PST 24
Finished	Feb 25 12:48:32 PM PST 24
Peak memory	201224 kb
Host	smart-753eed4d-3847-4e5a-9d38-9709c81a9e4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3600369080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3600369080
Directory	/workspace/43.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/43.adc_ctrl_smoke.1634720177
Short name	T503
Test name
Test status
Simulation time	5818248118 ps
CPU time	2.66 seconds
Started	Feb 25 12:48:11 PM PST 24
Finished	Feb 25 12:48:13 PM PST 24
Peak memory	201160 kb
Host	smart-ad7e8340-7101-4349-ae3a-8ba2eb3932c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1634720177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1634720177
Directory	/workspace/43.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.adc_ctrl_stress_all.4143301701
Short name	T637
Test name
Test status
Simulation time	162783578233 ps
CPU time	99.33 seconds
Started	Feb 25 12:48:17 PM PST 24
Finished	Feb 25 12:49:57 PM PST 24
Peak memory	201472 kb
Host	smart-f81f377d-9239-4f2f-be17-d0a3c7b24b76
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143301701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all .4143301701
Directory	/workspace/43.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/44.adc_ctrl_alert_test.3342279447
Short name	T790
Test name
Test status
Simulation time	322863345 ps
CPU time	1.32 seconds
Started	Feb 25 12:48:19 PM PST 24
Finished	Feb 25 12:48:20 PM PST 24
Peak memory	201200 kb
Host	smart-f7d1af91-1160-4cf8-9978-9e44dd44f203
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342279447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3342279447
Directory	/workspace/44.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.adc_ctrl_clock_gating.4231917354
Short name	T327
Test name
Test status
Simulation time	163957251755 ps
CPU time	376.26 seconds
Started	Feb 25 12:48:19 PM PST 24
Finished	Feb 25 12:54:36 PM PST 24
Peak memory	201520 kb
Host	smart-b7f87393-6bcf-4bd7-870b-03a88c148625
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231917354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat ing.4231917354
Directory	/workspace/44.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_both.651894452
Short name	T323
Test name
Test status
Simulation time	338934684199 ps
CPU time	780.25 seconds
Started	Feb 25 12:48:19 PM PST 24
Finished	Feb 25 01:01:19 PM PST 24
Peak memory	201540 kb
Host	smart-5c98a4d5-b214-4082-8f1d-82678f3fa1c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=651894452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.651894452
Directory	/workspace/44.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_interrupt.3155103150
Short name	T124
Test name
Test status
Simulation time	321512018504 ps
CPU time	349.57 seconds
Started	Feb 25 12:48:21 PM PST 24
Finished	Feb 25 12:54:11 PM PST 24
Peak memory	201568 kb
Host	smart-2786ff9b-1cec-4524-8614-2d1223343619
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3155103150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3155103150
Directory	/workspace/44.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.17091375
Short name	T371
Test name
Test status
Simulation time	487643457229 ps
CPU time	1123.33 seconds
Started	Feb 25 12:48:21 PM PST 24
Finished	Feb 25 01:07:05 PM PST 24
Peak memory	201384 kb
Host	smart-4788c083-6459-4063-a0c9-5b872b928a5b
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=17091375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt _fixed.17091375
Directory	/workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_polled.2293410933
Short name	T145
Test name
Test status
Simulation time	499148646167 ps
CPU time	613.45 seconds
Started	Feb 25 12:48:20 PM PST 24
Finished	Feb 25 12:58:34 PM PST 24
Peak memory	201476 kb
Host	smart-34a9f99a-a0c3-46ca-ab6a-4a637961a0fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2293410933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2293410933
Directory	/workspace/44.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.987227955
Short name	T565
Test name
Test status
Simulation time	166591726245 ps
CPU time	103.84 seconds
Started	Feb 25 12:48:18 PM PST 24
Finished	Feb 25 12:50:02 PM PST 24
Peak memory	201404 kb
Host	smart-d1db15ee-fdc0-492b-ac79-f106e0b1fe0b
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=987227955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe d.987227955
Directory	/workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_wakeup.1904631948
Short name	T505
Test name
Test status
Simulation time	339420465235 ps
CPU time	824.76 seconds
Started	Feb 25 12:48:18 PM PST 24
Finished	Feb 25 01:02:03 PM PST 24
Peak memory	201468 kb
Host	smart-6de48f44-8e37-40a0-b6ac-74ae9fd09850
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904631948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters _wakeup.1904631948
Directory	/workspace/44.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1240121495
Short name	T556
Test name
Test status
Simulation time	169014561023 ps
CPU time	368.01 seconds
Started	Feb 25 12:48:18 PM PST 24
Finished	Feb 25 12:54:27 PM PST 24
Peak memory	201472 kb
Host	smart-40c588ba-1ebc-4126-8275-1c1c79bc70cb
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240121495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44 .adc_ctrl_filters_wakeup_fixed.1240121495
Directory	/workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/44.adc_ctrl_fsm_reset.3244656658
Short name	T586
Test name
Test status
Simulation time	106163579262 ps
CPU time	542.6 seconds
Started	Feb 25 12:48:21 PM PST 24
Finished	Feb 25 12:57:24 PM PST 24
Peak memory	201852 kb
Host	smart-027c7847-fa09-4942-ae38-94195f246770
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244656658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3244656658
Directory	/workspace/44.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/44.adc_ctrl_lowpower_counter.1633565348
Short name	T705
Test name
Test status
Simulation time	42864660499 ps
CPU time	92.55 seconds
Started	Feb 25 12:48:28 PM PST 24
Finished	Feb 25 12:50:01 PM PST 24
Peak memory	201212 kb
Host	smart-f12e5020-e1f7-4617-b4f1-bacef8a6885d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1633565348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1633565348
Directory	/workspace/44.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/44.adc_ctrl_poweron_counter.78415431
Short name	T52
Test name
Test status
Simulation time	5314812660 ps
CPU time	6.48 seconds
Started	Feb 25 12:48:20 PM PST 24
Finished	Feb 25 12:48:26 PM PST 24
Peak memory	201272 kb
Host	smart-8dbb0456-aeeb-4c93-98fa-a9929a6e5aa2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78415431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.78415431
Directory	/workspace/44.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/44.adc_ctrl_smoke.109941002
Short name	T381
Test name
Test status
Simulation time	6208361248 ps
CPU time	1.53 seconds
Started	Feb 25 12:48:19 PM PST 24
Finished	Feb 25 12:48:21 PM PST 24
Peak memory	201300 kb
Host	smart-4992414d-3a53-49eb-867e-fa71f06b0698
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109941002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.109941002
Directory	/workspace/44.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.adc_ctrl_stress_all.3487213786
Short name	T585
Test name
Test status
Simulation time	11940244718 ps
CPU time	28.27 seconds
Started	Feb 25 12:48:20 PM PST 24
Finished	Feb 25 12:48:49 PM PST 24
Peak memory	201184 kb
Host	smart-b8ecb779-c993-4f25-b6c8-7c23f908e8c6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487213786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all .3487213786
Directory	/workspace/44.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.adc_ctrl_alert_test.3862063375
Short name	T603
Test name
Test status
Simulation time	419497583 ps
CPU time	1.56 seconds
Started	Feb 25 12:48:27 PM PST 24
Finished	Feb 25 12:48:29 PM PST 24
Peak memory	201160 kb
Host	smart-e3e64490-08cf-4f65-8546-95be8b5f4a0d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862063375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3862063375
Directory	/workspace/45.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_both.2971476587
Short name	T483
Test name
Test status
Simulation time	159826480891 ps
CPU time	69.64 seconds
Started	Feb 25 12:48:30 PM PST 24
Finished	Feb 25 12:49:40 PM PST 24
Peak memory	201436 kb
Host	smart-2f871276-2979-47db-b9e5-2f9ec0ac36fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2971476587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2971476587
Directory	/workspace/45.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_interrupt.4292385641
Short name	T200
Test name
Test status
Simulation time	162851166884 ps
CPU time	64.17 seconds
Started	Feb 25 12:48:21 PM PST 24
Finished	Feb 25 12:49:25 PM PST 24
Peak memory	201492 kb
Host	smart-b7299ba9-c639-4112-8055-94d5a4293c91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292385641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.4292385641
Directory	/workspace/45.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1383938834
Short name	T438
Test name
Test status
Simulation time	162299341523 ps
CPU time	394.38 seconds
Started	Feb 25 12:48:30 PM PST 24
Finished	Feb 25 12:55:05 PM PST 24
Peak memory	201420 kb
Host	smart-c8f6375d-6713-440e-82fc-f38dbc494346
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383938834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru pt_fixed.1383938834
Directory	/workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_polled.4251593454
Short name	T680
Test name
Test status
Simulation time	329807186803 ps
CPU time	807.55 seconds
Started	Feb 25 12:48:18 PM PST 24
Finished	Feb 25 01:01:46 PM PST 24
Peak memory	201604 kb
Host	smart-ec380afa-dfa6-4267-a677-df2f91022e5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4251593454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.4251593454
Directory	/workspace/45.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1276250314
Short name	T609
Test name
Test status
Simulation time	162430137638 ps
CPU time	35.01 seconds
Started	Feb 25 12:48:19 PM PST 24
Finished	Feb 25 12:48:54 PM PST 24
Peak memory	201352 kb
Host	smart-3373bfe5-d4bc-4cdb-9709-c7603b6a5f74
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276250314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix ed.1276250314
Directory	/workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_wakeup.1432637194
Short name	T157
Test name
Test status
Simulation time	325457244253 ps
CPU time	772.08 seconds
Started	Feb 25 12:48:33 PM PST 24
Finished	Feb 25 01:01:25 PM PST 24
Peak memory	201472 kb
Host	smart-3f8e6826-0788-4cf4-8559-6bcf3935d91d
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432637194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters _wakeup.1432637194
Directory	/workspace/45.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.114441768
Short name	T508
Test name
Test status
Simulation time	159175324630 ps
CPU time	97.32 seconds
Started	Feb 25 12:48:29 PM PST 24
Finished	Feb 25 12:50:06 PM PST 24
Peak memory	201384 kb
Host	smart-a5ee6e78-ae3d-4bcc-b2ed-90f46ad703bf
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114441768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. adc_ctrl_filters_wakeup_fixed.114441768
Directory	/workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/45.adc_ctrl_fsm_reset.1747520772
Short name	T440
Test name
Test status
Simulation time	101326776281 ps
CPU time	255.2 seconds
Started	Feb 25 12:48:28 PM PST 24
Finished	Feb 25 12:52:44 PM PST 24
Peak memory	201824 kb
Host	smart-fe0574a9-a669-4910-a86d-3419d668faf7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1747520772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1747520772
Directory	/workspace/45.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/45.adc_ctrl_lowpower_counter.1823747845
Short name	T521
Test name
Test status
Simulation time	26921837782 ps
CPU time	61.14 seconds
Started	Feb 25 12:48:30 PM PST 24
Finished	Feb 25 12:49:32 PM PST 24
Peak memory	201212 kb
Host	smart-2ddd4ef2-f20c-4cd6-90bf-a3c2f23ad53a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1823747845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1823747845
Directory	/workspace/45.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/45.adc_ctrl_poweron_counter.1610415659
Short name	T491
Test name
Test status
Simulation time	3486202014 ps
CPU time	2.75 seconds
Started	Feb 25 12:48:30 PM PST 24
Finished	Feb 25 12:48:34 PM PST 24
Peak memory	201244 kb
Host	smart-344e30ce-df5f-489b-89c8-175845c5395a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1610415659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1610415659
Directory	/workspace/45.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/45.adc_ctrl_smoke.3948561406
Short name	T473
Test name
Test status
Simulation time	5957437803 ps
CPU time	3.82 seconds
Started	Feb 25 12:48:23 PM PST 24
Finished	Feb 25 12:48:27 PM PST 24
Peak memory	201224 kb
Host	smart-632f211d-6680-40a6-82ba-5e9f39cb9526
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3948561406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3948561406
Directory	/workspace/45.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.adc_ctrl_stress_all.1877887039
Short name	T294
Test name
Test status
Simulation time	336343453793 ps
CPU time	390.23 seconds
Started	Feb 25 12:48:30 PM PST 24
Finished	Feb 25 12:55:01 PM PST 24
Peak memory	201568 kb
Host	smart-7acdcaf7-7cbf-436d-8479-aa0aee03ce8b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877887039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all .1877887039
Directory	/workspace/45.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1941230701
Short name	T58
Test name
Test status
Simulation time	244670476111 ps
CPU time	43.43 seconds
Started	Feb 25 12:48:30 PM PST 24
Finished	Feb 25 12:49:14 PM PST 24
Peak memory	209740 kb
Host	smart-6c4b3f2e-b108-482e-ae53-3adf6e26410b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941230701 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1941230701
Directory	/workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.adc_ctrl_alert_test.2816390884
Short name	T642
Test name
Test status
Simulation time	432527046 ps
CPU time	1.54 seconds
Started	Feb 25 12:48:40 PM PST 24
Finished	Feb 25 12:48:42 PM PST 24
Peak memory	201220 kb
Host	smart-029bcfb8-c011-41ac-9058-dbbae06bfdd9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816390884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2816390884
Directory	/workspace/46.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_both.1632475102
Short name	T551
Test name
Test status
Simulation time	163251797592 ps
CPU time	89.88 seconds
Started	Feb 25 12:48:30 PM PST 24
Finished	Feb 25 12:50:00 PM PST 24
Peak memory	201588 kb
Host	smart-5b5a0d47-93a7-4e4b-8435-4d27accea92b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1632475102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1632475102
Directory	/workspace/46.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_interrupt.2073190719
Short name	T650
Test name
Test status
Simulation time	162410976828 ps
CPU time	295 seconds
Started	Feb 25 12:48:28 PM PST 24
Finished	Feb 25 12:53:24 PM PST 24
Peak memory	201516 kb
Host	smart-2d27947b-0791-479f-acef-8f29f9ed873b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2073190719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2073190719
Directory	/workspace/46.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3669554393
Short name	T68
Test name
Test status
Simulation time	161929203184 ps
CPU time	45.02 seconds
Started	Feb 25 12:48:27 PM PST 24
Finished	Feb 25 12:49:13 PM PST 24
Peak memory	201524 kb
Host	smart-1b105b88-d6b9-4613-931e-95bd10d58613
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669554393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru pt_fixed.3669554393
Directory	/workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_polled.3855711779
Short name	T723
Test name
Test status
Simulation time	162179306698 ps
CPU time	155.92 seconds
Started	Feb 25 12:48:29 PM PST 24
Finished	Feb 25 12:51:05 PM PST 24
Peak memory	201500 kb
Host	smart-6e1be0af-9f0e-4964-affe-2772d19819f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3855711779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3855711779
Directory	/workspace/46.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1153059845
Short name	T453
Test name
Test status
Simulation time	492627835318 ps
CPU time	578.24 seconds
Started	Feb 25 12:48:29 PM PST 24
Finished	Feb 25 12:58:07 PM PST 24
Peak memory	201468 kb
Host	smart-5b30c6f0-0ebf-4351-b62d-57f39e0fdfb8
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153059845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix ed.1153059845
Directory	/workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_wakeup.643768823
Short name	T348
Test name
Test status
Simulation time	503092727198 ps
CPU time	1163.67 seconds
Started	Feb 25 12:48:29 PM PST 24
Finished	Feb 25 01:07:53 PM PST 24
Peak memory	201464 kb
Host	smart-68ae4e17-579a-4a06-859f-9e4ec626a6c0
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643768823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_ wakeup.643768823
Directory	/workspace/46.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2234800771
Short name	T774
Test name
Test status
Simulation time	328843870728 ps
CPU time	194.75 seconds
Started	Feb 25 12:48:27 PM PST 24
Finished	Feb 25 12:51:42 PM PST 24
Peak memory	201572 kb
Host	smart-e45eceac-b007-4b6f-9b7d-e4e657236ea8
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234800771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46 .adc_ctrl_filters_wakeup_fixed.2234800771
Directory	/workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/46.adc_ctrl_fsm_reset.4110188163
Short name	T534
Test name
Test status
Simulation time	113074628885 ps
CPU time	603.32 seconds
Started	Feb 25 12:48:36 PM PST 24
Finished	Feb 25 12:58:40 PM PST 24
Peak memory	201848 kb
Host	smart-3d660cb0-b939-4ed5-8888-fb26f387a676
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4110188163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.4110188163
Directory	/workspace/46.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/46.adc_ctrl_lowpower_counter.4117711167
Short name	T587
Test name
Test status
Simulation time	43637737447 ps
CPU time	105.5 seconds
Started	Feb 25 12:48:35 PM PST 24
Finished	Feb 25 12:50:21 PM PST 24
Peak memory	201172 kb
Host	smart-dff856cf-b3d4-4523-8394-8efa672c0fa8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4117711167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.4117711167
Directory	/workspace/46.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/46.adc_ctrl_poweron_counter.45218345
Short name	T593
Test name
Test status
Simulation time	3709916700 ps
CPU time	9.36 seconds
Started	Feb 25 12:48:27 PM PST 24
Finished	Feb 25 12:48:37 PM PST 24
Peak memory	201204 kb
Host	smart-1650aa33-1a07-490e-a395-a130de4f2b6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=45218345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.45218345
Directory	/workspace/46.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/46.adc_ctrl_smoke.61528232
Short name	T675
Test name
Test status
Simulation time	5668557065 ps
CPU time	3.72 seconds
Started	Feb 25 12:48:33 PM PST 24
Finished	Feb 25 12:48:36 PM PST 24
Peak memory	201276 kb
Host	smart-366178b1-41f7-4661-bce8-e75d3637da61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61528232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.61528232
Directory	/workspace/46.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.adc_ctrl_stress_all.1150278826
Short name	T8
Test name
Test status
Simulation time	103848267104 ps
CPU time	294.64 seconds
Started	Feb 25 12:48:36 PM PST 24
Finished	Feb 25 12:53:31 PM PST 24
Peak memory	210004 kb
Host	smart-fb29cf15-1872-4537-8e09-8dc8bb9355a3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150278826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all .1150278826
Directory	/workspace/46.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1362110132
Short name	T210
Test name
Test status
Simulation time	506795975389 ps
CPU time	465.25 seconds
Started	Feb 25 12:48:36 PM PST 24
Finished	Feb 25 12:56:22 PM PST 24
Peak memory	210168 kb
Host	smart-7f708ad7-dbc9-4cd3-8218-a0981ff53a20
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362110132 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1362110132
Directory	/workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.adc_ctrl_alert_test.1413963830
Short name	T405
Test name
Test status
Simulation time	505171227 ps
CPU time	1.45 seconds
Started	Feb 25 12:48:44 PM PST 24
Finished	Feb 25 12:48:46 PM PST 24
Peak memory	201156 kb
Host	smart-8f1ef224-1ebb-402f-83d8-7ff47f53b70b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413963830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1413963830
Directory	/workspace/47.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_both.241120534
Short name	T335
Test name
Test status
Simulation time	168403004223 ps
CPU time	413.22 seconds
Started	Feb 25 12:48:44 PM PST 24
Finished	Feb 25 12:55:37 PM PST 24
Peak memory	201512 kb
Host	smart-15c4a0dc-e50b-4402-906c-13ee393f5bc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=241120534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.241120534
Directory	/workspace/47.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_interrupt.2143691521
Short name	T287
Test name
Test status
Simulation time	325562666039 ps
CPU time	173.03 seconds
Started	Feb 25 12:48:40 PM PST 24
Finished	Feb 25 12:51:33 PM PST 24
Peak memory	201540 kb
Host	smart-31669da4-9a5d-456d-8f3e-858db349c002
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2143691521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2143691521
Directory	/workspace/47.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.852603874
Short name	T187
Test name
Test status
Simulation time	165366232921 ps
CPU time	93.46 seconds
Started	Feb 25 12:48:35 PM PST 24
Finished	Feb 25 12:50:09 PM PST 24
Peak memory	201460 kb
Host	smart-d499bfb0-d1a6-46c9-8ecc-976be0e5fb1d
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=852603874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup t_fixed.852603874
Directory	/workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_polled.2949628570
Short name	T447
Test name
Test status
Simulation time	161330139432 ps
CPU time	378.79 seconds
Started	Feb 25 12:48:37 PM PST 24
Finished	Feb 25 12:54:56 PM PST 24
Peak memory	201492 kb
Host	smart-31ff53ce-c4ac-4deb-8f7a-0b65fcafd7f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2949628570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2949628570
Directory	/workspace/47.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.4139594727
Short name	T527
Test name
Test status
Simulation time	163129350452 ps
CPU time	408.81 seconds
Started	Feb 25 12:48:37 PM PST 24
Finished	Feb 25 12:55:26 PM PST 24
Peak memory	201404 kb
Host	smart-98c5cf45-a9dc-4860-a81a-de39e07551a7
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139594727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix ed.4139594727
Directory	/workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_wakeup.1854278696
Short name	T149
Test name
Test status
Simulation time	165598560683 ps
CPU time	210.94 seconds
Started	Feb 25 12:48:45 PM PST 24
Finished	Feb 25 12:52:16 PM PST 24
Peak memory	201556 kb
Host	smart-0cfc0490-0bdc-4118-abba-dd85814cecab
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854278696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters _wakeup.1854278696
Directory	/workspace/47.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.278732450
Short name	T69
Test name
Test status
Simulation time	326155560826 ps
CPU time	174.3 seconds
Started	Feb 25 12:48:45 PM PST 24
Finished	Feb 25 12:51:39 PM PST 24
Peak memory	201464 kb
Host	smart-3d224e75-6d8c-4539-8ee9-7cea4acede5e
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278732450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. adc_ctrl_filters_wakeup_fixed.278732450
Directory	/workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/47.adc_ctrl_fsm_reset.4153111501
Short name	T571
Test name
Test status
Simulation time	123655140482 ps
CPU time	399.29 seconds
Started	Feb 25 12:48:44 PM PST 24
Finished	Feb 25 12:55:23 PM PST 24
Peak memory	201880 kb
Host	smart-c23f2b2c-515a-4850-b272-081e183b0eab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4153111501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.4153111501
Directory	/workspace/47.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/47.adc_ctrl_lowpower_counter.752295596
Short name	T542
Test name
Test status
Simulation time	39625518913 ps
CPU time	82.07 seconds
Started	Feb 25 12:48:43 PM PST 24
Finished	Feb 25 12:50:05 PM PST 24
Peak memory	201176 kb
Host	smart-2aeccaaf-5f54-44d7-b520-a61a8760ab05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=752295596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.752295596
Directory	/workspace/47.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/47.adc_ctrl_poweron_counter.3667947142
Short name	T584
Test name
Test status
Simulation time	3423416929 ps
CPU time	2.33 seconds
Started	Feb 25 12:48:43 PM PST 24
Finished	Feb 25 12:48:46 PM PST 24
Peak memory	201232 kb
Host	smart-37d6a75f-8003-49f0-845d-64db492723c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3667947142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3667947142
Directory	/workspace/47.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/47.adc_ctrl_smoke.3521568344
Short name	T742
Test name
Test status
Simulation time	5808159902 ps
CPU time	1.72 seconds
Started	Feb 25 12:48:35 PM PST 24
Finished	Feb 25 12:48:37 PM PST 24
Peak memory	201284 kb
Host	smart-d40769fe-9a17-4057-bfd2-e80f6219214f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521568344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3521568344
Directory	/workspace/47.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.adc_ctrl_stress_all.922065212
Short name	T47
Test name
Test status
Simulation time	97453353777 ps
CPU time	239.18 seconds
Started	Feb 25 12:48:43 PM PST 24
Finished	Feb 25 12:52:43 PM PST 24
Peak memory	209992 kb
Host	smart-bedd1433-b610-450e-9d60-1b8848fbd028
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922065212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all. 922065212
Directory	/workspace/47.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1720310433
Short name	T50
Test name
Test status
Simulation time	56141124104 ps
CPU time	114.61 seconds
Started	Feb 25 12:48:46 PM PST 24
Finished	Feb 25 12:50:41 PM PST 24
Peak memory	201992 kb
Host	smart-06a6c622-2425-4a9a-bc0b-48fa6ff12af6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720310433 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1720310433
Directory	/workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.adc_ctrl_alert_test.2946016315
Short name	T728
Test name
Test status
Simulation time	528363424 ps
CPU time	1.68 seconds
Started	Feb 25 12:48:51 PM PST 24
Finished	Feb 25 12:48:53 PM PST 24
Peak memory	201132 kb
Host	smart-6c27a154-2f05-457d-b12a-481250d4e47c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946016315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2946016315
Directory	/workspace/48.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_both.1618401171
Short name	T252
Test name
Test status
Simulation time	158308620385 ps
CPU time	363.69 seconds
Started	Feb 25 12:48:54 PM PST 24
Finished	Feb 25 12:54:57 PM PST 24
Peak memory	201484 kb
Host	smart-3c93eb8f-88f5-4c2a-90c7-e755ce1d8ed8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1618401171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1618401171
Directory	/workspace/48.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_interrupt.2995274088
Short name	T559
Test name
Test status
Simulation time	160442704775 ps
CPU time	34.38 seconds
Started	Feb 25 12:48:46 PM PST 24
Finished	Feb 25 12:49:20 PM PST 24
Peak memory	201568 kb
Host	smart-0aebe498-10a7-486c-8357-da9d0c0411f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2995274088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2995274088
Directory	/workspace/48.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1845701500
Short name	T140
Test name
Test status
Simulation time	339363639477 ps
CPU time	86.26 seconds
Started	Feb 25 12:48:44 PM PST 24
Finished	Feb 25 12:50:10 PM PST 24
Peak memory	201396 kb
Host	smart-9eefaaee-cad4-42b4-b68b-36077e8f07b8
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845701500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru pt_fixed.1845701500
Directory	/workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_polled.1692235714
Short name	T717
Test name
Test status
Simulation time	164259811653 ps
CPU time	397.3 seconds
Started	Feb 25 12:48:46 PM PST 24
Finished	Feb 25 12:55:23 PM PST 24
Peak memory	201548 kb
Host	smart-33418c10-7202-462f-8583-364cddb9a1f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1692235714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1692235714
Directory	/workspace/48.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2867767281
Short name	T622
Test name
Test status
Simulation time	330214093016 ps
CPU time	178.24 seconds
Started	Feb 25 12:48:43 PM PST 24
Finished	Feb 25 12:51:42 PM PST 24
Peak memory	201464 kb
Host	smart-09e770d1-c861-463d-b771-d9cd8a4d50bc
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867767281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix ed.2867767281
Directory	/workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_wakeup.1877730265
Short name	T266
Test name
Test status
Simulation time	338856624536 ps
CPU time	589.27 seconds
Started	Feb 25 12:48:52 PM PST 24
Finished	Feb 25 12:58:41 PM PST 24
Peak memory	201484 kb
Host	smart-fe72e52d-0875-4601-82fb-9044cbe46ee8
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877730265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters _wakeup.1877730265
Directory	/workspace/48.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1591523219
Short name	T493
Test name
Test status
Simulation time	330794432564 ps
CPU time	735.71 seconds
Started	Feb 25 12:48:53 PM PST 24
Finished	Feb 25 01:01:09 PM PST 24
Peak memory	201484 kb
Host	smart-e0033d6a-6d59-4ec9-9710-34a43a1fc7f4
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591523219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48 .adc_ctrl_filters_wakeup_fixed.1591523219
Directory	/workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/48.adc_ctrl_fsm_reset.2733487872
Short name	T216
Test name
Test status
Simulation time	84314501557 ps
CPU time	450.59 seconds
Started	Feb 25 12:48:53 PM PST 24
Finished	Feb 25 12:56:23 PM PST 24
Peak memory	201716 kb
Host	smart-e6420e08-d1bb-42b5-bff4-0bd6c8bc917f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2733487872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2733487872
Directory	/workspace/48.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/48.adc_ctrl_lowpower_counter.3501395232
Short name	T429
Test name
Test status
Simulation time	28031740930 ps
CPU time	9.12 seconds
Started	Feb 25 12:48:55 PM PST 24
Finished	Feb 25 12:49:04 PM PST 24
Peak memory	201268 kb
Host	smart-0924bc1a-6eb1-4eb3-817d-6b76c92984e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3501395232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3501395232
Directory	/workspace/48.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/48.adc_ctrl_poweron_counter.3270597431
Short name	T553
Test name
Test status
Simulation time	3302270372 ps
CPU time	7.82 seconds
Started	Feb 25 12:48:51 PM PST 24
Finished	Feb 25 12:48:59 PM PST 24
Peak memory	201224 kb
Host	smart-78e89fb2-943e-4bf1-95a8-2b319b125bb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3270597431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3270597431
Directory	/workspace/48.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/48.adc_ctrl_smoke.1726118414
Short name	T372
Test name
Test status
Simulation time	5908997928 ps
CPU time	14.15 seconds
Started	Feb 25 12:48:45 PM PST 24
Finished	Feb 25 12:49:00 PM PST 24
Peak memory	201228 kb
Host	smart-43286f14-0282-4615-9fa2-e8bfc9503bc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1726118414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1726118414
Directory	/workspace/48.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.adc_ctrl_stress_all.405742671
Short name	T366
Test name
Test status
Simulation time	33165262717 ps
CPU time	75.86 seconds
Started	Feb 25 12:48:51 PM PST 24
Finished	Feb 25 12:50:07 PM PST 24
Peak memory	201244 kb
Host	smart-298c8086-7e32-4ff5-aaf6-508eff5a34f5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405742671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all. 405742671
Directory	/workspace/48.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.adc_ctrl_alert_test.2428827455
Short name	T499
Test name
Test status
Simulation time	294436712 ps
CPU time	1.22 seconds
Started	Feb 25 12:49:01 PM PST 24
Finished	Feb 25 12:49:02 PM PST 24
Peak memory	201216 kb
Host	smart-6ced5fbf-c542-4fa0-aa77-94be8a46021a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428827455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2428827455
Directory	/workspace/49.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_both.876006394
Short name	T284
Test name
Test status
Simulation time	163033649294 ps
CPU time	69.03 seconds
Started	Feb 25 12:49:02 PM PST 24
Finished	Feb 25 12:50:11 PM PST 24
Peak memory	201568 kb
Host	smart-4cd9446a-6001-43ad-8734-e7c1553ecae6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=876006394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.876006394
Directory	/workspace/49.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2087805942
Short name	T555
Test name
Test status
Simulation time	169116817731 ps
CPU time	73.13 seconds
Started	Feb 25 12:49:02 PM PST 24
Finished	Feb 25 12:50:16 PM PST 24
Peak memory	201440 kb
Host	smart-bb7ca37c-a314-49b6-abf5-5c15855dcfed
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087805942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru pt_fixed.2087805942
Directory	/workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_polled.2335628167
Short name	T64
Test name
Test status
Simulation time	490578790233 ps
CPU time	1179.08 seconds
Started	Feb 25 12:48:51 PM PST 24
Finished	Feb 25 01:08:30 PM PST 24
Peak memory	201412 kb
Host	smart-8d646495-2289-4fb3-a928-0cf2d44b1c7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2335628167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2335628167
Directory	/workspace/49.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2125688729
Short name	T486
Test name
Test status
Simulation time	333406762409 ps
CPU time	93.86 seconds
Started	Feb 25 12:48:53 PM PST 24
Finished	Feb 25 12:50:27 PM PST 24
Peak memory	201464 kb
Host	smart-05db5d4b-05b0-4e51-8192-d176cc938eb2
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125688729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix ed.2125688729
Directory	/workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_wakeup.3258259040
Short name	T315
Test name
Test status
Simulation time	392682756711 ps
CPU time	363.3 seconds
Started	Feb 25 12:49:01 PM PST 24
Finished	Feb 25 12:55:05 PM PST 24
Peak memory	201472 kb
Host	smart-cae3a82c-0d69-448c-b9fc-75cc390dbdb3
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258259040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters _wakeup.3258259040
Directory	/workspace/49.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.997329204
Short name	T663
Test name
Test status
Simulation time	330781942065 ps
CPU time	205.42 seconds
Started	Feb 25 12:49:02 PM PST 24
Finished	Feb 25 12:52:27 PM PST 24
Peak memory	201468 kb
Host	smart-97526b76-e977-448e-9c83-796092c4b138
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997329204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. adc_ctrl_filters_wakeup_fixed.997329204
Directory	/workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/49.adc_ctrl_fsm_reset.2257353584
Short name	T407
Test name
Test status
Simulation time	77704363956 ps
CPU time	274.51 seconds
Started	Feb 25 12:49:00 PM PST 24
Finished	Feb 25 12:53:35 PM PST 24
Peak memory	201860 kb
Host	smart-3406bd34-2eab-40f0-a8d6-288d6f04c3f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257353584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2257353584
Directory	/workspace/49.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/49.adc_ctrl_lowpower_counter.803022765
Short name	T389
Test name
Test status
Simulation time	42228570554 ps
CPU time	47.95 seconds
Started	Feb 25 12:49:03 PM PST 24
Finished	Feb 25 12:49:51 PM PST 24
Peak memory	201216 kb
Host	smart-65f590fd-2ad8-457d-9f1d-0d1f87f8f0a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=803022765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.803022765
Directory	/workspace/49.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/49.adc_ctrl_poweron_counter.2307654801
Short name	T504
Test name
Test status
Simulation time	5417770371 ps
CPU time	3.09 seconds
Started	Feb 25 12:49:01 PM PST 24
Finished	Feb 25 12:49:05 PM PST 24
Peak memory	201272 kb
Host	smart-f344898b-a317-4f5f-a325-fb931f82dc58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2307654801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2307654801
Directory	/workspace/49.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/49.adc_ctrl_smoke.4056566654
Short name	T81
Test name
Test status
Simulation time	5929841135 ps
CPU time	4.29 seconds
Started	Feb 25 12:48:50 PM PST 24
Finished	Feb 25 12:48:54 PM PST 24
Peak memory	201192 kb
Host	smart-43c7a794-274c-448a-a3ce-e754f63c35b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4056566654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.4056566654
Directory	/workspace/49.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.adc_ctrl_stress_all.2227295456
Short name	T328
Test name
Test status
Simulation time	332541142432 ps
CPU time	707.77 seconds
Started	Feb 25 12:49:03 PM PST 24
Finished	Feb 25 01:00:51 PM PST 24
Peak memory	201540 kb
Host	smart-f6719e5e-802f-4bf7-a53c-036a66c1d3aa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227295456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all .2227295456
Directory	/workspace/49.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2939154940
Short name	T638
Test name
Test status
Simulation time	84422392614 ps
CPU time	108.91 seconds
Started	Feb 25 12:49:01 PM PST 24
Finished	Feb 25 12:50:50 PM PST 24
Peak memory	209764 kb
Host	smart-0fcdece4-d9c0-4a55-a53b-9a92adbef58c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939154940 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2939154940
Directory	/workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.adc_ctrl_alert_test.2898566240
Short name	T557
Test name
Test status
Simulation time	591783645 ps
CPU time	0.72 seconds
Started	Feb 25 12:44:50 PM PST 24
Finished	Feb 25 12:44:51 PM PST 24
Peak memory	201164 kb
Host	smart-38b0f76c-7611-4f04-bb1b-6de742d478e3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898566240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2898566240
Directory	/workspace/5.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_both.3362909441
Short name	T346
Test name
Test status
Simulation time	494857058963 ps
CPU time	1071.52 seconds
Started	Feb 25 12:44:51 PM PST 24
Finished	Feb 25 01:02:42 PM PST 24
Peak memory	201476 kb
Host	smart-04766c11-98df-4bc8-862f-218e6a4f175a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3362909441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3362909441
Directory	/workspace/5.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_interrupt.1437307227
Short name	T281
Test name
Test status
Simulation time	328889975942 ps
CPU time	222.4 seconds
Started	Feb 25 12:44:49 PM PST 24
Finished	Feb 25 12:48:32 PM PST 24
Peak memory	201416 kb
Host	smart-adef357a-aec5-4704-ab86-af104d52011e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1437307227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1437307227
Directory	/workspace/5.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1486247664
Short name	T770
Test name
Test status
Simulation time	492316452229 ps
CPU time	322.98 seconds
Started	Feb 25 12:44:54 PM PST 24
Finished	Feb 25 12:50:17 PM PST 24
Peak memory	201456 kb
Host	smart-00c4ea44-e00d-4502-b2a9-0b493dc13946
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486247664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup t_fixed.1486247664
Directory	/workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_polled.605694458
Short name	T5
Test name
Test status
Simulation time	164409992148 ps
CPU time	341.35 seconds
Started	Feb 25 12:44:54 PM PST 24
Finished	Feb 25 12:50:36 PM PST 24
Peak memory	201496 kb
Host	smart-3f41669f-7631-46fa-b1fd-fa7498b0442c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=605694458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.605694458
Directory	/workspace/5.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.4263234214
Short name	T518
Test name
Test status
Simulation time	161875279100 ps
CPU time	180.5 seconds
Started	Feb 25 12:44:51 PM PST 24
Finished	Feb 25 12:47:52 PM PST 24
Peak memory	201524 kb
Host	smart-9785657c-8db9-4bae-9fd8-f6d1069f7604
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263234214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe d.4263234214
Directory	/workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_wakeup.2100381658
Short name	T474
Test name
Test status
Simulation time	339197882453 ps
CPU time	766.21 seconds
Started	Feb 25 12:44:51 PM PST 24
Finished	Feb 25 12:57:38 PM PST 24
Peak memory	201532 kb
Host	smart-82cbdf38-70f5-47fa-a2f0-a1d0b98b4d92
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100381658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_ wakeup.2100381658
Directory	/workspace/5.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2648273224
Short name	T468
Test name
Test status
Simulation time	479667467058 ps
CPU time	560.11 seconds
Started	Feb 25 12:44:48 PM PST 24
Finished	Feb 25 12:54:09 PM PST 24
Peak memory	201392 kb
Host	smart-5f5d737c-b6ec-4844-a475-dc51140b43d2
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648273224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5. adc_ctrl_filters_wakeup_fixed.2648273224
Directory	/workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/5.adc_ctrl_fsm_reset.2972458747
Short name	T170
Test name
Test status
Simulation time	54604963867 ps
CPU time	201.21 seconds
Started	Feb 25 12:44:54 PM PST 24
Finished	Feb 25 12:48:16 PM PST 24
Peak memory	201816 kb
Host	smart-847c9a37-e487-46d4-9a12-accb4b75e623
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2972458747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2972458747
Directory	/workspace/5.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/5.adc_ctrl_lowpower_counter.1506890192
Short name	T388
Test name
Test status
Simulation time	42538063969 ps
CPU time	98.35 seconds
Started	Feb 25 12:44:49 PM PST 24
Finished	Feb 25 12:46:28 PM PST 24
Peak memory	201284 kb
Host	smart-c8d621ed-817f-4412-941a-60afa9d01517
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1506890192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1506890192
Directory	/workspace/5.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/5.adc_ctrl_poweron_counter.3966023019
Short name	T495
Test name
Test status
Simulation time	3095648828 ps
CPU time	4.62 seconds
Started	Feb 25 12:44:50 PM PST 24
Finished	Feb 25 12:44:55 PM PST 24
Peak memory	201224 kb
Host	smart-67b70572-6023-45e3-9a6c-6a810734a0a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3966023019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3966023019
Directory	/workspace/5.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/5.adc_ctrl_smoke.3569761107
Short name	T168
Test name
Test status
Simulation time	5987208136 ps
CPU time	5.24 seconds
Started	Feb 25 12:44:50 PM PST 24
Finished	Feb 25 12:44:56 PM PST 24
Peak memory	201156 kb
Host	smart-1012f053-8fc9-4181-b764-90e62b2c4d8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3569761107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3569761107
Directory	/workspace/5.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.adc_ctrl_stress_all.3293379112
Short name	T779
Test name
Test status
Simulation time	316009909385 ps
CPU time	1120.05 seconds
Started	Feb 25 12:44:50 PM PST 24
Finished	Feb 25 01:03:30 PM PST 24
Peak memory	209916 kb
Host	smart-a9dade75-6ad2-4cf5-b6b5-da20a726723d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293379112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all. 3293379112
Directory	/workspace/5.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1642285691
Short name	T353
Test name
Test status
Simulation time	345321280564 ps
CPU time	327.57 seconds
Started	Feb 25 12:44:53 PM PST 24
Finished	Feb 25 12:50:21 PM PST 24
Peak memory	210028 kb
Host	smart-e8534406-84be-4c39-a209-9c5ac153b972
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642285691 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1642285691
Directory	/workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.adc_ctrl_alert_test.4292772482
Short name	T432
Test name
Test status
Simulation time	534476712 ps
CPU time	0.7 seconds
Started	Feb 25 12:44:55 PM PST 24
Finished	Feb 25 12:44:56 PM PST 24
Peak memory	201156 kb
Host	smart-17adbafa-404b-4e07-b288-67e2b1ce850b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292772482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.4292772482
Directory	/workspace/6.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.adc_ctrl_clock_gating.2141138817
Short name	T171
Test name
Test status
Simulation time	162097996701 ps
CPU time	27.58 seconds
Started	Feb 25 12:44:53 PM PST 24
Finished	Feb 25 12:45:21 PM PST 24
Peak memory	201388 kb
Host	smart-31fca173-07fe-4836-a059-16f940eaed82
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141138817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati ng.2141138817
Directory	/workspace/6.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_both.1842848291
Short name	T349
Test name
Test status
Simulation time	164487327620 ps
CPU time	96.94 seconds
Started	Feb 25 12:44:51 PM PST 24
Finished	Feb 25 12:46:28 PM PST 24
Peak memory	201468 kb
Host	smart-5e69ed08-f14d-4fd6-9b26-54cc38b3484c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1842848291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1842848291
Directory	/workspace/6.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2975041904
Short name	T415
Test name
Test status
Simulation time	494865500771 ps
CPU time	1038.47 seconds
Started	Feb 25 12:44:53 PM PST 24
Finished	Feb 25 01:02:11 PM PST 24
Peak memory	201356 kb
Host	smart-d9e45e5a-8a0b-4cbc-bfdd-75deb5394e40
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975041904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup t_fixed.2975041904
Directory	/workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_polled.3978969124
Short name	T48
Test name
Test status
Simulation time	323924870334 ps
CPU time	771.74 seconds
Started	Feb 25 12:44:53 PM PST 24
Finished	Feb 25 12:57:44 PM PST 24
Peak memory	201448 kb
Host	smart-00272903-1f85-464b-ba03-1095e52ff847
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3978969124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3978969124
Directory	/workspace/6.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2372322371
Short name	T684
Test name
Test status
Simulation time	333193030654 ps
CPU time	383.78 seconds
Started	Feb 25 12:44:49 PM PST 24
Finished	Feb 25 12:51:13 PM PST 24
Peak memory	201524 kb
Host	smart-2b3efbf1-c058-4c13-b073-6e1eb3717078
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372322371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe d.2372322371
Directory	/workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1921315610
Short name	T457
Test name
Test status
Simulation time	164711537649 ps
CPU time	91.07 seconds
Started	Feb 25 12:44:50 PM PST 24
Finished	Feb 25 12:46:21 PM PST 24
Peak memory	201468 kb
Host	smart-db5149af-6f1b-4d0d-b29c-975ce1fef111
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921315610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6. adc_ctrl_filters_wakeup_fixed.1921315610
Directory	/workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/6.adc_ctrl_fsm_reset.633181293
Short name	T229
Test name
Test status
Simulation time	134475118019 ps
CPU time	449.83 seconds
Started	Feb 25 12:44:56 PM PST 24
Finished	Feb 25 12:52:26 PM PST 24
Peak memory	201784 kb
Host	smart-a0f66c3b-3a25-4795-bdd5-cd0bbbb29d77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=633181293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.633181293
Directory	/workspace/6.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/6.adc_ctrl_lowpower_counter.4166254338
Short name	T386
Test name
Test status
Simulation time	45760529957 ps
CPU time	102.31 seconds
Started	Feb 25 12:44:54 PM PST 24
Finished	Feb 25 12:46:36 PM PST 24
Peak memory	201272 kb
Host	smart-ac8cb113-0bcb-4c2f-8158-1f7747dbd761
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4166254338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.4166254338
Directory	/workspace/6.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/6.adc_ctrl_poweron_counter.345049804
Short name	T566
Test name
Test status
Simulation time	4579659018 ps
CPU time	10.53 seconds
Started	Feb 25 12:44:54 PM PST 24
Finished	Feb 25 12:45:05 PM PST 24
Peak memory	201272 kb
Host	smart-e3a868ea-0986-4a2b-9d3f-007672194800
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=345049804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.345049804
Directory	/workspace/6.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/6.adc_ctrl_smoke.2335038084
Short name	T374
Test name
Test status
Simulation time	5871622484 ps
CPU time	5.19 seconds
Started	Feb 25 12:44:54 PM PST 24
Finished	Feb 25 12:44:59 PM PST 24
Peak memory	201208 kb
Host	smart-501d536c-c658-4075-83c0-98bb9a41132a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2335038084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2335038084
Directory	/workspace/6.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.adc_ctrl_stress_all.4048978890
Short name	T695
Test name
Test status
Simulation time	334907302775 ps
CPU time	203.69 seconds
Started	Feb 25 12:44:55 PM PST 24
Finished	Feb 25 12:48:19 PM PST 24
Peak memory	201472 kb
Host	smart-53ff7968-e684-4976-823b-4ced2a8b0e2a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048978890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all. 4048978890
Directory	/workspace/6.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/7.adc_ctrl_alert_test.3955921612
Short name	T506
Test name
Test status
Simulation time	344335679 ps
CPU time	1.42 seconds
Started	Feb 25 12:44:59 PM PST 24
Finished	Feb 25 12:45:01 PM PST 24
Peak memory	201220 kb
Host	smart-e444e90c-3de2-45ff-a1a1-43209c943849
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955921612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3955921612
Directory	/workspace/7.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.adc_ctrl_clock_gating.3100735368
Short name	T632
Test name
Test status
Simulation time	166395407911 ps
CPU time	23.41 seconds
Started	Feb 25 12:45:15 PM PST 24
Finished	Feb 25 12:45:38 PM PST 24
Peak memory	201428 kb
Host	smart-0e1207d9-debc-41fc-81dc-8aa04a6858b1
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100735368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati ng.3100735368
Directory	/workspace/7.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_interrupt.3257659346
Short name	T131
Test name
Test status
Simulation time	165204629459 ps
CPU time	124.32 seconds
Started	Feb 25 12:45:07 PM PST 24
Finished	Feb 25 12:47:11 PM PST 24
Peak memory	201472 kb
Host	smart-f3dab7c7-912c-45ee-a40b-6d9bfd3505d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3257659346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3257659346
Directory	/workspace/7.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3359926585
Short name	T574
Test name
Test status
Simulation time	163172736136 ps
CPU time	366 seconds
Started	Feb 25 12:45:08 PM PST 24
Finished	Feb 25 12:51:15 PM PST 24
Peak memory	201528 kb
Host	smart-380059db-8f01-4806-a6e5-f6a4e31d3650
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359926585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup t_fixed.3359926585
Directory	/workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_polled.3388304126
Short name	T734
Test name
Test status
Simulation time	166531117914 ps
CPU time	355 seconds
Started	Feb 25 12:45:00 PM PST 24
Finished	Feb 25 12:50:55 PM PST 24
Peak memory	201444 kb
Host	smart-2623eb87-d727-4aed-bbb5-7747ec0fd1a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3388304126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3388304126
Directory	/workspace/7.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1627917072
Short name	T482
Test name
Test status
Simulation time	482107235082 ps
CPU time	224.29 seconds
Started	Feb 25 12:45:08 PM PST 24
Finished	Feb 25 12:48:52 PM PST 24
Peak memory	201464 kb
Host	smart-a635176f-9950-44b8-a39d-f617ef8d63a7
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627917072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe d.1627917072
Directory	/workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.55080775
Short name	T121
Test name
Test status
Simulation time	323139212373 ps
CPU time	119.44 seconds
Started	Feb 25 12:45:02 PM PST 24
Finished	Feb 25 12:47:02 PM PST 24
Peak memory	201512 kb
Host	smart-0cf5d9b1-bfec-4bc9-b290-c539a344438c
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55080775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ= adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.ad c_ctrl_filters_wakeup_fixed.55080775
Directory	/workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/7.adc_ctrl_fsm_reset.1265616450
Short name	T582
Test name
Test status
Simulation time	132441178638 ps
CPU time	670.35 seconds
Started	Feb 25 12:44:57 PM PST 24
Finished	Feb 25 12:56:08 PM PST 24
Peak memory	201760 kb
Host	smart-036ced8d-e2fa-4dfe-9150-ec922b7d4094
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1265616450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1265616450
Directory	/workspace/7.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/7.adc_ctrl_lowpower_counter.3703655349
Short name	T450
Test name
Test status
Simulation time	21813377955 ps
CPU time	24.91 seconds
Started	Feb 25 12:45:02 PM PST 24
Finished	Feb 25 12:45:27 PM PST 24
Peak memory	201284 kb
Host	smart-9273c507-57e2-44f4-a08f-8bc850b70a69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3703655349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3703655349
Directory	/workspace/7.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/7.adc_ctrl_poweron_counter.393661618
Short name	T771
Test name
Test status
Simulation time	5136955650 ps
CPU time	2.5 seconds
Started	Feb 25 12:44:59 PM PST 24
Finished	Feb 25 12:45:02 PM PST 24
Peak memory	201272 kb
Host	smart-54aea045-2607-45c6-b541-06f4ac713a31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=393661618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.393661618
Directory	/workspace/7.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/7.adc_ctrl_smoke.3012755820
Short name	T589
Test name
Test status
Simulation time	6033470218 ps
CPU time	4.07 seconds
Started	Feb 25 12:44:58 PM PST 24
Finished	Feb 25 12:45:02 PM PST 24
Peak memory	201200 kb
Host	smart-3e5f907d-358a-43dc-a699-6a2a1f07bc55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3012755820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3012755820
Directory	/workspace/7.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1122909080
Short name	T57
Test name
Test status
Simulation time	340288772454 ps
CPU time	409.25 seconds
Started	Feb 25 12:45:00 PM PST 24
Finished	Feb 25 12:51:49 PM PST 24
Peak memory	210056 kb
Host	smart-2f810a0a-1a60-43f1-b996-6e7d5be9fcae
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122909080 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1122909080
Directory	/workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.adc_ctrl_alert_test.1437745810
Short name	T647
Test name
Test status
Simulation time	465196995 ps
CPU time	1.56 seconds
Started	Feb 25 12:45:01 PM PST 24
Finished	Feb 25 12:45:03 PM PST 24
Peak memory	201212 kb
Host	smart-8e3c0df0-13ca-43ae-a161-86df4b5c09cb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437745810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1437745810
Directory	/workspace/8.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_interrupt.157359770
Short name	T263
Test name
Test status
Simulation time	324621079268 ps
CPU time	796.41 seconds
Started	Feb 25 12:45:00 PM PST 24
Finished	Feb 25 12:58:17 PM PST 24
Peak memory	201476 kb
Host	smart-0d3c172f-3ad7-4f86-8df5-445611785eb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=157359770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.157359770
Directory	/workspace/8.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3399387295
Short name	T132
Test name
Test status
Simulation time	331199850198 ps
CPU time	753.95 seconds
Started	Feb 25 12:45:07 PM PST 24
Finished	Feb 25 12:57:42 PM PST 24
Peak memory	200612 kb
Host	smart-feb1c25f-26e3-43b6-8799-6e22f8e6802f
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399387295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup t_fixed.3399387295
Directory	/workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_polled.2040736769
Short name	T129
Test name
Test status
Simulation time	159566066929 ps
CPU time	88.16 seconds
Started	Feb 25 12:44:57 PM PST 24
Finished	Feb 25 12:46:25 PM PST 24
Peak memory	201564 kb
Host	smart-c9aa0ce4-dc22-4a9e-9ecb-3cf583601d41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2040736769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2040736769
Directory	/workspace/8.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1938645230
Short name	T423
Test name
Test status
Simulation time	488288735635 ps
CPU time	575.53 seconds
Started	Feb 25 12:45:02 PM PST 24
Finished	Feb 25 12:54:38 PM PST 24
Peak memory	201500 kb
Host	smart-4b0f2da5-bef2-4eba-8479-f21ec306a04d
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938645230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe d.1938645230
Directory	/workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_wakeup.1628399070
Short name	T182
Test name
Test status
Simulation time	325451255209 ps
CPU time	232.8 seconds
Started	Feb 25 12:45:07 PM PST 24
Finished	Feb 25 12:49:00 PM PST 24
Peak memory	201468 kb
Host	smart-646aacaf-3904-420b-b66c-91053462954c
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628399070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_ wakeup.1628399070
Directory	/workspace/8.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.843828034
Short name	T727
Test name
Test status
Simulation time	497628882022 ps
CPU time	310.46 seconds
Started	Feb 25 12:45:00 PM PST 24
Finished	Feb 25 12:50:11 PM PST 24
Peak memory	201412 kb
Host	smart-79d07ddf-1848-4f85-9309-b177d905b422
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843828034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a dc_ctrl_filters_wakeup_fixed.843828034
Directory	/workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/8.adc_ctrl_lowpower_counter.2008774124
Short name	T690
Test name
Test status
Simulation time	41032262976 ps
CPU time	91.14 seconds
Started	Feb 25 12:45:07 PM PST 24
Finished	Feb 25 12:46:38 PM PST 24
Peak memory	201288 kb
Host	smart-d9d233a1-1e5d-4204-87a7-256ac5f23add
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2008774124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2008774124
Directory	/workspace/8.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/8.adc_ctrl_poweron_counter.3952131517
Short name	T137
Test name
Test status
Simulation time	2880148413 ps
CPU time	6.99 seconds
Started	Feb 25 12:45:04 PM PST 24
Finished	Feb 25 12:45:11 PM PST 24
Peak memory	201224 kb
Host	smart-4454783b-9122-42c9-8c88-3458fce83e21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3952131517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3952131517
Directory	/workspace/8.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/8.adc_ctrl_smoke.1024550419
Short name	T610
Test name
Test status
Simulation time	6064141007 ps
CPU time	4.86 seconds
Started	Feb 25 12:45:07 PM PST 24
Finished	Feb 25 12:45:12 PM PST 24
Peak memory	201280 kb
Host	smart-c9b28249-84c2-4069-8d60-5134e295f766
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1024550419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1024550419
Directory	/workspace/8.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.adc_ctrl_stress_all.658439813
Short name	T359
Test name
Test status
Simulation time	578030948662 ps
CPU time	766.55 seconds
Started	Feb 25 12:45:08 PM PST 24
Finished	Feb 25 12:57:55 PM PST 24
Peak memory	201796 kb
Host	smart-d082c0c6-27be-4957-80f8-7dc6814cabe0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658439813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.658439813
Directory	/workspace/8.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2373369460
Short name	T46
Test name
Test status
Simulation time	45885544558 ps
CPU time	127.06 seconds
Started	Feb 25 12:45:15 PM PST 24
Finished	Feb 25 12:47:22 PM PST 24
Peak memory	210172 kb
Host	smart-31dd9c91-5c9d-4222-a54f-6e2ae807431d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373369460 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2373369460
Directory	/workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.adc_ctrl_alert_test.1692587566
Short name	T490
Test name
Test status
Simulation time	321577129 ps
CPU time	1.4 seconds
Started	Feb 25 12:45:01 PM PST 24
Finished	Feb 25 12:45:02 PM PST 24
Peak memory	201136 kb
Host	smart-a978d6b6-73a0-4e7a-9f33-b2f2461fbef5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692587566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1692587566
Directory	/workspace/9.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.adc_ctrl_clock_gating.721578801
Short name	T12
Test name
Test status
Simulation time	160923679347 ps
CPU time	288.42 seconds
Started	Feb 25 12:45:14 PM PST 24
Finished	Feb 25 12:50:03 PM PST 24
Peak memory	201464 kb
Host	smart-2167b199-9e14-47d1-8975-d45e9fb42bb7
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721578801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin g.721578801
Directory	/workspace/9.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_interrupt.110819465
Short name	T666
Test name
Test status
Simulation time	490898168294 ps
CPU time	1141.44 seconds
Started	Feb 25 12:45:08 PM PST 24
Finished	Feb 25 01:04:10 PM PST 24
Peak memory	201472 kb
Host	smart-24b5e48b-9bc0-4102-b69c-25e3853797bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110819465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.110819465
Directory	/workspace/9.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2910395793
Short name	T598
Test name
Test status
Simulation time	486086447227 ps
CPU time	280.95 seconds
Started	Feb 25 12:45:04 PM PST 24
Finished	Feb 25 12:49:45 PM PST 24
Peak memory	201400 kb
Host	smart-3554bdc5-ab04-487f-9b6a-88e1a4aaecb6
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910395793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup t_fixed.2910395793
Directory	/workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_polled.4133273264
Short name	T692
Test name
Test status
Simulation time	326865452106 ps
CPU time	365.46 seconds
Started	Feb 25 12:45:00 PM PST 24
Finished	Feb 25 12:51:05 PM PST 24
Peak memory	201396 kb
Host	smart-539d7923-c856-4d47-8fe6-80e33211a481
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4133273264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.4133273264
Directory	/workspace/9.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1310035201
Short name	T391
Test name
Test status
Simulation time	163214094675 ps
CPU time	351.79 seconds
Started	Feb 25 12:45:08 PM PST 24
Finished	Feb 25 12:51:00 PM PST 24
Peak memory	201464 kb
Host	smart-c5e4bc36-9516-427e-8539-4a124ac9561f
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310035201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe d.1310035201
Directory	/workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_wakeup.631741324
Short name	T120
Test name
Test status
Simulation time	335410907647 ps
CPU time	196.55 seconds
Started	Feb 25 12:45:00 PM PST 24
Finished	Feb 25 12:48:17 PM PST 24
Peak memory	201424 kb
Host	smart-18be0ed5-7b63-4f7b-b91a-fbdb29147ab0
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631741324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w akeup.631741324
Directory	/workspace/9.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.4285128112
Short name	T500
Test name
Test status
Simulation time	491738445806 ps
CPU time	255.61 seconds
Started	Feb 25 12:45:00 PM PST 24
Finished	Feb 25 12:49:16 PM PST 24
Peak memory	201508 kb
Host	smart-aa939e33-a858-4695-9519-26c3e9375c06
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285128112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9. adc_ctrl_filters_wakeup_fixed.4285128112
Directory	/workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/9.adc_ctrl_lowpower_counter.2918867545
Short name	T20
Test name
Test status
Simulation time	31645773993 ps
CPU time	67.58 seconds
Started	Feb 25 12:45:07 PM PST 24
Finished	Feb 25 12:46:15 PM PST 24
Peak memory	201284 kb
Host	smart-2fcc4710-3db2-4ee9-9bee-7ed84faaa999
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2918867545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2918867545
Directory	/workspace/9.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/9.adc_ctrl_poweron_counter.4042383484
Short name	T573
Test name
Test status
Simulation time	4842000448 ps
CPU time	3.46 seconds
Started	Feb 25 12:45:08 PM PST 24
Finished	Feb 25 12:45:12 PM PST 24
Peak memory	201244 kb
Host	smart-777dd673-5ff9-410c-92cb-56803f4ee218
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4042383484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.4042383484
Directory	/workspace/9.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/9.adc_ctrl_smoke.653889973
Short name	T416
Test name
Test status
Simulation time	6044888787 ps
CPU time	4.57 seconds
Started	Feb 25 12:45:08 PM PST 24
Finished	Feb 25 12:45:13 PM PST 24
Peak memory	201228 kb
Host	smart-86c51ce7-05ae-408a-a510-486524efacf7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=653889973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.653889973
Directory	/workspace/9.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.adc_ctrl_stress_all.2630290764
Short name	T178
Test name
Test status
Simulation time	191010487156 ps
CPU time	408.71 seconds
Started	Feb 25 12:45:07 PM PST 24
Finished	Feb 25 12:51:57 PM PST 24
Peak memory	201404 kb
Host	smart-3f992c39-f7c8-4a59-84ea-7de03d54c22d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630290764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all. 2630290764
Directory	/workspace/9.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1995354262
Short name	T31
Test name
Test status
Simulation time	202733360117 ps
CPU time	260.18 seconds
Started	Feb 25 12:45:07 PM PST 24
Finished	Feb 25 12:49:28 PM PST 24
Peak memory	209416 kb
Host	smart-76d52957-1089-45a3-a840-f1069c8918d4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995354262 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1995354262
Directory	/workspace/9.adc_ctrl_stress_all_with_rand_reset/latest