Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1210199	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1165284

1

T1

1328

T2

435

T3

6313

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2094177	1			T1	2446		T2	30		T3	12022
values[0x0]	140425	1			T1	137		T2	496		T3	416
values[0x1]	140881	1			T1	157		T2	476		T3	436

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	974726	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1400757

1

T1

1601

T2

522

T3

7554

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7847	1			T1	8		T2	6		T3	31
valid_sources[0x01]	7100	1			T1	8		T2	4		T3	29
valid_sources[0x02]	6959	1			T1	7		T2	4		T3	40
valid_sources[0x03]	10842	1			T1	16		T2	6		T3	23
valid_sources[0x04]	8583	1			T1	11		T2	4		T3	69
valid_sources[0x05]	7831	1			T1	6		T2	10		T3	41
valid_sources[0x06]	11616	1			T1	11		T2	1		T3	27
valid_sources[0x07]	6874	1			T1	20		T2	1		T3	55
valid_sources[0x08]	6692	1			T1	7		T2	1		T3	41
valid_sources[0x09]	11959	1			T1	12		T2	2		T3	39
valid_sources[0x0a]	6601	1			T1	11		T2	5		T3	66
valid_sources[0x0b]	7883	1			T1	18		T2	5		T3	46
valid_sources[0x0c]	6620	1			T1	12		T2	4		T3	45
valid_sources[0x0d]	6764	1			T1	5		T2	7		T3	18
valid_sources[0x0e]	6913	1			T1	12		T2	2		T3	54
valid_sources[0x0f]	9763	1			T1	11		T2	4		T3	24
valid_sources[0x10]	6828	1			T1	10		T2	5		T3	42
valid_sources[0x11]	9227	1			T1	9		T2	4		T3	61
valid_sources[0x12]	6544	1			T1	17		T2	2		T3	53
valid_sources[0x13]	15133	1			T1	6		T2	6		T3	39
valid_sources[0x14]	7473	1			T1	4		T2	5		T3	73
valid_sources[0x15]	7844	1			T1	5		T2	2		T3	37
valid_sources[0x16]	9509	1			T1	11		T2	6		T3	64
valid_sources[0x17]	10667	1			T1	14		T2	3		T3	51
valid_sources[0x18]	10902	1			T1	7		T2	2		T3	30
valid_sources[0x19]	8921	1			T1	8		T2	5		T3	27
valid_sources[0x1a]	8583	1			T1	19		T2	2		T3	75
valid_sources[0x1b]	6829	1			T1	14		T3	38		T5	89
valid_sources[0x1c]	7426	1			T1	11		T2	3		T3	49
valid_sources[0x1d]	6629	1			T1	10		T2	2		T3	35
valid_sources[0x1e]	6811	1			T1	11		T3	48		T5	64
valid_sources[0x1f]	8136	1			T1	16		T2	5		T3	25
valid_sources[0x20]	6680	1			T1	19		T2	4		T3	52
valid_sources[0x21]	9081	1			T1	6		T2	3		T3	86
valid_sources[0x22]	6915	1			T1	13		T2	4		T3	27
valid_sources[0x23]	6904	1			T1	9		T2	4		T3	13
valid_sources[0x24]	6831	1			T1	11		T2	3		T3	24
valid_sources[0x25]	7637	1			T1	11		T2	1		T3	71
valid_sources[0x26]	6252	1			T1	15		T2	5		T3	34
valid_sources[0x27]	16462	1			T1	8		T2	7		T3	122
valid_sources[0x28]	9617	1			T1	17		T2	7		T3	52
valid_sources[0x29]	7767	1			T1	8		T3	35		T5	70
valid_sources[0x2a]	12616	1			T1	13		T2	5		T3	32
valid_sources[0x2b]	12089	1			T1	11		T2	1		T3	28
valid_sources[0x2c]	7517	1			T1	12		T2	4		T3	22
valid_sources[0x2d]	6845	1			T1	14		T2	2		T3	53
valid_sources[0x2e]	7651	1			T1	10		T2	2		T3	94
valid_sources[0x2f]	7276	1			T1	11		T2	3		T3	36
valid_sources[0x30]	11077	1			T1	18		T2	7		T3	33
valid_sources[0x31]	11021	1			T1	9		T2	1		T3	58
valid_sources[0x32]	9014	1			T1	15		T2	5		T3	45
valid_sources[0x33]	9494	1			T1	6		T2	3		T3	52
valid_sources[0x34]	11800	1			T1	9		T2	4		T3	46
valid_sources[0x35]	21061	1			T1	11		T2	4		T3	64
valid_sources[0x36]	6699	1			T1	12		T2	8		T3	57
valid_sources[0x37]	9624	1			T1	10		T2	2		T3	33
valid_sources[0x38]	12468	1			T1	11		T2	6		T3	71
valid_sources[0x39]	11011	1			T1	3		T2	3		T3	49
valid_sources[0x3a]	19734	1			T1	8		T2	4		T3	25
valid_sources[0x3b]	13502	1			T1	15		T2	4		T3	113
valid_sources[0x3c]	10534	1			T1	10		T2	3		T3	31
valid_sources[0x3d]	9727	1			T1	8		T2	1		T3	26
valid_sources[0x3e]	11384	1			T1	8		T2	1		T3	45
valid_sources[0x3f]	8717	1			T1	14		T2	3		T3	53
valid_sources[0x40]	11212	1			T1	17		T2	4		T3	76
valid_sources[0x41]	10057	1			T1	10		T2	5		T3	74
valid_sources[0x42]	9261	1			T1	12		T3	58		T5	38
valid_sources[0x43]	20293	1			T1	13		T2	1		T3	30
valid_sources[0x44]	7425	1			T1	12		T2	5		T3	54
valid_sources[0x45]	7423	1			T1	11		T2	4		T3	90
valid_sources[0x46]	11679	1			T1	7		T2	4		T3	61
valid_sources[0x47]	11012	1			T1	5		T2	5		T3	35
valid_sources[0x48]	11185	1			T1	5		T2	3		T3	46
valid_sources[0x49]	11239	1			T1	9		T2	5		T3	51
valid_sources[0x4a]	11331	1			T1	13		T2	9		T3	39
valid_sources[0x4b]	12170	1			T1	3		T2	4		T3	51
valid_sources[0x4c]	7014	1			T1	9		T2	6		T3	70
valid_sources[0x4d]	7082	1			T1	21		T2	2		T3	64
valid_sources[0x4e]	8102	1			T1	9		T2	3		T3	54
valid_sources[0x4f]	7429	1			T1	9		T2	3		T3	46
valid_sources[0x50]	7099	1			T1	10		T2	6		T3	33
valid_sources[0x51]	7306	1			T1	13		T2	6		T3	40
valid_sources[0x52]	7501	1			T1	3		T2	5		T3	67
valid_sources[0x53]	10804	1			T1	6		T2	2		T3	53
valid_sources[0x54]	6852	1			T1	5		T2	2		T3	74
valid_sources[0x55]	7177	1			T1	13		T2	2		T3	36
valid_sources[0x56]	6979	1			T1	13		T2	6		T3	57
valid_sources[0x57]	13827	1			T1	11		T2	1		T3	40
valid_sources[0x58]	6761	1			T1	14		T2	5		T3	19
valid_sources[0x59]	8572	1			T1	10		T2	8		T3	63
valid_sources[0x5a]	11176	1			T1	8		T2	7		T3	41
valid_sources[0x5b]	20100	1			T1	9		T2	4		T3	92
valid_sources[0x5c]	7205	1			T1	16		T2	4		T3	43
valid_sources[0x5d]	9707	1			T1	14		T2	8		T3	102
valid_sources[0x5e]	6709	1			T1	12		T2	2		T3	41
valid_sources[0x5f]	11171	1			T1	9		T2	6		T3	63
valid_sources[0x60]	6689	1			T1	11		T2	8		T3	49
valid_sources[0x61]	6825	1			T1	8		T2	2		T3	47
valid_sources[0x62]	15400	1			T1	15		T2	7		T3	102
valid_sources[0x63]	7131	1			T1	9		T2	1		T3	51
valid_sources[0x64]	9681	1			T1	10		T2	1		T3	47
valid_sources[0x65]	6537	1			T1	8		T2	3		T3	49
valid_sources[0x66]	10756	1			T1	8		T2	5		T3	38
valid_sources[0x67]	6946	1			T1	7		T2	2		T3	64
valid_sources[0x68]	17051	1			T1	11		T2	4		T3	92
valid_sources[0x69]	6712	1			T1	10		T2	8		T3	71
valid_sources[0x6a]	11657	1			T1	3		T2	3		T3	59
valid_sources[0x6b]	6618	1			T1	9		T2	3		T3	73
valid_sources[0x6c]	8817	1			T1	10		T2	1		T3	51
valid_sources[0x6d]	8237	1			T1	11		T2	6		T3	73
valid_sources[0x6e]	6774	1			T1	13		T2	6		T3	47
valid_sources[0x6f]	7044	1			T1	8		T2	5		T3	52
valid_sources[0x70]	11304	1			T1	12		T2	3		T3	42
valid_sources[0x71]	12108	1			T1	17		T2	2		T3	35
valid_sources[0x72]	7117	1			T1	10		T2	2		T3	57
valid_sources[0x73]	6694	1			T1	13		T2	2		T3	39
valid_sources[0x74]	6576	1			T1	10		T2	4		T3	63
valid_sources[0x75]	9979	1			T1	10		T2	4		T3	47
valid_sources[0x76]	7403	1			T1	12		T2	3		T3	22
valid_sources[0x77]	10975	1			T1	19		T2	3		T3	49
valid_sources[0x78]	8475	1			T1	8		T2	4		T3	16
valid_sources[0x79]	6557	1			T1	11		T2	2		T3	60
valid_sources[0x7a]	11174	1			T1	3		T2	2		T3	43
valid_sources[0x7b]	6939	1			T1	2		T2	6		T3	55
valid_sources[0x7c]	11487	1			T1	13		T2	5		T3	48
valid_sources[0x7d]	6804	1			T1	10		T2	4		T3	69
valid_sources[0x7e]	6678	1			T1	5		T2	5		T3	33
valid_sources[0x7f]	6570	1			T1	8		T2	2		T3	55
valid_sources[0x80]	7005	1			T1	13		T2	4		T3	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1044782

1

T1

1222

T2

15

T3

6019

values[0x0]

all_enables

biggest_size

70094

1

T1

55

T2

253

T3

183

values[0x1]

all_enables

biggest_size

50408

1

T1

51

T2

167

T3

111