Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	27987	1			T1	19		T2	229		T3	20
auto[PWRUP]	99	1			T2	2		T16	2		T15	2
auto[ONEST_0]	59	1			T2	1		T23	1		T168	1
auto[ONEST_021]	12	1			T15	1		T27	1		T28	1
auto[ONEST_1]	59	1			T16	2		T15	3		T29	3
auto[ONEST_DONE]	7	1			T23	1		T169	1		T170	1
auto[LP_0]	118	1			T2	3		T16	3		T21	1
auto[LP_021]	23	1			T15	1		T23	1		T27	1
auto[LP_1]	120	1			T2	2		T16	1		T25	1
auto[LP_EVAL]	64	1			T15	2		T23	1		T24	1
auto[LP_SLP]	450	1			T2	7		T16	5		T25	1
auto[LP_PWRUP]	28	1			T29	1		T171	2		T172	1
auto[NP_0]	132	1			T2	2		T25	1		T15	3
auto[NP_021]	31	1			T2	2		T28	1		T29	1
auto[NP_1]	158	1			T2	2		T16	4		T25	1
auto[NP_EVAL]	27	1			T23	1		T29	1		T173	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

4

1

T174

1

T175

1

T176

1

min

27514

1

T1

19

T2

226

T3

20

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27519	1			T1	19		T2	226		T3	20
pow[0x1]	6	1			T29	2		T177	1		T171	1
pow[0x2]	16	1			T28	1		T177	1		T172	2
pow[0x3]	24	1			T15	1		T29	1		T173	1
pow[0x4]	56	1			T168	1		T28	2		T29	1
pow[0x5]	127	1			T2	2		T16	2		T15	3
pow[0x6]	219	1			T2	4		T16	5		T21	2
pow[0x7]	494	1			T2	6		T16	5		T25	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

157

1

T2

3

T16

1

T15

5

min

27095

1

T1

19

T2

216

T3

20

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27095	1			T1	19		T2	216		T3	20
pow[0x1]	1	1			T178	1		-	-		-	-
pow[0x4]	2	1			T28	1		T179	1		-	-
pow[0x5]	1	1			T180	1		-	-		-	-
pow[0x7]	3	1			T2	1		T181	1		T176	1
pow[0x8]	6	1			T2	1		T177	1		T182	1
pow[0x9]	15	1			T168	1		T28	1		T171	2
pow[0xa]	13	1			T183	1		T181	1		T184	1
pow[0xb]	29	1			T168	1		T173	1		T174	1
pow[0xc]	70	1			T16	1		T25	1		T21	1
pow[0xd]	131	1			T2	2		T16	1		T25	1
pow[0xe]	277	1			T2	1		T16	2		T15	9
pow[0xf]	517	1			T2	8		T16	7		T25	1