Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	2	15	88.24	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	2	15	88.24

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[ONEST_DONE]	0	1	1
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2083	1			T2	16		T4	2		T14	20
auto[PWRUP]	120	1			T2	1		T16	1		T21	1
auto[ONEST_0]	67	1			T16	1		T15	2		T23	2
auto[ONEST_021]	24	1			T2	1		T21	1		T15	1
auto[ONEST_1]	88	1			T16	1		T15	4		T26	2
auto[LP_0]	124	1			T2	4		T16	2		T21	1
auto[LP_021]	30	1			T15	1		T26	1		T168	1
auto[LP_1]	128	1			T2	1		T16	1		T15	5
auto[LP_EVAL]	53	1			T15	1		T168	1		T29	1
auto[LP_SLP]	462	1			T2	3		T16	6		T25	3
auto[LP_PWRUP]	27	1			T27	1		T28	1		T174	1
auto[NP_0]	191	1			T2	1		T16	3		T25	3
auto[NP_021]	48	1			T16	1		T25	1		T15	1
auto[NP_1]	222	1			T2	3		T25	2		T21	4
auto[NP_EVAL]	30	1			T26	1		T28	1		T29	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T185

1

T158

1

T186

1

min

1827

1

T2

9

T4

2

T14

20

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1835	1			T2	9		T4	2		T14	20
pow[0x1]	6	1			T171	1		T31	1		T51	1
pow[0x2]	13	1			T28	1		T187	1		T169	1
pow[0x3]	33	1			T2	1		T16	1		T25	1
pow[0x4]	72	1			T2	1		T25	1		T15	1
pow[0x5]	114	1			T2	2		T16	1		T25	1
pow[0x6]	247	1			T2	3		T16	4		T25	3
pow[0x7]	496	1			T2	3		T16	9		T25	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

184

1

T2

1

T16

2

T25

1

min

1243

1

T2

7

T4

2

T14

20

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1246	1			T2	7		T4	2		T14	20
pow[0x1]	20	1			T163	1		T188	1		T189	1
pow[0x2]	38	1			T25	3		T21	2		T23	1
pow[0x3]	44	1			T21	3		T15	5		T23	6
pow[0x4]	46	1			T24	2		T161	2		T162	5
pow[0x6]	1	1			T190	1		-	-		-	-
pow[0x8]	5	1			T15	1		T38	1		T191	1
pow[0x9]	16	1			T168	2		T29	3		T31	1
pow[0xa]	19	1			T16	1		T15	2		T28	1
pow[0xb]	38	1			T16	1		T24	1		T28	1
pow[0xc]	72	1			T25	2		T21	1		T15	1
pow[0xd]	129	1			T2	2		T15	6		T23	1
pow[0xe]	287	1			T2	3		T16	6		T25	2
pow[0xf]	511	1			T2	5		T16	6		T25	3