Unified Coverage Report :: Module :: adc_ctrl_fsm

Module : adc_ctrl_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	96.84		100.00	92.77	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm	97.92	100.00	96.84		100.00	92.77	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	96.84		100.00	92.77	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	96.84		100.00	92.77	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_adc_ctrl_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm_sva	100.00						100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_fsm

	Line No.	Total	Covered	Percent
TOTAL		157	157	100.00
ALWAYS	58	5	5	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	74	5	5	100.00
CONT_ASSIGN	84	1	1	100.00
ALWAYS	87	5	5	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	100	5	5	100.00
CONT_ASSIGN	110	1	1	100.00
ALWAYS	114	5	5	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
ALWAYS	133	14	14	100.00
ALWAYS	156	6	6	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	175	5	5	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
ALWAYS	190	91	91	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
59	1	1
61	1	1
62	1	1
64	1	1
68	1	1
69	1	1
71	1	1
74	1	1
75	1	1
77	1	1
78	1	1
80	1	1
84	1	1
87	1	1
88	1	1
90	1	1
91	1	1
93	1	1
97	1	1
100	1	1
101	1	1
103	1	1
104	1	1
106	1	1
110	1	1
114	1	1
115	1	1
117	1	1
118	1	1
120	1	1
124	1	1
125	1	1
126	1	1
128	1	1
129	1	1
130	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
140	1	1
141	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
156	1	1
157	1	1
159	1	1
160	1	1
162	1	1
163	1	1
			MISSING_ELSE
168	1	1
172	1	1
175	1	1
176	1	1
178	1	1
179	1	1
181	1	1
185	1	1
186	1	1
190	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
204	1	1
206	1	1
208	1	1
209	1	1
210	1	1
			MISSING_ELSE
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
221	1	1
223	1	1
224	1	1
226	1	1
227	1	1
			==> MISSING_ELSE
			==> MISSING_ELSE
233	1	1
234	1	1
235	1	1
			MISSING_ELSE
240	1	1
241	1	1
			MISSING_ELSE
246	1	1
247	1	1
248	1	1
			MISSING_ELSE
255	1	1
256	1	1
260	1	1
261	1	1
262	1	1
			MISSING_ELSE
267	1	1
268	1	1
			MISSING_ELSE
273	1	1
274	1	1
275	1	1
			MISSING_ELSE
281	1	1
282	1	1
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
			MISSING_ELSE
			MISSING_ELSE
297	1	1
298	1	1
299	1	1
301	1	1
302	1	1
303	1	1
			==> MISSING_ELSE
308	1	1
309	1	1
311	1	1
312	1	1
313	1	1
			==> MISSING_ELSE
318	1	1
319	1	1
320	1	1
			MISSING_ELSE
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
332	1	1
333	1	1
			MISSING_ELSE
339	1	1
340	1	1
349	1	1
350	1	1
351	1	1
352	1	1
353	1	1
354	1	1
355	1	1
356	1	1
357	1	1
358	1	1
359	1	1
			==> MISSING_ELSE
			MISSING_ELSE
366	1	1
367	1	1

---

Cond Coverage for Module : adc_ctrl_fsm

	Total	Covered	Percent
Conditions	95	92	96.84
Logical	95	92	96.84
Non-Logical	0	0
Event	0	0

 LINE       68
 EXPRESSION ((trigger_q == 1'b0) && (cfg_adc_enable_i == 1'b1))
             ---------1---------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       68
 SUB-EXPRESSION (trigger_q == 1'b0)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       68
 SUB-EXPRESSION (cfg_adc_enable_i == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       69
 EXPRESSION ((trigger_q == 1'b1) && (cfg_adc_enable_i == 1'b0))
             ---------1---------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       69
 SUB-EXPRESSION (trigger_q == 1'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       69
 SUB-EXPRESSION (cfg_adc_enable_i == 1'b0)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 EXPRESSION (pwrup_timer_cnt_en ? ((pwrup_timer_cnt_q + 1'b1)) : pwrup_timer_cnt_q)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       77
 EXPRESSION (pwrup_timer_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
             ---------1---------    ------2------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (lp_sample_cnt_en ? ((lp_sample_cnt_q + 1'b1)) : lp_sample_cnt_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T12

 LINE       90
 EXPRESSION (lp_sample_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
             --------1--------    ------2------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T2,T4,T5

 LINE       97
 EXPRESSION (np_sample_cnt_en ? ((np_sample_cnt_q + 1'b1)) : np_sample_cnt_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       103
 EXPRESSION (np_sample_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
             --------1--------    ------2------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       110
 EXPRESSION (wakeup_timer_cnt_en ? ((wakeup_timer_cnt_q + 1'b1)) : wakeup_timer_cnt_q)
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       117
 EXPRESSION (wakeup_timer_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
             ----------1---------    ------2------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T2,T4,T5

 LINE       124
 EXPRESSION ((fsm_state_q == ONEST_0) || (fsm_state_q == LP_0) || (fsm_state_q == NP_0))
             ------------1-----------    ----------2----------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T2,T4,T5
1	0	0	Covered	T2,T4,T9

 LINE       124
 SUB-EXPRESSION (fsm_state_q == ONEST_0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T9

 LINE       124
 SUB-EXPRESSION (fsm_state_q == LP_0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       124
 SUB-EXPRESSION (fsm_state_q == NP_0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION (fsm_chn0_sel && adc_d_val_i)
             ------1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (chn0_val_we_d ? adc_d_i : chn0_val_o)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION ((fsm_state_q == ONEST_1) || (fsm_state_q == LP_1) || (fsm_state_q == NP_1))
             ------------1-----------    ----------2----------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T2,T4,T5
1	0	0	Covered	T2,T4,T9

 LINE       128
 SUB-EXPRESSION (fsm_state_q == ONEST_1)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T9

 LINE       128
 SUB-EXPRESSION (fsm_state_q == LP_1)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       128
 SUB-EXPRESSION (fsm_state_q == NP_1)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       129
 EXPRESSION (fsm_chn1_sel && adc_d_val_i)
             ------1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION (chn1_val_we_d ? adc_d_i : chn1_val_o)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       168
 EXPRESSION (((|adc_ctrl_match_i)) & ((adc_ctrl_match_i == adc_ctrl_match_q) | ((~|adc_ctrl_match_q))))
             ----------1----------   --------------------------------2--------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       168
 SUB-EXPRESSION ((adc_ctrl_match_i == adc_ctrl_match_q) | ((~|adc_ctrl_match_q)))
                 -------------------1------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       168
 SUB-EXPRESSION (adc_ctrl_match_i == adc_ctrl_match_q)
                -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       178
 EXPRESSION (trigger_h2l || cfg_fsm_rst_i)
             -----1-----    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       215
 EXPRESSION (pwrup_timer_cnt_q != cfg_pwrup_time_i)
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       218
 EXPRESSION (pwrup_timer_cnt_q == cfg_pwrup_time_i)
            -------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION (lp_sample_cnt_q == lp_sample_cnt_thresh)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T15,T23,T24
1	Covered	T4,T11,T12

 LINE       298
 EXPRESSION (wakeup_timer_cnt_q != cfg_wakeup_time_i)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       301
 EXPRESSION (wakeup_timer_cnt_q == cfg_wakeup_time_i)
            --------------------1--------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T4,T5

 LINE       308
 EXPRESSION (pwrup_timer_cnt_q != cfg_pwrup_time_i)
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       311
 EXPRESSION (pwrup_timer_cnt_q == cfg_pwrup_time_i)
            -------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T4,T5

 LINE       355
 EXPRESSION (np_sample_cnt_q == np_sample_cnt_thresh)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

---

FSM Coverage for Module : adc_ctrl_fsm

Summary for FSM :: fsm_state_q

	Total	Covered	Percent
States	17	17	100.00	(Not included in score)
Transitions	36	36	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fsm_state_q

---

states	Line No.	Covered	Tests
LP_0	224	Covered	T2,T4,T5
LP_021	262	Covered	T2,T4,T5
LP_1	268	Covered	T2,T4,T5
LP_EVAL	275	Covered	T2,T4,T5
LP_PWRUP	302	Covered	T2,T4,T5
LP_SLP	284	Covered	T2,T4,T5
NP_0	227	Covered	T1,T2,T3
NP_021	320	Covered	T1,T2,T3
NP_1	326	Covered	T1,T2,T3
NP_DONE	356	Covered	T1,T3,T4
NP_EVAL	333	Covered	T1,T2,T3
ONEST_0	221	Covered	T2,T4,T9
ONEST_021	235	Covered	T2,T4,T9
ONEST_1	241	Covered	T2,T4,T9
ONEST_DONE	248	Covered	T2,T4,T9
PWRDN	179	Covered	T1,T2,T3
PWRUP	210	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
LP_0->LP_021	262	Covered	T2,T4,T5
LP_0->PWRDN	179	Covered	T2,T16,T25
LP_021->LP_1	268	Covered	T2,T4,T5
LP_021->PWRDN	179	Covered	T15,T23,T26
LP_1->LP_EVAL	275	Covered	T2,T4,T5
LP_1->PWRDN	179	Covered	T2,T16,T25
LP_EVAL->LP_SLP	284	Covered	T2,T4,T5
LP_EVAL->NP_0	290	Covered	T4,T11,T12
LP_EVAL->PWRDN	179	Covered	T2,T5,T10
LP_PWRUP->LP_0	313	Covered	T2,T4,T5
LP_PWRUP->PWRDN	179	Covered	T27,T28,T29
LP_SLP->LP_PWRUP	302	Covered	T2,T4,T5
LP_SLP->PWRDN	179	Covered	T2,T5,T10
NP_0->NP_021	320	Covered	T1,T2,T3
NP_0->PWRDN	179	Covered	T1,T2,T3
NP_021->NP_1	326	Covered	T1,T2,T3
NP_021->PWRDN	179	Covered	T2,T16,T25
NP_1->NP_EVAL	333	Covered	T1,T2,T3
NP_1->PWRDN	179	Covered	T2,T16,T25
NP_DONE->NP_0	367	Covered	T1,T3,T4
NP_DONE->PWRDN	179	Covered	T23,T30,T31
NP_EVAL->NP_0	350	Covered	T1,T2,T3
NP_EVAL->NP_DONE	356	Covered	T1,T3,T4
NP_EVAL->PWRDN	179	Covered	T2,T16,T22
ONEST_0->ONEST_021	235	Covered	T2,T4,T9
ONEST_0->PWRDN	179	Covered	T2,T16,T21
ONEST_021->ONEST_1	241	Covered	T2,T4,T9
ONEST_021->PWRDN	179	Covered	T2,T21,T15
ONEST_1->ONEST_DONE	248	Covered	T2,T4,T9
ONEST_1->PWRDN	179	Covered	T16,T15,T26
ONEST_DONE->PWRDN	179	Covered	T2,T4,T9
PWRDN->PWRUP	210	Covered	T1,T2,T3
PWRUP->LP_0	224	Covered	T2,T4,T5
PWRUP->NP_0	227	Covered	T1,T2,T3
PWRUP->ONEST_0	221	Covered	T2,T4,T9
PWRUP->PWRDN	179	Covered	T2,T16,T25

---

Branch Coverage for Module : adc_ctrl_fsm

	Line No.	Total	Covered	Percent
Branches		83	77	92.77
TERNARY	71	2	2	100.00
TERNARY	84	2	2	100.00
TERNARY	97	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	126	2	2	100.00
TERNARY	130	2	2	100.00
IF	58	3	3	100.00
IF	74	3	3	100.00
IF	87	3	3	100.00
IF	100	3	3	100.00
IF	114	3	3	100.00
IF	133	3	3	100.00
IF	156	4	4	100.00
IF	175	3	3	100.00
CASE	206	46	40	86.96

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	(pwrup_timer_cnt_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	84	(lp_sample_cnt_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	97	(np_sample_cnt_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(wakeup_timer_cnt_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	(chn0_val_we_d) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	(chn1_val_we_d) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	58	if ((!rst_aon_ni))
-2-:	61	if (cfg_fsm_rst_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	74	if ((!rst_aon_ni))
-2-:	77	if (((pwrup_timer_cnt_clr || cfg_fsm_rst_i) || trigger_h2l))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	87	if ((!rst_aon_ni))
-2-:	90	if (((lp_sample_cnt_clr || cfg_fsm_rst_i) || trigger_h2l))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	if ((!rst_aon_ni))
-2-:	103	if (((np_sample_cnt_clr || cfg_fsm_rst_i) || trigger_h2l))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	114	if ((!rst_aon_ni))
-2-:	117	if (((wakeup_timer_cnt_clr || cfg_fsm_rst_i) || trigger_h2l))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	133	if ((!rst_aon_ni))
-2-:	139	if (cfg_fsm_rst_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	if ((!rst_aon_ni))
-2-:	159	if (cfg_fsm_rst_i)
-3-:	162	if (ld_match)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	175	if ((!rst_aon_ni))
-2-:	178	if ((trigger_h2l || cfg_fsm_rst_i))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	case (fsm_state_q)
-2-:	209	if (trigger_l2h)
-3-:	215	if ((pwrup_timer_cnt_q != cfg_pwrup_time_i))
-4-:	218	if ((pwrup_timer_cnt_q == cfg_pwrup_time_i))
-5-:	220	if (cfg_oneshot_mode_i)
-6-:	223	if (cfg_lp_mode_i)
-7-:	226	if ((!cfg_lp_mode_i))
-8-:	234	if (adc_d_val_i)
-9-:	240	if ((!adc_d_val_i))
-10-:	247	if (adc_d_val_i)
-11-:	261	if (adc_d_val_i)
-12-:	267	if ((!adc_d_val_i))
-13-:	274	if (adc_d_val_i)
-14-:	281	if ((!adc_d_val_i))
-15-:	283	if ((!stay_match))
-16-:	286	if ((lp_sample_cnt_q < lp_sample_cnt_thresh))
-17-:	289	if ((lp_sample_cnt_q == lp_sample_cnt_thresh))
-18-:	298	if ((wakeup_timer_cnt_q != cfg_wakeup_time_i))
-19-:	301	if ((wakeup_timer_cnt_q == cfg_wakeup_time_i))
-20-:	308	if ((pwrup_timer_cnt_q != cfg_pwrup_time_i))
-21-:	311	if ((pwrup_timer_cnt_q == cfg_pwrup_time_i))
-22-:	319	if (adc_d_val_i)
-23-:	325	if ((!adc_d_val_i))
-24-:	332	if (adc_d_val_i)
-25-:	339	if ((!adc_d_val_i))
-26-:	349	if ((!stay_match))
-27-:	352	if ((np_sample_cnt_q < np_sample_cnt_thresh))
-28-:	355	if ((np_sample_cnt_q == np_sample_cnt_thresh))
-29-:	358	if ((np_sample_cnt_q > np_sample_cnt_thresh))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	Status	Tests
PWRDN	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
PWRDN	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
PWRUP	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
PWRUP	-	0	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T9
PWRUP	-	0	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
PWRUP	-	0	1	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
PWRUP	-	0	1	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
PWRUP	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ONEST_0	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T9
ONEST_0	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T9
ONEST_021	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T9
ONEST_021	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T9
ONEST_1	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T9
ONEST_1	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T9
ONEST_DONE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T9
LP_0	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
LP_0	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
LP_021	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
LP_021	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
LP_1	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
LP_1	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
LP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
LP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12
LP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12
LP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T23,T24
LP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
LP_SLP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
LP_SLP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
LP_SLP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	Not Covered
LP_PWRUP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
LP_PWRUP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
LP_PWRUP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	Not Covered
NP_0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
NP_0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
NP_021	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T3
NP_021	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T2,T3
NP_1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
NP_1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	Covered	T1,T2,T3
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	Covered	T1,T3,T4
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	1	-	Covered	T1,T3,T4
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	0	1	Covered	T1,T2,T3
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	0	0	Not Covered
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
NP_DONE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

---

Assert Coverage for Module : adc_ctrl_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
LpSampleCntCfg_M	30719749	30640352	0	0
NpCntClrMisMatch_A	30719749	168320	0	0
NpCntClrPwrDn_A	30719749	93320	0	0
NpSampleCntCfg_M	30719749	30640352	0	0

LpSampleCntCfg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	30719749	30640352	0	0
T1	95490	95423	0	0
T2	5216	4898	0	0
T3	98004	97938	0	0
T4	36118	35849	0	0
T5	139938	139479	0	0
T6	32924	32870	0	0
T7	34275	34198	0	0
T8	31931	31854	0	0
T9	1160	1072	0	0
T14	83	1	0	0

NpCntClrMisMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30719749	168320	0	0
T1	95490	954	0	0
T2	5216	33	0	0
T3	98004	1058	0	0
T4	36118	113	0	0
T5	139938	329	0	0
T6	32924	309	0	0
T7	34275	336	0	0
T8	31931	350	0	0
T9	1160	0	0	0
T10	0	42	0	0
T14	83	0	0	0
T22	0	11	0	0

NpCntClrPwrDn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30719749	93320	0	0
T1	95490	196	0	0
T2	5216	51	0	0
T3	98004	198	0	0
T4	36118	325	0	0
T5	139938	361	0	0
T6	32924	74	0	0
T7	34275	71	0	0
T8	31931	71	0	0
T9	1160	251	0	0
T14	83	1	0	0

NpSampleCntCfg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	30719749	30640352	0	0
T1	95490	95423	0	0
T2	5216	4898	0	0
T3	98004	97938	0	0
T4	36118	35849	0	0
T5	139938	139479	0	0
T6	32924	32870	0	0
T7	34275	34198	0	0
T8	31931	31854	0	0
T9	1160	1072	0	0
T14	83	1	0	0