Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	6087	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1646	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1561	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1479	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1639	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1607	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1644	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1546	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1482	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1670	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1593	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1556	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1527	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1550	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1725	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1639	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1664	0	0
adc_en_ctl_rd_A	2147483647	1486	0	0
adc_fsm_rst_rd_A	2147483647	1217	0	0
adc_intr_ctl_rd_A	2147483647	1228	0	0
adc_lp_sample_ctl_rd_A	2147483647	1265	0	0
adc_pd_ctl_rd_A	2147483647	1388	0	0
adc_sample_ctl_rd_A	2147483647	1165	0	0
adc_wakeup_ctl_rd_A	2147483647	1150	0	0
intr_enable_rd_A	2147483647	1805	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6087	0	0
T15	514344	3	0	0
T20	863360	0	0	0
T21	841604	2	0	0
T23	613913	0	0	0
T25	226545	1	0	0
T42	45917	0	0	0
T51	0	1	0	0
T56	252320	0	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	2	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1646	0	0
T15	514344	0	0	0
T21	841604	19	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	52	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	12	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	13	0	0
T161	0	20	0	0
T162	0	27	0	0
T163	0	15	0	0
T164	0	21	0	0
T165	0	8	0	0
T166	0	28	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1561	0	0
T15	514344	0	0	0
T21	841604	23	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	45	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	28	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	8	0	0
T161	0	19	0	0
T162	0	42	0	0
T163	0	16	0	0
T164	0	54	0	0
T165	0	8	0	0
T166	0	33	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1479	0	0
T15	514344	0	0	0
T21	841604	34	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	30	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	12	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	5	0	0
T161	0	27	0	0
T162	0	29	0	0
T163	0	4	0	0
T164	0	38	0	0
T165	0	22	0	0
T166	0	27	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1639	0	0
T15	514344	0	0	0
T21	841604	24	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	49	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	11	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	15	0	0
T161	0	24	0	0
T162	0	34	0	0
T163	0	12	0	0
T164	0	44	0	0
T165	0	9	0	0
T166	0	33	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1607	0	0
T15	514344	0	0	0
T21	841604	31	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	31	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	17	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	21	0	0
T161	0	11	0	0
T162	0	42	0	0
T163	0	15	0	0
T164	0	47	0	0
T165	0	13	0	0
T166	0	42	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1644	0	0
T15	514344	0	0	0
T21	841604	36	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	36	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	4	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	24	0	0
T161	0	9	0	0
T162	0	52	0	0
T163	0	16	0	0
T164	0	35	0	0
T165	0	18	0	0
T166	0	39	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1546	0	0
T15	514344	0	0	0
T21	841604	19	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	32	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	20	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	9	0	0
T161	0	18	0	0
T162	0	37	0	0
T163	0	28	0	0
T164	0	32	0	0
T165	0	9	0	0
T166	0	31	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1482	0	0
T15	514344	0	0	0
T21	841604	28	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	41	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	10	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	24	0	0
T161	0	9	0	0
T162	0	27	0	0
T163	0	21	0	0
T164	0	43	0	0
T165	0	5	0	0
T166	0	44	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1670	0	0
T15	514344	0	0	0
T21	841604	27	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	36	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	20	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	18	0	0
T161	0	20	0	0
T162	0	52	0	0
T163	0	19	0	0
T164	0	41	0	0
T165	0	12	0	0
T166	0	26	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1593	0	0
T15	514344	0	0	0
T21	841604	34	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	48	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	15	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	25	0	0
T161	0	28	0	0
T162	0	33	0	0
T163	0	13	0	0
T164	0	40	0	0
T165	0	8	0	0
T166	0	29	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1556	0	0
T15	514344	0	0	0
T21	841604	36	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	45	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	11	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	12	0	0
T161	0	4	0	0
T162	0	30	0	0
T163	0	22	0	0
T164	0	23	0	0
T165	0	14	0	0
T166	0	42	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1527	0	0
T15	514344	0	0	0
T21	841604	32	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	15	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	18	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	21	0	0
T161	0	21	0	0
T162	0	45	0	0
T163	0	14	0	0
T164	0	24	0	0
T165	0	10	0	0
T166	0	44	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1550	0	0
T15	514344	0	0	0
T21	841604	41	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	34	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	5	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	23	0	0
T161	0	25	0	0
T162	0	35	0	0
T163	0	21	0	0
T164	0	27	0	0
T165	0	13	0	0
T166	0	49	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1725	0	0
T15	514344	0	0	0
T21	841604	50	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	27	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	24	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	23	0	0
T161	0	18	0	0
T162	0	38	0	0
T163	0	9	0	0
T164	0	36	0	0
T165	0	8	0	0
T166	0	46	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1639	0	0
T15	514344	0	0	0
T21	841604	28	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	38	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	11	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	17	0	0
T161	0	20	0	0
T162	0	11	0	0
T163	0	5	0	0
T164	0	36	0	0
T165	0	23	0	0
T166	0	44	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1664	0	0
T15	514344	0	0	0
T21	841604	37	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	40	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	13	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	30	0	0
T161	0	17	0	0
T162	0	47	0	0
T163	0	10	0	0
T164	0	37	0	0
T165	0	7	0	0
T166	0	39	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1486	0	0
T15	514344	0	0	0
T21	841604	42	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	27	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	19	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	9	0	0
T161	0	29	0	0
T162	0	42	0	0
T163	0	16	0	0
T164	0	47	0	0
T165	0	18	0	0
T166	0	42	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1217	0	0
T15	514344	0	0	0
T21	841604	39	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	42	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	29	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	16	0	0
T161	0	27	0	0
T162	0	39	0	0
T163	0	13	0	0
T164	0	31	0	0
T165	0	13	0	0
T166	0	31	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1228	0	0
T15	514344	0	0	0
T21	841604	33	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	36	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	15	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	20	0	0
T161	0	27	0	0
T162	0	44	0	0
T163	0	13	0	0
T164	0	44	0	0
T165	0	16	0	0
T166	0	41	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1265	0	0
T15	514344	0	0	0
T21	841604	42	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	26	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	14	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	29	0	0
T161	0	21	0	0
T162	0	50	0	0
T163	0	16	0	0
T164	0	35	0	0
T165	0	19	0	0
T166	0	27	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1388	0	0
T15	514344	0	0	0
T21	841604	35	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	40	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	19	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	27	0	0
T161	0	13	0	0
T162	0	40	0	0
T163	0	17	0	0
T164	0	47	0	0
T165	0	11	0	0
T166	0	39	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1165	0	0
T15	514344	0	0	0
T21	841604	40	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	27	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	25	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	23	0	0
T161	0	18	0	0
T162	0	22	0	0
T163	0	21	0	0
T164	0	46	0	0
T165	0	7	0	0
T166	0	40	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1150	0	0
T15	514344	0	0	0
T21	841604	27	0	0
T23	613913	0	0	0
T24	255915	0	0	0
T30	0	29	0	0
T57	524814	0	0	0
T58	109083	0	0	0
T59	161970	0	0	0
T60	0	5	0	0
T65	163560	0	0	0
T66	394384	0	0	0
T67	773422	0	0	0
T158	0	21	0	0
T161	0	10	0	0
T162	0	33	0	0
T163	0	8	0	0
T164	0	36	0	0
T165	0	18	0	0
T166	0	53	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1805	0	0
T2	112945	23	0	0
T3	122507	0	0	0
T4	372918	0	0	0
T5	160321	0	0	0
T6	823140	0	0	0
T7	171380	0	0	0
T8	798312	0	0	0
T9	87099	0	0	0
T10	152159	0	0	0
T14	377313	0	0	0
T21	0	32	0	0
T28	0	20	0	0
T30	0	80	0	0
T60	0	19	0	0
T158	0	19	0	0
T161	0	23	0	0
T162	0	56	0	0
T163	0	53	0	0
T167	0	16	0	0