Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1216591	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1175545

1

T1

937

T2

918

T3

69

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2102304	1			T1	1657		T2	1681		T3	82
values[0x0]	144710	1			T1	109		T2	89		T3	32
values[0x1]	145122	1			T1	112		T2	91		T3	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	978294	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1413842

1

T1

1112

T2

1116

T3

88

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11293	1			T1	3		T2	9		T4	13
valid_sources[0x01]	16071	1			T1	8		T2	4		T3	3
valid_sources[0x02]	11674	1			T1	10		T2	5		T4	23
valid_sources[0x03]	9953	1			T1	6		T2	6		T4	10
valid_sources[0x04]	8047	1			T1	4		T2	7		T4	9
valid_sources[0x05]	6998	1			T1	4		T2	9		T4	7
valid_sources[0x06]	6930	1			T1	12		T2	9		T4	5
valid_sources[0x07]	6924	1			T1	6		T2	2		T4	9
valid_sources[0x08]	6854	1			T1	6		T2	8		T3	4
valid_sources[0x09]	8165	1			T1	8		T2	2		T4	24
valid_sources[0x0a]	7284	1			T1	7		T2	12		T4	7
valid_sources[0x0b]	19490	1			T1	8		T2	9		T4	11
valid_sources[0x0c]	11940	1			T1	1		T2	12		T4	8
valid_sources[0x0d]	11160	1			T1	4		T2	6		T3	1
valid_sources[0x0e]	7315	1			T1	2		T2	4		T4	10
valid_sources[0x0f]	8210	1			T1	8		T2	4		T4	8
valid_sources[0x10]	7140	1			T1	14		T2	7		T3	3
valid_sources[0x11]	12911	1			T1	5		T2	4		T4	11
valid_sources[0x12]	15720	1			T1	10		T2	3		T4	7
valid_sources[0x13]	8471	1			T1	5		T2	7		T4	11
valid_sources[0x14]	6611	1			T1	3		T2	7		T4	13
valid_sources[0x15]	6846	1			T1	4		T2	3		T3	3
valid_sources[0x16]	6651	1			T1	3		T2	6		T3	5
valid_sources[0x17]	11616	1			T1	4		T2	8		T3	2
valid_sources[0x18]	6714	1			T1	8		T2	3		T4	8
valid_sources[0x19]	6715	1			T1	9		T2	8		T4	10
valid_sources[0x1a]	8145	1			T1	7		T2	7		T4	10
valid_sources[0x1b]	15559	1			T1	12		T2	14		T4	7
valid_sources[0x1c]	6678	1			T1	3		T2	6		T4	15
valid_sources[0x1d]	6861	1			T1	9		T2	10		T4	11
valid_sources[0x1e]	12824	1			T1	6		T2	4		T4	14
valid_sources[0x1f]	11734	1			T1	3		T2	7		T4	5
valid_sources[0x20]	13840	1			T1	6		T2	7		T3	4
valid_sources[0x21]	12576	1			T1	5		T2	6		T4	21
valid_sources[0x22]	18174	1			T1	5		T2	6		T4	11
valid_sources[0x23]	13136	1			T1	7		T2	9		T4	5
valid_sources[0x24]	7177	1			T1	6		T2	12		T4	7
valid_sources[0x25]	8873	1			T1	2		T2	6		T3	4
valid_sources[0x26]	11418	1			T1	4		T2	5		T4	15
valid_sources[0x27]	7966	1			T1	8		T2	7		T3	2
valid_sources[0x28]	9081	1			T1	7		T2	6		T4	9
valid_sources[0x29]	7964	1			T1	9		T2	5		T3	1
valid_sources[0x2a]	11475	1			T1	5		T2	8		T4	11
valid_sources[0x2b]	6948	1			T1	11		T2	5		T4	13
valid_sources[0x2c]	6890	1			T1	7		T2	5		T4	17
valid_sources[0x2d]	6956	1			T1	8		T2	7		T4	12
valid_sources[0x2e]	11497	1			T1	10		T2	9		T3	1
valid_sources[0x2f]	6523	1			T1	1		T2	5		T3	1
valid_sources[0x30]	14735	1			T1	4		T2	3		T4	2
valid_sources[0x31]	7935	1			T1	15		T2	8		T4	13
valid_sources[0x32]	7090	1			T1	2		T2	9		T4	10
valid_sources[0x33]	12309	1			T1	6		T2	12		T4	4
valid_sources[0x34]	8254	1			T1	6		T2	8		T4	15
valid_sources[0x35]	7240	1			T1	11		T2	3		T4	11
valid_sources[0x36]	8202	1			T1	16		T2	11		T4	15
valid_sources[0x37]	6852	1			T1	2		T2	7		T4	12
valid_sources[0x38]	7758	1			T1	2		T2	6		T4	20
valid_sources[0x39]	10880	1			T1	7		T2	9		T4	17
valid_sources[0x3a]	7537	1			T1	11		T2	10		T4	21
valid_sources[0x3b]	7600	1			T1	5		T2	4		T4	9
valid_sources[0x3c]	6865	1			T1	4		T2	7		T4	18
valid_sources[0x3d]	12220	1			T1	7		T2	9		T4	7
valid_sources[0x3e]	7260	1			T1	16		T2	6		T4	4
valid_sources[0x3f]	11312	1			T1	5		T2	3		T4	17
valid_sources[0x40]	18366	1			T1	9		T2	4		T4	8
valid_sources[0x41]	7228	1			T2	7		T4	5		T5	11
valid_sources[0x42]	6545	1			T1	9		T2	13		T4	15
valid_sources[0x43]	7131	1			T1	5		T2	6		T3	1
valid_sources[0x44]	6759	1			T1	15		T2	8		T4	13
valid_sources[0x45]	7284	1			T1	8		T2	7		T3	10
valid_sources[0x46]	7688	1			T1	3		T2	4		T4	16
valid_sources[0x47]	6662	1			T1	9		T2	3		T4	14
valid_sources[0x48]	11081	1			T1	6		T2	5		T4	10
valid_sources[0x49]	7867	1			T1	4		T2	10		T4	11
valid_sources[0x4a]	11980	1			T1	5		T2	7		T4	10
valid_sources[0x4b]	7188	1			T1	3		T2	10		T3	2
valid_sources[0x4c]	11261	1			T1	9		T2	5		T4	11
valid_sources[0x4d]	6499	1			T1	4		T2	5		T4	8
valid_sources[0x4e]	11225	1			T1	18		T2	7		T4	12
valid_sources[0x4f]	6870	1			T1	4		T2	3		T4	12
valid_sources[0x50]	7594	1			T1	9		T2	7		T4	10
valid_sources[0x51]	16410	1			T1	4		T2	3		T4	7
valid_sources[0x52]	7591	1			T1	12		T2	7		T4	12
valid_sources[0x53]	7141	1			T1	4		T2	14		T4	10
valid_sources[0x54]	10112	1			T1	2		T2	9		T4	9
valid_sources[0x55]	8265	1			T1	8		T2	6		T3	2
valid_sources[0x56]	10073	1			T1	3		T2	6		T4	4
valid_sources[0x57]	6824	1			T1	16		T2	5		T4	8
valid_sources[0x58]	6787	1			T1	8		T2	6		T4	27
valid_sources[0x59]	14672	1			T1	10		T2	8		T3	2
valid_sources[0x5a]	7865	1			T1	11		T2	6		T4	4
valid_sources[0x5b]	18039	1			T1	9		T2	6		T4	3
valid_sources[0x5c]	12583	1			T1	22		T2	6		T4	7
valid_sources[0x5d]	12837	1			T1	5		T2	6		T4	14
valid_sources[0x5e]	9183	1			T1	2		T2	12		T4	10
valid_sources[0x5f]	12960	1			T1	6		T2	9		T4	8
valid_sources[0x60]	10222	1			T1	2		T2	3		T4	13
valid_sources[0x61]	7690	1			T1	7		T2	5		T4	14
valid_sources[0x62]	7204	1			T1	8		T2	9		T3	3
valid_sources[0x63]	7612	1			T1	8		T2	4		T4	21
valid_sources[0x64]	8007	1			T1	9		T2	10		T4	15
valid_sources[0x65]	6940	1			T1	5		T2	7		T4	9
valid_sources[0x66]	6887	1			T1	9		T2	6		T4	17
valid_sources[0x67]	8056	1			T1	4		T2	6		T4	21
valid_sources[0x68]	7196	1			T1	10		T2	11		T4	27
valid_sources[0x69]	7230	1			T1	4		T2	6		T4	19
valid_sources[0x6a]	9712	1			T1	7		T2	9		T3	2
valid_sources[0x6b]	7091	1			T1	11		T2	6		T4	9
valid_sources[0x6c]	10322	1			T1	18		T2	4		T4	10
valid_sources[0x6d]	13614	1			T1	4		T2	15		T3	1
valid_sources[0x6e]	11048	1			T1	4		T2	13		T4	16
valid_sources[0x6f]	10315	1			T1	10		T2	4		T3	2
valid_sources[0x70]	6906	1			T1	6		T2	7		T4	15
valid_sources[0x71]	9274	1			T1	1		T2	7		T4	18
valid_sources[0x72]	6665	1			T1	21		T2	11		T3	1
valid_sources[0x73]	6935	1			T1	15		T2	5		T4	10
valid_sources[0x74]	9735	1			T1	14		T2	9		T4	12
valid_sources[0x75]	7157	1			T1	5		T2	11		T4	15
valid_sources[0x76]	6839	1			T1	13		T2	11		T4	4
valid_sources[0x77]	7158	1			T1	9		T2	11		T4	5
valid_sources[0x78]	7159	1			T1	5		T2	7		T4	14
valid_sources[0x79]	7929	1			T1	9		T2	4		T3	4
valid_sources[0x7a]	8385	1			T1	4		T2	9		T4	20
valid_sources[0x7b]	10825	1			T1	9		T2	8		T4	5
valid_sources[0x7c]	6917	1			T1	4		T2	7		T3	4
valid_sources[0x7d]	21423	1			T1	4		T2	6		T4	16
valid_sources[0x7e]	11591	1			T1	8		T2	6		T4	12
valid_sources[0x7f]	9108	1			T1	6		T2	6		T4	13
valid_sources[0x80]	7716	1			T1	4		T2	7		T4	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1048063

1

T1

844

T2

841

T3

52

values[0x0]

all_enables

biggest_size

73806

1

T1

53

T2

48

T3

11

values[0x1]

all_enables

biggest_size

53676

1

T1

40

T2

29

T3

6