Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29467	1			T1	19		T2	15		T4	26
auto[PWRUP]	105	1			T8	3		T9	2		T22	1
auto[ONEST_0]	75	1			T8	3		T18	1		T20	1
auto[ONEST_021]	23	1			T223	1		T23	1		T24	1
auto[ONEST_1]	78	1			T9	1		T21	3		T20	2
auto[ONEST_DONE]	4	1			T8	1		T60	1		T72	1
auto[LP_0]	112	1			T8	1		T9	3		T18	2
auto[LP_021]	33	1			T23	2		T24	1		T176	1
auto[LP_1]	115	1			T8	3		T9	1		T20	2
auto[LP_EVAL]	68	1			T21	1		T20	1		T22	1
auto[LP_SLP]	472	1			T8	17		T9	4		T18	2
auto[LP_PWRUP]	27	1			T8	1		T22	1		T16	1
auto[NP_0]	157	1			T8	3		T9	2		T18	1
auto[NP_021]	27	1			T8	1		T9	1		T18	1
auto[NP_1]	140	1			T8	4		T9	2		T18	2
auto[NP_EVAL]	33	1			T9	1		T20	1		T22	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T22

1

T223

1

T224

2

min

28976

1

T1

19

T2

15

T4

26

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28985	1			T1	19		T2	15		T4	26
pow[0x1]	8	1			T8	1		T25	1		T225	1
pow[0x2]	18	1			T21	1		T23	1		T226	1
pow[0x3]	28	1			T223	1		T23	1		T24	1
pow[0x4]	61	1			T9	1		T20	1		T22	1
pow[0x5]	116	1			T8	2		T9	2		T20	1
pow[0x6]	265	1			T8	2		T9	3		T18	2
pow[0x7]	484	1			T8	7		T9	11		T18	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

183

1

T8

2

T9

5

T20

3

min

28547

1

T1

19

T2

15

T4

26

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28547	1			T1	19		T2	15		T4	26
pow[0x6]	1	1			T60	1		-	-		-	-
pow[0x7]	5	1			T21	1		T226	1		T225	1
pow[0x8]	6	1			T20	1		T81	1		T72	1
pow[0x9]	9	1			T176	1		T227	1		T71	1
pow[0xa]	13	1			T22	1		T16	1		T23	1
pow[0xb]	34	1			T8	3		T22	1		T223	1
pow[0xc]	60	1			T8	1		T22	1		T16	1
pow[0xd]	148	1			T8	1		T9	1		T18	1
pow[0xe]	272	1			T8	7		T9	2		T18	2
pow[0xf]	554	1			T8	12		T9	12		T18	5