Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2223	1			T8	20		T9	12		T18	18
auto[PWRUP]	130	1			T8	3		T9	2		T21	1
auto[ONEST_0]	78	1			T8	2		T9	2		T21	2
auto[ONEST_021]	13	1			T8	1		T9	2		T21	1
auto[ONEST_1]	85	1			T9	1		T21	1		T20	2
auto[ONEST_DONE]	4	1			T362	1		T57	1		T75	1
auto[LP_0]	141	1			T9	3		T18	2		T20	5
auto[LP_021]	35	1			T9	1		T22	1		T24	1
auto[LP_1]	137	1			T8	1		T9	3		T18	1
auto[LP_EVAL]	61	1			T18	1		T22	1		T16	1
auto[LP_SLP]	492	1			T8	4		T9	5		T18	2
auto[LP_PWRUP]	24	1			T20	1		T226	2		T363	1
auto[NP_0]	209	1			T8	5		T9	3		T18	1
auto[NP_021]	47	1			T20	1		T24	1		T364	1
auto[NP_1]	227	1			T8	4		T9	1		T18	2
auto[NP_EVAL]	39	1			T18	1		T205	2		T246	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T23

1

T196

1

T270

1

min

2000

1

T8

5

T9

5

T18

20

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2009	1			T8	5		T9	5		T18	20
pow[0x1]	9	1			T365	1		T225	1		T366	1
pow[0x2]	22	1			T20	1		T223	1		T26	1
pow[0x3]	34	1			T9	1		T223	2		T23	1
pow[0x4]	66	1			T8	1		T9	1		T18	1
pow[0x5]	117	1			T9	3		T18	1		T21	3
pow[0x6]	248	1			T8	4		T9	6		T18	1
pow[0x7]	493	1			T8	12		T9	5		T18	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

181

1

T8

2

T9

1

T18

1

min

1374

1

T8

5

T9

3

T18

14

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1375	1			T8	5		T9	3		T18	14
pow[0x1]	21	1			T18	1		T15	1		T205	3
pow[0x2]	24	1			T246	1		T54	2		T270	3
pow[0x3]	48	1			T16	1		T26	2		T246	1
pow[0x4]	71	1			T18	2		T16	2		T26	2
pow[0x5]	1	1			T364	1		-	-		-	-
pow[0x6]	3	1			T367	1		T368	1		T369	1
pow[0x7]	1	1			T370	1		-	-		-	-
pow[0x8]	3	1			T223	1		T363	1		T371	1
pow[0x9]	11	1			T196	1		T54	1		T72	1
pow[0xa]	23	1			T22	1		T364	1		T25	2
pow[0xb]	26	1			T9	1		T223	1		T23	1
pow[0xc]	59	1			T9	2		T21	1		T22	3
pow[0xd]	163	1			T8	2		T9	2		T18	1
pow[0xe]	259	1			T8	3		T9	1		T21	3
pow[0xf]	568	1			T8	11		T9	4		T18	1