Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.70	99.67	98.31		100.00	95.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	97.92	100.00	96.84		100.00	92.77	100.00
u_adc_ctrl_intr	95.01	98.67	84.62			96.77	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		61	61	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	199	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	8	8
59	8	8
68	1	1
69	1	1
70	1	1
71	1	1
79	1	1
82	1	1
83	1	1
84	1	1
85	1	1
100	8	8
103	8	8
113	8	8
117	8	8
133	1	1
134	1	1
138	1	1
199	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	284	284	100.00
Logical	284	284	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T8,T9

 LINE       79
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T7
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T4,T7

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T4

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T7
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T4,T7

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T7
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T2,T4,T5

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T4

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T2,T4,T5

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T2,T4,T5

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T1,T4,T5

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T1,T4,T5

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T1,T4,T5

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T4

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       117
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       117
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       117
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       117
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       117
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T4,T5

 LINE       117
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T4,T5

 LINE       117
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T4,T5

 LINE       117
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	79	3	3	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	79	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T8,T9
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	32797177	32497203	0	0
gen_filter_match[0].MatchCheck00_A	32797177	9529352	0	0
gen_filter_match[0].MatchCheck01_A	32797177	2507708	0	0
gen_filter_match[0].MatchCheck10_A	32797177	2721819	0	0
gen_filter_match[0].MatchCheck11_A	32797177	17738324	0	0
gen_filter_match[1].MatchCheck00_A	32797177	11163984	0	0
gen_filter_match[1].MatchCheck01_A	32797177	1216642	0	0
gen_filter_match[1].MatchCheck10_A	32797177	1064004	0	0
gen_filter_match[1].MatchCheck11_A	32797177	19052573	0	0
gen_filter_match[2].MatchCheck00_A	32797177	11737724	0	0
gen_filter_match[2].MatchCheck01_A	32797177	402760	0	0
gen_filter_match[2].MatchCheck10_A	32797177	630193	0	0
gen_filter_match[2].MatchCheck11_A	32797177	19726526	0	0
gen_filter_match[3].MatchCheck00_A	32797177	11710269	0	0
gen_filter_match[3].MatchCheck01_A	32797177	487506	0	0
gen_filter_match[3].MatchCheck10_A	32797177	367637	0	0
gen_filter_match[3].MatchCheck11_A	32797177	19931791	0	0
gen_filter_match[4].MatchCheck00_A	32797177	11809941	0	0
gen_filter_match[4].MatchCheck01_A	32797177	32540	0	0
gen_filter_match[4].MatchCheck10_A	32797177	32379	0	0
gen_filter_match[4].MatchCheck11_A	32797177	20622343	0	0
gen_filter_match[5].MatchCheck00_A	32797177	12954363	0	0
gen_filter_match[5].MatchCheck01_A	32797177	9	0	0
gen_filter_match[5].MatchCheck10_A	32797177	72567	0	0
gen_filter_match[5].MatchCheck11_A	32797177	19470264	0	0
gen_filter_match[6].MatchCheck00_A	32797177	12452508	0	0
gen_filter_match[6].MatchCheck01_A	32797177	13	0	0
gen_filter_match[6].MatchCheck10_A	32797177	63989	0	0
gen_filter_match[6].MatchCheck11_A	32797177	19980693	0	0
gen_filter_match[7].MatchCheck00_A	32797177	11852222	0	0
gen_filter_match[7].MatchCheck01_A	32797177	107074	0	0
gen_filter_match[7].MatchCheck10_A	32797177	167408	0	0
gen_filter_match[7].MatchCheck11_A	32797177	20370499	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	32497203	0	0
T1	65163	65085	0	0
T2	65534	65448	0	0
T3	1175	1086	0	0
T4	102119	102048	0	0
T5	98902	98807	0	0
T6	7933	7852	0	0
T7	100513	100425	0	0
T8	25929	23008	0	0
T9	19967	17274	0	0
T14	86	5	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	9529352	0	0
T1	65163	65085	0	0
T2	65534	32636	0	0
T3	1175	1086	0	0
T4	102119	68701	0	0
T5	98902	3	0	0
T6	7933	7852	0	0
T7	100513	66759	0	0
T8	25929	22854	0	0
T9	19967	16971	0	0
T14	86	5	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	2507708	0	0
T12	97597	31860	0	0
T13	65153	0	0	0
T17	98755	0	0	0
T18	14950	0	0	0
T19	66354	0	0	0
T21	17817	0	0	0
T54	0	2281	0	0
T86	65521	0	0	0
T87	98793	0	0	0
T119	864	0	0	0
T121	0	33395	0	0
T122	0	32411	0	0
T123	0	33302	0	0
T124	0	32550	0	0
T125	0	33903	0	0
T126	0	31867	0	0
T127	0	31942	0	0
T128	0	32328	0	0
T129	33404	0	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	2721819	0	0
T11	105930	40679	0	0
T12	97597	0	0	0
T13	65153	0	0	0
T15	0	12920	0	0
T17	98755	0	0	0
T18	14950	0	0	0
T21	17817	0	0	0
T24	0	1	0	0
T32	0	65159	0	0
T86	65521	0	0	0
T87	98793	0	0	0
T119	864	0	0	0
T129	33404	0	0	0
T130	0	32633	0	0
T131	0	4	0	0
T132	0	32691	0	0
T133	0	32997	0	0
T134	0	33379	0	0
T135	0	1	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	17738324	0	0
T2	65534	32812	0	0
T3	1175	0	0	0
T4	102119	33347	0	0
T5	98902	98804	0	0
T6	7933	0	0	0
T7	100513	33666	0	0
T8	25929	154	0	0
T9	19967	303	0	0
T10	66075	33071	0	0
T12	0	32509	0	0
T13	0	33455	0	0
T14	86	0	0	0
T17	0	65835	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	11163984	0	0
T1	65163	3	0	0
T2	65534	3	0	0
T3	1175	1086	0	0
T4	102119	68948	0	0
T5	98902	3	0	0
T6	7933	7852	0	0
T7	100513	66483	0	0
T8	25929	23008	0	0
T9	19967	17274	0	0
T14	86	5	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	1216642	0	0
T16	0	18546	0	0
T22	24903	0	0	0
T46	0	65945	0	0
T126	0	1	0	0
T128	0	32529	0	0
T136	32958	32858	0	0
T137	0	32340	0	0
T138	0	33241	0	0
T139	0	33200	0	0
T140	0	33228	0	0
T141	0	33053	0	0
T142	32416	0	0	0
T143	996	0	0	0
T144	1191	0	0	0
T145	66652	0	0	0
T146	7225	0	0	0
T147	33819	0	0	0
T148	32760	0	0	0
T149	1173	0	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	1064004	0	0
T12	97597	1	0	0
T13	65153	0	0	0
T17	98755	0	0	0
T18	14950	0	0	0
T19	66354	0	0	0
T20	0	33191	0	0
T21	17817	0	0	0
T24	0	1	0	0
T86	65521	0	0	0
T87	98793	0	0	0
T119	864	0	0	0
T122	0	33390	0	0
T129	33404	0	0	0
T131	0	3	0	0
T135	0	2	0	0
T150	0	1	0	0
T151	0	32570	0	0
T152	0	1	0	0
T153	0	1	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	19052573	0	0
T1	65163	65082	0	0
T2	65534	65445	0	0
T3	1175	0	0	0
T4	102119	33100	0	0
T5	98902	98804	0	0
T6	7933	0	0	0
T7	100513	33942	0	0
T8	25929	0	0	0
T9	19967	0	0	0
T10	0	32946	0	0
T12	0	64368	0	0
T13	0	65058	0	0
T14	86	0	0	0
T17	0	64862	0	0
T86	0	65447	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	11737724	0	0
T1	65163	65085	0	0
T2	65534	32636	0	0
T3	1175	1086	0	0
T4	102119	33350	0	0
T5	98902	3	0	0
T6	7933	7852	0	0
T7	100513	67611	0	0
T8	25929	23008	0	0
T9	19967	17274	0	0
T14	86	5	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	402760	0	0
T16	33399	7938	0	0
T23	25573	0	0	0
T24	80324	0	0	0
T32	97993	0	0	0
T37	83	0	0	0
T126	0	1	0	0
T154	0	33122	0	0
T155	0	33118	0	0
T156	0	2	0	0
T157	0	33058	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	33188	0	0
T161	0	32280	0	0
T162	65848	0	0	0
T163	98280	0	0	0
T164	5936	0	0	0
T165	32753	0	0	0
T166	1155	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	630193	0	0
T4	102119	33100	0	0
T5	98902	0	0	0
T6	7933	0	0	0
T7	100513	0	0	0
T8	25929	0	0	0
T9	19967	0	0	0
T10	66075	0	0	0
T11	105930	0	0	0
T14	86	0	0	0
T68	1187	0	0	0
T131	0	31982	0	0
T135	0	2	0	0
T150	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	32760	0	0
T170	0	2	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	19726526	0	0
T2	65534	32812	0	0
T3	1175	0	0	0
T4	102119	35598	0	0
T5	98902	98804	0	0
T6	7933	0	0	0
T7	100513	32814	0	0
T8	25929	0	0	0
T9	19967	0	0	0
T10	66075	32946	0	0
T11	0	33178	0	0
T13	0	33455	0	0
T14	86	0	0	0
T17	0	33796	0	0
T18	0	2602	0	0
T129	0	33306	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	11710269	0	0
T1	65163	65085	0	0
T2	65534	3	0	0
T3	1175	1086	0	0
T4	102119	66450	0	0
T5	98902	3	0	0
T6	7933	7852	0	0
T7	100513	33945	0	0
T8	25929	23008	0	0
T9	19967	17274	0	0
T14	86	5	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	487506	0	0
T24	80324	31927	0	0
T37	83	0	0	0
T38	80	0	0	0
T45	0	33417	0	0
T79	0	1	0	0
T126	0	1	0	0
T132	65426	0	0	0
T156	0	2	0	0
T157	0	1	0	0
T165	32753	0	0	0
T166	1155	0	0	0
T167	98902	0	0	0
T171	0	33208	0	0
T172	0	2	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	38205	0	0	0
T176	37971	0	0	0
T177	1192	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	367637	0	0
T11	105930	33178	0	0
T12	97597	1	0	0
T13	65153	0	0	0
T17	98755	32039	0	0
T18	14950	0	0	0
T21	17817	0	0	0
T24	0	1	0	0
T26	0	5	0	0
T86	65521	0	0	0
T87	98793	0	0	0
T119	864	0	0	0
T129	33404	0	0	0
T131	0	3	0	0
T135	0	2	0	0
T150	0	1	0	0
T167	0	1	0	0
T178	0	33485	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	19931791	0	0
T2	65534	65445	0	0
T3	1175	0	0	0
T4	102119	35598	0	0
T5	98902	98804	0	0
T6	7933	0	0	0
T7	100513	66480	0	0
T8	25929	0	0	0
T9	19967	0	0	0
T10	66075	32946	0	0
T12	0	64368	0	0
T13	0	65058	0	0
T14	86	0	0	0
T18	0	994	0	0
T86	0	65447	0	0
T129	0	33306	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	11809941	0	0
T1	65163	32809	0	0
T2	65534	65448	0	0
T3	1175	1086	0	0
T4	102119	33350	0	0
T5	98902	3	0	0
T6	7933	7852	0	0
T7	100513	66483	0	0
T8	25929	23008	0	0
T9	19967	17274	0	0
T14	86	5	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	32540	0	0
T82	65531	1	0	0
T83	897	0	0	0
T84	24938	0	0	0
T156	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T174	0	1	0	0
T179	99192	1	0	0
T180	0	32531	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	913	0	0	0
T185	5958	0	0	0
T186	32049	0	0	0
T187	32756	0	0	0
T188	1125	0	0	0
T189	32949	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	32379	0	0
T22	24903	0	0	0
T24	0	1	0	0
T26	0	5	0	0
T131	32075	3	0	0
T135	0	1	0	0
T136	32958	0	0	0
T142	32416	0	0	0
T143	996	0	0	0
T144	1191	0	0	0
T145	66652	0	0	0
T146	7225	0	0	0
T147	33819	0	0	0
T148	32760	0	0	0
T150	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T170	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	20622343	0	0
T1	65163	32276	0	0
T2	65534	0	0	0
T3	1175	0	0	0
T4	102119	68698	0	0
T5	98902	98804	0	0
T6	7933	0	0	0
T7	100513	33942	0	0
T8	25929	0	0	0
T9	19967	0	0	0
T10	0	66017	0	0
T11	0	105827	0	0
T13	0	33455	0	0
T14	86	0	0	0
T17	0	64862	0	0
T18	0	3596	0	0
T129	0	33306	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	12954363	0	0
T1	65163	3	0	0
T2	65534	65448	0	0
T3	1175	1086	0	0
T4	102119	68948	0	0
T5	98902	3	0	0
T6	7933	7852	0	0
T7	100513	67611	0	0
T8	25929	23008	0	0
T9	19967	17274	0	0
T14	86	5	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	9	0	0
T12	97597	1	0	0
T13	65153	0	0	0
T17	98755	0	0	0
T18	14950	0	0	0
T19	66354	0	0	0
T21	17817	0	0	0
T86	65521	0	0	0
T87	98793	0	0	0
T119	864	0	0	0
T129	33404	0	0	0
T156	0	1	0	0
T159	0	1	0	0
T169	0	1	0	0
T173	0	1	0	0
T179	0	1	0	0
T183	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	72567	0	0
T12	97597	1	0	0
T13	65153	0	0	0
T17	98755	0	0	0
T18	14950	2602	0	0
T19	66354	0	0	0
T21	17817	0	0	0
T26	0	5	0	0
T86	65521	0	0	0
T87	98793	0	0	0
T119	864	0	0	0
T129	33404	0	0	0
T135	0	2	0	0
T150	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	19470264	0	0
T1	65163	65082	0	0
T2	65534	0	0	0
T3	1175	0	0	0
T4	102119	33100	0	0
T5	98902	98804	0	0
T6	7933	0	0	0
T7	100513	32814	0	0
T8	25929	0	0	0
T9	19967	0	0	0
T10	0	32946	0	0
T11	0	33178	0	0
T12	0	65674	0	0
T14	86	0	0	0
T17	0	98658	0	0
T18	0	994	0	0
T129	0	33306	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	12452508	0	0
T1	65163	32809	0	0
T2	65534	65448	0	0
T3	1175	1086	0	0
T4	102119	35601	0	0
T5	98902	3	0	0
T6	7933	7852	0	0
T7	100513	100425	0	0
T8	25929	23008	0	0
T9	19967	17274	0	0
T14	86	5	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	13	0	0
T126	96369	1	0	0
T127	96370	0	0	0
T156	0	2	0	0
T158	0	1	0	0
T159	0	2	0	0
T173	0	1	0	0
T174	0	1	0	0
T181	0	1	0	0
T190	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T194	33916	0	0	0
T195	93	0	0	0
T196	23929	0	0	0
T197	97895	0	0	0
T198	979	0	0	0
T199	32441	0	0	0
T200	97718	0	0	0
T201	97	0	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	63989	0	0
T12	97597	1	0	0
T13	65153	0	0	0
T17	98755	0	0	0
T18	14950	0	0	0
T19	66354	0	0	0
T21	17817	0	0	0
T26	0	5	0	0
T86	65521	0	0	0
T87	98793	0	0	0
T119	864	0	0	0
T126	0	2	0	0
T129	33404	0	0	0
T135	0	2	0	0
T150	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T167	0	1	0	0
T169	0	1	0	0
T170	0	2	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	19980693	0	0
T1	65163	32276	0	0
T2	65534	0	0	0
T3	1175	0	0	0
T4	102119	66447	0	0
T5	98902	98804	0	0
T6	7933	0	0	0
T7	100513	0	0	0
T8	25929	0	0	0
T9	19967	0	0	0
T10	0	33071	0	0
T11	0	105827	0	0
T12	0	64368	0	0
T13	0	33455	0	0
T14	86	0	0	0
T17	0	98658	0	0
T86	0	65447	0	0
T87	0	98694	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	11852222	0	0
T1	65163	3	0	0
T2	65534	32815	0	0
T3	1175	1086	0	0
T4	102119	3	0	0
T5	98902	3	0	0
T6	7933	7852	0	0
T7	100513	66483	0	0
T8	25929	23008	0	0
T9	19967	17274	0	0
T14	86	5	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	107074	0	0
T7	100513	33942	0	0
T8	25929	0	0	0
T9	19967	0	0	0
T10	66075	0	0	0
T11	105930	0	0	0
T12	97597	1	0	0
T13	65153	0	0	0
T17	98755	0	0	0
T18	14950	0	0	0
T68	1187	0	0	0
T126	0	1	0	0
T130	0	32867	0	0
T179	0	1	0	0
T180	0	1	0	0
T190	0	1	0	0
T192	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	167408	0	0
T12	97597	1	0	0
T13	65153	0	0	0
T17	98755	0	0	0
T18	14950	0	0	0
T19	66354	0	0	0
T21	17817	0	0	0
T24	0	1	0	0
T26	0	5	0	0
T86	65521	0	0	0
T87	98793	0	0	0
T119	864	0	0	0
T129	33404	0	0	0
T135	0	2	0	0
T150	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T162	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32797177	20370499	0	0
T1	65163	65082	0	0
T2	65534	32633	0	0
T3	1175	0	0	0
T4	102119	102045	0	0
T5	98902	98804	0	0
T6	7933	0	0	0
T7	100513	0	0	0
T8	25929	0	0	0
T9	19967	0	0	0
T11	0	65148	0	0
T12	0	33165	0	0
T13	0	33455	0	0
T14	86	0	0	0
T17	0	32039	0	0
T18	0	994	0	0
T86	0	65447	0	0