Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	6515	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2627	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2645	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2640	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2564	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2396	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2709	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2538	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2676	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2661	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2459	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2582	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2541	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2590	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2770	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2606	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2630	0	0
adc_en_ctl_rd_A	2147483647	2203	0	0
adc_fsm_rst_rd_A	2147483647	2033	0	0
adc_intr_ctl_rd_A	2147483647	2218	0	0
adc_lp_sample_ctl_rd_A	2147483647	1954	0	0
adc_pd_ctl_rd_A	2147483647	2515	0	0
adc_sample_ctl_rd_A	2147483647	2125	0	0
adc_wakeup_ctl_rd_A	2147483647	2012	0	0
intr_enable_rd_A	2147483647	2559	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6515	0	0
T15	726981	1	0	0
T47	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	3	0	0
T73	0	1	0	0
T131	801927	0	0	0
T136	193097	0	0	0
T142	155597	0	0	0
T143	483748	0	0	0
T178	257548	0	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	120616	0	0	0
T208	165606	0	0	0
T209	244222	0	0	0
T210	150043	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2627	0	0
T18	667888	30	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	30	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	8	0	0
T212	0	20	0	0
T213	0	15	0	0
T214	0	18	0	0
T215	0	35	0	0
T216	0	51	0	0
T217	0	16	0	0
T218	0	9	0	0
T219	111236	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2645	0	0
T18	667888	42	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	42	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	9	0	0
T212	0	6	0	0
T213	0	20	0	0
T214	0	37	0	0
T215	0	26	0	0
T216	0	22	0	0
T217	0	26	0	0
T218	0	5	0	0
T219	111236	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2640	0	0
T18	667888	34	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	32	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	3	0	0
T212	0	17	0	0
T213	0	10	0	0
T214	0	16	0	0
T215	0	43	0	0
T216	0	43	0	0
T217	0	17	0	0
T218	0	5	0	0
T219	111236	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2564	0	0
T18	667888	41	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	35	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	7	0	0
T212	0	21	0	0
T213	0	14	0	0
T214	0	20	0	0
T215	0	33	0	0
T216	0	34	0	0
T217	0	22	0	0
T218	0	10	0	0
T219	111236	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2396	0	0
T18	667888	47	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	34	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	7	0	0
T212	0	12	0	0
T213	0	18	0	0
T214	0	19	0	0
T215	0	34	0	0
T216	0	39	0	0
T217	0	20	0	0
T218	0	13	0	0
T219	111236	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2709	0	0
T18	667888	26	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	38	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	8	0	0
T212	0	20	0	0
T213	0	21	0	0
T214	0	31	0	0
T215	0	37	0	0
T216	0	37	0	0
T217	0	27	0	0
T218	0	12	0	0
T219	111236	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2538	0	0
T18	667888	44	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	38	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	10	0	0
T212	0	29	0	0
T213	0	11	0	0
T214	0	30	0	0
T215	0	46	0	0
T216	0	37	0	0
T217	0	22	0	0
T218	0	12	0	0
T219	111236	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2676	0	0
T18	667888	39	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	31	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	7	0	0
T212	0	19	0	0
T213	0	19	0	0
T214	0	11	0	0
T215	0	29	0	0
T216	0	27	0	0
T217	0	25	0	0
T218	0	13	0	0
T219	111236	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2661	0	0
T18	667888	51	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	37	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	4	0	0
T212	0	17	0	0
T213	0	13	0	0
T214	0	25	0	0
T215	0	33	0	0
T216	0	43	0	0
T217	0	28	0	0
T218	0	16	0	0
T219	111236	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2459	0	0
T18	667888	28	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	41	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	19	0	0
T212	0	21	0	0
T213	0	17	0	0
T214	0	18	0	0
T215	0	32	0	0
T216	0	24	0	0
T217	0	16	0	0
T218	0	4	0	0
T219	111236	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2582	0	0
T18	667888	50	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	31	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	8	0	0
T212	0	17	0	0
T213	0	12	0	0
T214	0	13	0	0
T215	0	42	0	0
T216	0	33	0	0
T217	0	17	0	0
T218	0	16	0	0
T219	111236	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2541	0	0
T18	667888	38	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	35	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	1	0	0
T212	0	10	0	0
T213	0	16	0	0
T214	0	7	0	0
T215	0	49	0	0
T216	0	32	0	0
T217	0	17	0	0
T218	0	20	0	0
T219	111236	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2590	0	0
T18	667888	30	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	34	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	9	0	0
T212	0	16	0	0
T213	0	25	0	0
T214	0	16	0	0
T215	0	30	0	0
T216	0	34	0	0
T217	0	21	0	0
T218	0	13	0	0
T219	111236	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2770	0	0
T18	667888	42	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	34	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	13	0	0
T212	0	18	0	0
T213	0	20	0	0
T214	0	16	0	0
T215	0	42	0	0
T216	0	22	0	0
T217	0	20	0	0
T218	0	3	0	0
T219	111236	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2606	0	0
T18	667888	45	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	38	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	12	0	0
T212	0	22	0	0
T213	0	13	0	0
T214	0	23	0	0
T215	0	27	0	0
T216	0	39	0	0
T217	0	29	0	0
T218	0	10	0	0
T219	111236	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2630	0	0
T18	667888	34	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	41	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	1	0	0
T212	0	22	0	0
T213	0	11	0	0
T214	0	19	0	0
T215	0	35	0	0
T216	0	43	0	0
T217	0	19	0	0
T218	0	12	0	0
T219	111236	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2203	0	0
T18	667888	28	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	38	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	4	0	0
T212	0	13	0	0
T213	0	9	0	0
T214	0	28	0	0
T215	0	26	0	0
T216	0	24	0	0
T217	0	22	0	0
T218	0	17	0	0
T219	111236	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2033	0	0
T18	667888	33	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	42	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	13	0	0
T212	0	4	0	0
T213	0	11	0	0
T214	0	16	0	0
T215	0	47	0	0
T216	0	53	0	0
T217	0	19	0	0
T218	0	13	0	0
T219	111236	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2218	0	0
T18	667888	28	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	35	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	17	0	0
T212	0	27	0	0
T213	0	11	0	0
T214	0	18	0	0
T215	0	56	0	0
T216	0	32	0	0
T217	0	5	0	0
T218	0	7	0	0
T219	111236	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1954	0	0
T18	667888	31	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	38	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T212	0	21	0	0
T213	0	14	0	0
T214	0	15	0	0
T215	0	27	0	0
T216	0	26	0	0
T217	0	16	0	0
T218	0	3	0	0
T219	111236	0	0	0
T220	0	27	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2515	0	0
T18	667888	29	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	45	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	12	0	0
T212	0	23	0	0
T213	0	10	0	0
T214	0	13	0	0
T215	0	40	0	0
T216	0	35	0	0
T217	0	25	0	0
T218	0	23	0	0
T219	111236	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2125	0	0
T18	667888	38	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	22	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	12	0	0
T212	0	12	0	0
T213	0	27	0	0
T214	0	28	0	0
T215	0	40	0	0
T216	0	31	0	0
T217	0	24	0	0
T218	0	8	0	0
T219	111236	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2012	0	0
T18	667888	34	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	52	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	0	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	19	0	0
T212	0	18	0	0
T213	0	17	0	0
T214	0	18	0	0
T215	0	27	0	0
T216	0	31	0	0
T217	0	14	0	0
T218	0	8	0	0
T219	111236	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2559	0	0
T18	667888	36	0	0
T19	136029	0	0	0
T20	272460	0	0	0
T21	890952	0	0	0
T26	0	48	0	0
T86	317790	0	0	0
T87	543367	0	0	0
T112	132374	10	0	0
T119	47598	0	0	0
T129	160338	0	0	0
T211	0	7	0	0
T212	0	20	0	0
T213	0	53	0	0
T214	0	30	0	0
T215	0	30	0	0
T219	111236	0	0	0
T221	0	12	0	0
T222	0	22	0	0