Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1199880	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1154346

1

T1

1355

T2

55

T3

2112

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2062513	1			T1	2508		T2	82		T3	4084
values[0x0]	145232	1			T1	162		T2	31		T3	133
values[0x1]	146481	1			T1	138		T2	33		T3	133

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	966254	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1387972

1

T1

1632

T2

68

T3

2565

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11099	1			T1	3		T3	17		T4	22
valid_sources[0x01]	7894	1			T1	6		T3	14		T4	17
valid_sources[0x02]	11615	1			T1	14		T3	19		T4	21
valid_sources[0x03]	6474	1			T1	1		T3	15		T4	13
valid_sources[0x04]	7553	1			T1	936		T3	10		T4	19
valid_sources[0x05]	6836	1			T1	1		T2	4		T3	26
valid_sources[0x06]	12845	1			T1	6		T3	21		T4	37
valid_sources[0x07]	11031	1			T1	2		T2	1		T3	12
valid_sources[0x08]	6354	1			T1	6		T3	15		T4	16
valid_sources[0x09]	11544	1			T1	6		T3	20		T4	15
valid_sources[0x0a]	8156	1			T1	7		T2	6		T3	14
valid_sources[0x0b]	6954	1			T1	12		T3	16		T4	21
valid_sources[0x0c]	7029	1			T1	13		T3	18		T4	32
valid_sources[0x0d]	6812	1			T1	1		T3	16		T4	42
valid_sources[0x0e]	8341	1			T1	6		T3	18		T4	12
valid_sources[0x0f]	6392	1			T1	2		T3	22		T4	120
valid_sources[0x10]	7670	1			T1	8		T3	13		T4	16
valid_sources[0x11]	6608	1			T1	3		T3	14		T4	17
valid_sources[0x12]	6803	1			T1	4		T3	16		T4	59
valid_sources[0x13]	6782	1			T1	7		T3	15		T4	41
valid_sources[0x14]	6680	1			T1	5		T3	20		T4	35
valid_sources[0x15]	7338	1			T1	14		T3	14		T4	16
valid_sources[0x16]	7691	1			T1	1		T3	20		T4	14
valid_sources[0x17]	15352	1			T1	15		T3	13		T4	18
valid_sources[0x18]	6756	1			T1	3		T3	19		T4	18
valid_sources[0x19]	7033	1			T1	7		T3	18		T4	55
valid_sources[0x1a]	6618	1			T1	4		T2	13		T3	18
valid_sources[0x1b]	7672	1			T1	5		T3	18		T4	22
valid_sources[0x1c]	11678	1			T1	6		T2	3		T3	7
valid_sources[0x1d]	12302	1			T3	17		T4	10		T5	11
valid_sources[0x1e]	8426	1			T1	1		T3	12		T4	18
valid_sources[0x1f]	6459	1			T1	5		T3	17		T4	16
valid_sources[0x20]	7628	1			T1	6		T3	16		T4	22
valid_sources[0x21]	13329	1			T1	18		T3	15		T4	16
valid_sources[0x22]	11062	1			T1	3		T3	16		T4	76
valid_sources[0x23]	6750	1			T1	7		T3	18		T4	18
valid_sources[0x24]	7143	1			T1	13		T2	10		T3	17
valid_sources[0x25]	9196	1			T1	1		T2	5		T3	12
valid_sources[0x26]	6844	1			T1	8		T3	14		T4	22
valid_sources[0x27]	7312	1			T1	7		T3	19		T4	38
valid_sources[0x28]	6970	1			T1	5		T3	20		T4	17
valid_sources[0x29]	6651	1			T1	13		T3	19		T4	49
valid_sources[0x2a]	9504	1			T1	4		T3	26		T4	17
valid_sources[0x2b]	6704	1			T1	2		T3	19		T4	90
valid_sources[0x2c]	6522	1			T1	12		T3	21		T4	25
valid_sources[0x2d]	6930	1			T1	13		T3	14		T4	18
valid_sources[0x2e]	6549	1			T1	8		T3	21		T4	59
valid_sources[0x2f]	7159	1			T1	7		T3	9		T4	48
valid_sources[0x30]	19553	1			T1	2		T3	16		T4	15
valid_sources[0x31]	7825	1			T1	2		T3	17		T4	60
valid_sources[0x32]	7067	1			T1	24		T3	14		T4	15
valid_sources[0x33]	8032	1			T1	3		T3	15		T4	12
valid_sources[0x34]	7401	1			T1	5		T3	15		T4	90
valid_sources[0x35]	6651	1			T1	8		T3	17		T4	11
valid_sources[0x36]	6741	1			T1	14		T3	17		T4	16
valid_sources[0x37]	10575	1			T1	12		T3	16		T4	23
valid_sources[0x38]	12320	1			T1	6		T2	3		T3	15
valid_sources[0x39]	15525	1			T1	4		T3	24		T4	4412
valid_sources[0x3a]	7120	1			T1	1		T3	13		T4	18
valid_sources[0x3b]	13537	1			T1	9		T3	15		T4	104
valid_sources[0x3c]	10212	1			T1	1		T3	15		T4	24
valid_sources[0x3d]	6992	1			T1	2		T3	24		T4	114
valid_sources[0x3e]	11002	1			T1	2		T3	20		T4	25
valid_sources[0x3f]	6510	1			T1	8		T3	13		T4	16
valid_sources[0x40]	6727	1			T1	14		T3	25		T4	19
valid_sources[0x41]	7701	1			T1	5		T3	16		T4	10
valid_sources[0x42]	10268	1			T1	5		T3	22		T4	16
valid_sources[0x43]	6838	1			T1	3		T3	14		T4	78
valid_sources[0x44]	6396	1			T1	1		T3	22		T4	14
valid_sources[0x45]	8363	1			T1	5		T2	17		T3	20
valid_sources[0x46]	11863	1			T1	2		T3	11		T4	9
valid_sources[0x47]	6414	1			T1	7		T3	17		T4	36
valid_sources[0x48]	8746	1			T1	14		T3	17		T4	12
valid_sources[0x49]	9499	1			T1	4		T3	16		T4	48
valid_sources[0x4a]	6739	1			T1	9		T2	2		T3	23
valid_sources[0x4b]	6796	1			T1	2		T3	13		T4	16
valid_sources[0x4c]	6875	1			T1	9		T3	21		T4	19
valid_sources[0x4d]	11258	1			T1	7		T3	13		T4	16
valid_sources[0x4e]	7045	1			T1	2		T3	17		T4	18
valid_sources[0x4f]	7870	1			T1	21		T3	22		T4	14
valid_sources[0x50]	8263	1			T1	10		T3	19		T4	18
valid_sources[0x51]	8011	1			T1	2		T3	22		T4	54
valid_sources[0x52]	11823	1			T1	2		T3	18		T4	19
valid_sources[0x53]	10403	1			T1	7		T3	8		T4	16
valid_sources[0x54]	12579	1			T1	8		T3	12		T4	53
valid_sources[0x55]	19530	1			T1	8		T3	23		T4	31
valid_sources[0x56]	11080	1			T1	11		T3	18		T4	24
valid_sources[0x57]	6259	1			T1	2		T3	15		T4	61
valid_sources[0x58]	9531	1			T3	23		T4	17		T5	17
valid_sources[0x59]	7302	1			T1	6		T3	20		T4	15
valid_sources[0x5a]	6858	1			T1	1		T3	11		T4	42
valid_sources[0x5b]	24181	1			T1	5		T3	20		T4	22
valid_sources[0x5c]	6268	1			T1	5		T3	7		T4	10
valid_sources[0x5d]	7201	1			T1	6		T3	15		T4	22
valid_sources[0x5e]	6520	1			T1	4		T3	22		T4	45
valid_sources[0x5f]	7582	1			T1	7		T3	17		T4	15
valid_sources[0x60]	8971	1			T1	4		T3	17		T4	19
valid_sources[0x61]	8402	1			T1	5		T3	10		T4	12
valid_sources[0x62]	7943	1			T1	1		T3	11		T4	66
valid_sources[0x63]	6881	1			T3	22		T4	24		T5	7
valid_sources[0x64]	12306	1			T1	6		T3	24		T4	86
valid_sources[0x65]	11387	1			T1	4		T3	18		T4	18
valid_sources[0x66]	9287	1			T1	14		T3	28		T4	22
valid_sources[0x67]	6829	1			T1	8		T3	21		T4	10
valid_sources[0x68]	11606	1			T1	11		T3	12		T4	50
valid_sources[0x69]	11143	1			T1	12		T3	12		T4	19
valid_sources[0x6a]	9802	1			T1	7		T3	22		T4	13
valid_sources[0x6b]	7770	1			T1	7		T3	11		T4	44
valid_sources[0x6c]	11801	1			T1	6		T3	17		T4	61
valid_sources[0x6d]	6814	1			T1	8		T3	14		T4	20
valid_sources[0x6e]	6426	1			T1	5		T3	9		T4	41
valid_sources[0x6f]	9800	1			T1	25		T3	25		T4	22
valid_sources[0x70]	6642	1			T1	9		T2	10		T3	8
valid_sources[0x71]	13860	1			T1	12		T3	16		T4	77
valid_sources[0x72]	7737	1			T1	10		T3	11		T4	33
valid_sources[0x73]	8237	1			T1	2		T3	18		T4	110
valid_sources[0x74]	7055	1			T1	6		T3	19		T4	18
valid_sources[0x75]	9526	1			T3	11		T4	50		T5	6
valid_sources[0x76]	13486	1			T1	2		T3	9		T4	110
valid_sources[0x77]	7947	1			T1	3		T3	15		T4	11
valid_sources[0x78]	6688	1			T1	12		T3	20		T4	14
valid_sources[0x79]	6727	1			T1	9		T3	19		T4	77
valid_sources[0x7a]	7968	1			T1	7		T3	25		T4	9
valid_sources[0x7b]	7977	1			T1	16		T3	17		T4	36
valid_sources[0x7c]	8452	1			T1	6		T3	14		T4	21
valid_sources[0x7d]	9862	1			T1	13		T3	22		T4	17
valid_sources[0x7e]	11443	1			T1	1		T3	19		T4	15
valid_sources[0x7f]	9751	1			T1	4		T3	14		T4	72
valid_sources[0x80]	10935	1			T1	21		T3	18		T4	62

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1027352

1

T1

1244

T2

39

T3

2022

values[0x0]

all_enables

biggest_size

73484

1

T1

69

T2

12

T3

54

values[0x1]

all_enables

biggest_size

53510

1

T1

42

T2

4

T3

36