Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	27593	1			T1	27		T3	11		T4	21
auto[PWRUP]	116	1			T8	1		T22	1		T24	2
auto[ONEST_0]	80	1			T24	3		T188	3		T33	1
auto[ONEST_021]	23	1			T8	1		T27	2		T209	1
auto[ONEST_1]	75	1			T8	1		T25	1		T24	3
auto[ONEST_DONE]	8	1			T8	1		T210	1		T211	1
auto[LP_0]	126	1			T22	2		T188	2		T27	1
auto[LP_021]	35	1			T22	1		T25	1		T23	1
auto[LP_1]	118	1			T22	2		T24	1		T188	1
auto[LP_EVAL]	53	1			T25	1		T23	3		T188	2
auto[LP_SLP]	467	1			T8	1		T22	5		T25	5
auto[LP_PWRUP]	41	1			T27	2		T209	1		T212	1
auto[NP_0]	128	1			T8	2		T22	2		T25	2
auto[NP_021]	43	1			T22	3		T24	1		T27	2
auto[NP_1]	184	1			T8	1		T22	2		T25	2
auto[NP_EVAL]	41	1			T22	1		T24	1		T27	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T33

1

T209

1

T77

1

min

27068

1

T1

27

T3

11

T4

21

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27075	1			T1	27		T3	11		T4	21
pow[0x1]	6	1			T8	1		T213	1		T205	1
pow[0x2]	20	1			T22	1		T213	1		T14	1
pow[0x3]	33	1			T25	1		T213	1		T134	2
pow[0x4]	70	1			T24	1		T27	2		T28	3
pow[0x5]	116	1			T22	1		T25	1		T23	1
pow[0x6]	281	1			T8	2		T22	2		T25	4
pow[0x7]	501	1			T8	1		T22	5		T25	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

182

1

T22

1

T25

2

T23

3

min

26634

1

T1

27

T3

11

T4

21

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26634	1			T1	27		T3	11		T4	21
pow[0x4]	1	1			T214	1		-	-		-	-
pow[0x6]	1	1			T77	1		-	-		-	-
pow[0x7]	1	1			T215	1		-	-		-	-
pow[0x8]	2	1			T25	1		T216	1		-	-
pow[0x9]	10	1			T25	1		T27	1		T217	1
pow[0xa]	20	1			T25	1		T33	4		T213	1
pow[0xb]	46	1			T8	1		T23	1		T24	1
pow[0xc]	68	1			T22	1		T23	2		T27	2
pow[0xd]	148	1			T25	2		T23	2		T24	2
pow[0xe]	293	1			T8	2		T22	4		T25	5
pow[0xf]	595	1			T8	2		T22	5		T25	4