Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2217	1			T8	22		T47	2		T22	9
auto[PWRUP]	124	1			T8	2		T22	2		T25	3
auto[ONEST_0]	74	1			T8	1		T22	2		T24	2
auto[ONEST_021]	18	1			T33	1		T338	1		T14	1
auto[ONEST_1]	99	1			T8	1		T22	2		T23	1
auto[ONEST_DONE]	2	1			T27	1		T339	1		-	-
auto[LP_0]	112	1			T8	3		T22	1		T25	2
auto[LP_021]	24	1			T27	1		T133	1		T338	1
auto[LP_1]	143	1			T8	2		T25	4		T23	4
auto[LP_EVAL]	61	1			T8	1		T25	1		T23	2
auto[LP_SLP]	532	1			T8	3		T22	3		T25	8
auto[LP_PWRUP]	24	1			T8	2		T28	2		T338	1
auto[NP_0]	204	1			T8	4		T22	1		T25	1
auto[NP_021]	47	1			T8	1		T28	1		T133	1
auto[NP_1]	230	1			T8	1		T22	3		T25	1
auto[NP_EVAL]	27	1			T39	1		T209	2		T340	1
auto[NP_DONE]	1	1			T67	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T212

1

T29

1

T341

2

min

1889

1

T8

27

T47

2

T22

4

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1901	1			T8	27		T47	2		T22	4
pow[0x1]	9	1			T27	1		T77	1		T342	1
pow[0x2]	18	1			T27	1		T343	1		T205	1
pow[0x3]	28	1			T23	2		T27	1		T133	1
pow[0x4]	74	1			T8	1		T22	1		T27	4
pow[0x5]	136	1			T22	3		T27	1		T28	2
pow[0x6]	244	1			T8	2		T22	3		T25	2
pow[0x7]	559	1			T8	3		T22	3		T25	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

207

1

T8

1

T22

1

T23

2

min

1265

1

T8

19

T47

2

T22

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1268	1			T8	19		T47	2		T22	3
pow[0x1]	15	1			T63	1		T73	3		T60	1
pow[0x2]	27	1			T8	1		T39	4		T102	5
pow[0x3]	33	1			T39	2		T12	1		T239	1
pow[0x4]	55	1			T8	2		T12	1		T134	3
pow[0x6]	1	1			T22	1		-	-		-	-
pow[0x7]	3	1			T22	1		T344	1		T339	1
pow[0x8]	6	1			T345	1		T330	1		T202	1
pow[0x9]	11	1			T134	1		T216	1		T214	1
pow[0xa]	24	1			T39	1		T338	1		T77	1
pow[0xb]	47	1			T25	2		T23	1		T24	1
pow[0xc]	72	1			T8	1		T22	1		T25	1
pow[0xd]	155	1			T22	1		T25	1		T23	1
pow[0xe]	276	1			T8	4		T22	5		T25	5
pow[0xf]	594	1			T8	5		T22	7		T25	10