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Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_chn1_filter_ctl_7_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.34 90.00 65.12 78.26 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.63 94.90 63.27 88.37 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
68.40 94.12 46.15 83.33 50.00 u_adc_chn_val_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 87.50 100.00 50.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.34 90.00 65.12 78.26 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.63 94.90 63.27 88.37 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
68.40 94.12 46.15 83.33 50.00 u_adc_chn_val_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 87.50 100.00 50.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_wakeup_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.17 100.00 93.02 95.65 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.36 100.00 87.76 97.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_filter_status_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 87.50 100.00 50.00 100.00 100.00

Go back
Module Instances:
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb
tb.dut.u_reg.u_filter_status_cdc.u_arb
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
284 1 1
285 1 1
300 unreachable


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T3,T4
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL504590.00
CONT_ASSIGN10011100.00
ALWAYS11233100.00
ALWAYS1226466.67
CONT_ASSIGN13611100.00
ALWAYS14066100.00
ALWAYS15610990.00
CONT_ASSIGN18411100.00
ALWAYS188191789.47
CONT_ASSIGN22911100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
112 1 1
113 1 1
115 1 1
122 1 1
123 1 1
124 1 1
129 0 1
130 1 1
133 0 1
MISSING_ELSE
136 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
MISSING_ELSE
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 0 1
162 1 1
163 1 1
164 1 1
165 1 1
MISSING_ELSE
184 1 1
188 1 1
189 1 1
193 1 1
194 1 1
196 1 1
198 1 1
200 1 1
201 1 1
203 0 1
204 0 1
205 1 1
206 1 1
207 1 1
208 1 1
211 1 1
212 1 1
MISSING_ELSE
217 1 1
218 1 1
219 1 1
MISSING_ELSE
229 1 1
244 1 1
245 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb
TotalCoveredPercent
Conditions432865.12
Logical432865.12
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT6,T17,T38
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       124
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       130
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111Not Covered

 LINE       136
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       158
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       162
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       184
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       208
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T17,T38

 LINE       229
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT6,T17,T38
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       245
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       245
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 18 78.26
IF 112 2 2 100.00
IF 122 4 2 50.00
IF 140 4 4 100.00
IF 156 6 5 83.33
CASE 198 7 5 71.43

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 112 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 122 if ((!rst_dst_ni)) -2-: 124 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 130 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 140 if ((!rst_dst_ni)) -2-: 142 if (gen_wr_req.dst_lat_d) -3-: 144 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T6,T17,T38
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 156 if ((!rst_dst_ni)) -2-: 158 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 160 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 162 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 164 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T1,T2,T3
0 0 1 - - Not Covered
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T6,T17,T38
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 198 case (gen_wr_req.state_q) -2-: 201 if (gen_wr_req.dst_req) -3-: 205 if (dst_update) -4-: 208 if ((dst_qs_o != dst_qs_i)) -5-: 218 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Not Covered
StIdle 0 1 - - Covered T1,T2,T3
StIdle 0 0 1 - Covered T6,T17,T38
StIdle 0 0 0 - Covered T1,T2,T3
StWait - - - 1 Covered T1,T2,T3
StWait - - - 0 Covered T1,T2,T3
default - - - - Not Covered


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 32334166 635333 0 912
gen_wr_req.HwIdSelCheck_A 32334166 635503 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 32334166 635333 0 912
T1 97850 2070 0 1
T2 1215 40 0 1
T3 33189 684 0 1
T4 98065 2086 0 1
T5 98643 2137 0 1
T6 32249 679 0 1
T7 32492 687 0 1
T8 20251 379 0 1
T9 97802 2079 0 1
T10 98029 2127 0 1

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 32334166 635503 0 0
T1 97850 2070 0 0
T2 1215 40 0 0
T3 33189 684 0 0
T4 98065 2086 0 0
T5 98643 2137 0 0
T6 32249 680 0 0
T7 32492 687 0 0
T8 20251 379 0 0
T9 97802 2079 0 0
T10 98029 2127 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL504590.00
CONT_ASSIGN10011100.00
ALWAYS11233100.00
ALWAYS1226466.67
CONT_ASSIGN13611100.00
ALWAYS14066100.00
ALWAYS15610990.00
CONT_ASSIGN18411100.00
ALWAYS188191789.47
CONT_ASSIGN22911100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
112 1 1
113 1 1
115 1 1
122 1 1
123 1 1
124 1 1
129 0 1
130 1 1
133 0 1
MISSING_ELSE
136 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
MISSING_ELSE
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 0 1
162 1 1
163 1 1
164 1 1
165 1 1
MISSING_ELSE
184 1 1
188 1 1
189 1 1
193 1 1
194 1 1
196 1 1
198 1 1
200 1 1
201 1 1
203 0 1
204 0 1
205 1 1
206 1 1
207 1 1
208 1 1
211 1 1
212 1 1
MISSING_ELSE
217 1 1
218 1 1
219 1 1
MISSING_ELSE
229 1 1
244 1 1
245 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb
TotalCoveredPercent
Conditions432865.12
Logical432865.12
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       124
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       130
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111Not Covered

 LINE       136
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       158
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       162
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       184
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       208
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       229
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T3,T4
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       245
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       245
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 18 78.26
IF 112 2 2 100.00
IF 122 4 2 50.00
IF 140 4 4 100.00
IF 156 6 5 83.33
CASE 198 7 5 71.43

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 112 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 122 if ((!rst_dst_ni)) -2-: 124 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 130 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 140 if ((!rst_dst_ni)) -2-: 142 if (gen_wr_req.dst_lat_d) -3-: 144 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T3,T4
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 156 if ((!rst_dst_ni)) -2-: 158 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 160 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 162 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 164 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T1,T2,T3
0 0 1 - - Not Covered
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T3,T4
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 198 case (gen_wr_req.state_q) -2-: 201 if (gen_wr_req.dst_req) -3-: 205 if (dst_update) -4-: 208 if ((dst_qs_o != dst_qs_i)) -5-: 218 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Not Covered
StIdle 0 1 - - Covered T1,T2,T3
StIdle 0 0 1 - Covered T1,T3,T4
StIdle 0 0 0 - Covered T1,T2,T3
StWait - - - 1 Covered T1,T2,T3
StWait - - - 0 Covered T1,T2,T3
default - - - - Not Covered


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 32334166 618657 0 912
gen_wr_req.HwIdSelCheck_A 32334166 626803 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 32334166 618657 0 912
T1 97850 2065 0 1
T2 1215 20 0 1
T3 33189 724 0 1
T4 98065 2048 0 1
T5 98643 2062 0 1
T6 32249 691 0 1
T7 32492 690 0 1
T8 20251 286 0 1
T9 97802 2078 0 1
T10 98029 2063 0 1

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 32334166 626803 0 0
T1 97850 2086 0 0
T2 1215 20 0 0
T3 33189 736 0 0
T4 98065 2069 0 0
T5 98643 2096 0 0
T6 32249 698 0 0
T7 32492 692 0 0
T8 20251 290 0 0
T9 97802 2102 0 0
T10 98029 2094 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable


Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT3,T5,T6
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T6
Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL5050100.00
CONT_ASSIGN10011100.00
ALWAYS11233100.00
ALWAYS12266100.00
CONT_ASSIGN13611100.00
ALWAYS14066100.00
ALWAYS1561010100.00
CONT_ASSIGN18411100.00
ALWAYS1881919100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
112 1 1
113 1 1
115 1 1
122 1 1
123 1 1
124 1 1
129 1 1
130 1 1
133 1 1
MISSING_ELSE
136 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
MISSING_ELSE
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
165 1 1
MISSING_ELSE
184 1 1
188 1 1
189 1 1
193 1 1
194 1 1
196 1 1
198 1 1
200 1 1
201 1 1
203 1 1
204 1 1
205 1 1
206 1 1
207 1 1
208 1 1
211 1 1
212 1 1
MISSING_ELSE
217 1 1
218 1 1
219 1 1
MISSING_ELSE
229 1 1
244 1 1
245 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb
TotalCoveredPercent
Conditions434093.02
Logical434093.02
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT12,T13,T14
10CoveredT1,T3,T4
11CoveredT1,T3,T4

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       124
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT34,T35,T36
11CoveredT37,T34,T35

 LINE       130
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T3,T4
101Not Covered
110CoveredT1,T3,T4
111CoveredT37,T34,T35

 LINE       136
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT37,T34,T35

 LINE       158
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T4
11CoveredT1,T3,T4

 LINE       160
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT34,T35,T36
11CoveredT1,T3,T4

 LINE       162
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T3,T4

 LINE       184
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01CoveredT37,T34,T35
10CoveredT1,T2,T3
11CoveredT1,T3,T4

 LINE       208
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T13,T14

 LINE       229
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT12,T13,T14
010CoveredT1,T3,T4
100CoveredT1,T3,T4

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T3,T4

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       245
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T3,T4
11CoveredT1,T3,T4

 LINE       245
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 22 95.65
IF 112 2 2 100.00
IF 122 4 4 100.00
IF 140 4 4 100.00
IF 156 6 6 100.00
CASE 198 7 6 85.71

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 112 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 122 if ((!rst_dst_ni)) -2-: 124 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 130 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T37,T34,T35
0 0 1 Covered T37,T34,T35
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 140 if ((!rst_dst_ni)) -2-: 142 if (gen_wr_req.dst_lat_d) -3-: 144 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T3,T4
0 0 1 Covered T12,T13,T14
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 156 if ((!rst_dst_ni)) -2-: 158 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 160 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 162 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 164 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T1,T3,T4
0 0 1 - - Covered T1,T3,T4
0 0 0 1 - Covered T1,T3,T4
0 0 0 0 1 Covered T12,T13,T14
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 198 case (gen_wr_req.state_q) -2-: 201 if (gen_wr_req.dst_req) -3-: 205 if (dst_update) -4-: 208 if ((dst_qs_o != dst_qs_i)) -5-: 218 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T3,T4
StIdle 0 1 - - Covered T1,T3,T4
StIdle 0 0 1 - Covered T12,T13,T14
StIdle 0 0 0 - Covered T1,T2,T3
StWait - - - 1 Covered T1,T3,T4
StWait - - - 0 Covered T1,T3,T4
default - - - - Not Covered


Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 32334166 12132 0 912
gen_wr_req.HwIdSelCheck_A 32334166 12174 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 32334166 12132 0 912
T1 97850 33 0 1
T2 1215 0 0 1
T3 33189 15 0 1
T4 98065 29 0 1
T5 98643 47 0 1
T6 32249 10 0 1
T7 32492 5 0 1
T8 20251 3 0 1
T9 97802 43 0 1
T10 98029 50 0 1
T11 0 19 0 0

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 32334166 12174 0 0
T1 97850 33 0 0
T2 1215 0 0 0
T3 33189 15 0 0
T4 98065 29 0 0
T5 98643 47 0 0
T6 32249 10 0 0
T7 32492 5 0 0
T8 20251 3 0 0
T9 97802 43 0 0
T10 98029 50 0 0
T11 0 19 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%