Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	7640	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2125	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2060	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2188	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2120	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2165	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2088	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2114	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2160	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2184	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2205	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1973	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2110	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2090	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2231	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2105	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1994	0	0
adc_en_ctl_rd_A	2147483647	1989	0	0
adc_fsm_rst_rd_A	2147483647	1759	0	0
adc_intr_ctl_rd_A	2147483647	2061	0	0
adc_lp_sample_ctl_rd_A	2147483647	1762	0	0
adc_pd_ctl_rd_A	2147483647	1963	0	0
adc_sample_ctl_rd_A	2147483647	1771	0	0
adc_wakeup_ctl_rd_A	2147483647	1761	0	0
intr_enable_rd_A	2147483647	2595	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7640	0	0
T13	318904	0	0	0
T64	0	1	0	0
T65	0	4	0	0
T67	0	2	0	0
T68	0	8	0	0
T69	0	1	0	0
T81	0	1	0	0
T102	397901	1	0	0
T104	260383	0	0	0
T105	593322	0	0	0
T106	6251	0	0	0
T107	13378	0	0	0
T108	795757	0	0	0
T109	408246	0	0	0
T110	230071	0	0	0
T111	147697	0	0	0
T174	0	2	0	0
T203	0	1	0	0
T204	0	1	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2125	0	0
T8	101260	44	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	8	0	0
T31	0	17	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	11	0	0
T98	0	10	0	0
T144	72174	0	0	0
T202	0	37	0	0
T205	0	13	0	0
T206	0	44	0	0
T207	0	29	0	0
T208	0	15	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2060	0	0
T8	101260	2	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	38	0	0
T31	0	17	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	14	0	0
T98	0	10	0	0
T144	72174	0	0	0
T202	0	25	0	0
T205	0	17	0	0
T206	0	28	0	0
T207	0	18	0	0
T208	0	5	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2188	0	0
T8	101260	33	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	32	0	0
T31	0	24	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	16	0	0
T98	0	11	0	0
T144	72174	0	0	0
T202	0	23	0	0
T205	0	19	0	0
T206	0	38	0	0
T207	0	13	0	0
T208	0	8	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2120	0	0
T8	101260	27	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	38	0	0
T31	0	18	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	19	0	0
T98	0	3	0	0
T144	72174	0	0	0
T202	0	24	0	0
T205	0	17	0	0
T206	0	36	0	0
T207	0	31	0	0
T208	0	13	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2165	0	0
T8	101260	23	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	38	0	0
T31	0	15	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	20	0	0
T98	0	9	0	0
T144	72174	0	0	0
T202	0	37	0	0
T205	0	24	0	0
T206	0	50	0	0
T207	0	42	0	0
T208	0	14	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2088	0	0
T8	101260	25	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	24	0	0
T31	0	6	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	14	0	0
T98	0	13	0	0
T144	72174	0	0	0
T202	0	22	0	0
T205	0	16	0	0
T206	0	60	0	0
T207	0	53	0	0
T208	0	12	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2114	0	0
T8	101260	5	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	32	0	0
T31	0	24	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	24	0	0
T98	0	17	0	0
T144	72174	0	0	0
T202	0	32	0	0
T205	0	20	0	0
T206	0	28	0	0
T207	0	29	0	0
T208	0	9	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2160	0	0
T8	101260	19	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	27	0	0
T31	0	27	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	25	0	0
T98	0	4	0	0
T144	72174	0	0	0
T202	0	30	0	0
T205	0	13	0	0
T206	0	28	0	0
T207	0	30	0	0
T208	0	20	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2184	0	0
T8	101260	32	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	25	0	0
T31	0	21	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	24	0	0
T98	0	13	0	0
T144	72174	0	0	0
T202	0	27	0	0
T205	0	20	0	0
T206	0	29	0	0
T207	0	40	0	0
T208	0	13	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2205	0	0
T8	101260	33	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	39	0	0
T31	0	21	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	20	0	0
T98	0	19	0	0
T144	72174	0	0	0
T202	0	28	0	0
T205	0	16	0	0
T206	0	36	0	0
T207	0	41	0	0
T208	0	5	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1973	0	0
T8	101260	7	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	21	0	0
T31	0	18	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	14	0	0
T98	0	2	0	0
T144	72174	0	0	0
T202	0	18	0	0
T205	0	11	0	0
T206	0	20	0	0
T207	0	23	0	0
T208	0	15	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2110	0	0
T8	101260	25	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	38	0	0
T31	0	28	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	18	0	0
T98	0	12	0	0
T144	72174	0	0	0
T202	0	26	0	0
T205	0	17	0	0
T206	0	49	0	0
T207	0	38	0	0
T208	0	8	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2090	0	0
T8	101260	17	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	36	0	0
T31	0	17	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	28	0	0
T98	0	14	0	0
T144	72174	0	0	0
T202	0	50	0	0
T205	0	7	0	0
T206	0	41	0	0
T207	0	31	0	0
T208	0	14	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2231	0	0
T8	101260	17	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	39	0	0
T31	0	27	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	10	0	0
T98	0	18	0	0
T144	72174	0	0	0
T202	0	36	0	0
T205	0	15	0	0
T206	0	31	0	0
T207	0	42	0	0
T208	0	4	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2105	0	0
T8	101260	28	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	21	0	0
T31	0	11	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	27	0	0
T144	72174	0	0	0
T202	0	27	0	0
T204	0	4	0	0
T205	0	16	0	0
T206	0	27	0	0
T207	0	43	0	0
T208	0	10	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1994	0	0
T8	101260	24	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	37	0	0
T31	0	19	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	32	0	0
T98	0	8	0	0
T144	72174	0	0	0
T202	0	26	0	0
T205	0	20	0	0
T206	0	37	0	0
T207	0	33	0	0
T208	0	1	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1989	0	0
T8	101260	16	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	43	0	0
T31	0	27	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	11	0	0
T98	0	4	0	0
T144	72174	0	0	0
T202	0	39	0	0
T205	0	16	0	0
T206	0	42	0	0
T207	0	29	0	0
T208	0	11	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1759	0	0
T8	101260	14	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	40	0	0
T31	0	20	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	8	0	0
T98	0	8	0	0
T144	72174	0	0	0
T202	0	45	0	0
T204	0	17	0	0
T205	0	21	0	0
T206	0	26	0	0
T207	0	22	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2061	0	0
T8	101260	13	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	39	0	0
T31	0	28	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	20	0	0
T98	0	2	0	0
T144	72174	0	0	0
T202	0	26	0	0
T205	0	23	0	0
T206	0	32	0	0
T207	0	46	0	0
T208	0	8	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1762	0	0
T8	101260	26	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	44	0	0
T31	0	27	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	10	0	0
T98	0	7	0	0
T144	72174	0	0	0
T202	0	45	0	0
T205	0	14	0	0
T206	0	31	0	0
T207	0	24	0	0
T208	0	17	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1963	0	0
T8	101260	20	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	42	0	0
T31	0	15	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	10	0	0
T98	0	8	0	0
T144	72174	0	0	0
T202	0	15	0	0
T205	0	33	0	0
T206	0	29	0	0
T207	0	37	0	0
T208	0	6	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1771	0	0
T8	101260	22	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	48	0	0
T31	0	19	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	31	0	0
T98	0	14	0	0
T144	72174	0	0	0
T202	0	23	0	0
T205	0	17	0	0
T206	0	18	0	0
T207	0	30	0	0
T208	0	17	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1761	0	0
T8	101260	10	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	26	0	0
T31	0	18	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T92	0	26	0	0
T98	0	4	0	0
T144	72174	0	0	0
T202	0	26	0	0
T205	0	20	0	0
T206	0	21	0	0
T207	0	35	0	0
T208	0	18	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2595	0	0
T8	101260	27	0	0
T9	122254	0	0	0
T10	588187	0	0	0
T11	159729	0	0	0
T15	25105	0	0	0
T16	807594	0	0	0
T21	101519	0	0	0
T30	0	73	0	0
T31	0	29	0	0
T32	92911	0	0	0
T62	803049	0	0	0
T85	0	19	0	0
T98	0	19	0	0
T132	0	29	0	0
T144	72174	0	0	0
T202	0	45	0	0
T205	0	38	0	0
T206	0	48	0	0
T207	0	71	0	0