Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1167270	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1120510

1

T1

1382

T4

2

T2

923

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2006825	1			T1	2547		T4	1		T2	1695
values[0x0]	139958	1			T1	157		T4	2		T2	107
values[0x1]	140997	1			T1	147		T4	5		T2	110

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	940259	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1347521

1

T1

1670

T4

2

T2

1105

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7192	1			T1	12		T2	12		T3	4
valid_sources[0x01]	9351	1			T1	8		T2	21		T3	3
valid_sources[0x02]	12473	1			T1	11		T2	4		T3	1
valid_sources[0x03]	9945	1			T1	12		T2	4		T3	5
valid_sources[0x04]	7215	1			T1	9		T2	5		T3	4
valid_sources[0x05]	8064	1			T1	8		T2	7		T3	4
valid_sources[0x06]	6702	1			T1	11		T2	2		T3	2
valid_sources[0x07]	6799	1			T1	9		T2	11		T3	2
valid_sources[0x08]	19662	1			T1	5		T2	3		T3	6
valid_sources[0x09]	7834	1			T1	13		T2	4		T3	6
valid_sources[0x0a]	8192	1			T1	13		T2	15		T3	10
valid_sources[0x0b]	12228	1			T1	8		T2	6		T3	8
valid_sources[0x0c]	7006	1			T1	10		T2	4		T3	1
valid_sources[0x0d]	7434	1			T1	7		T2	22		T3	1
valid_sources[0x0e]	7059	1			T1	16		T2	4		T3	7
valid_sources[0x0f]	11146	1			T1	12		T2	11		T3	4
valid_sources[0x10]	8136	1			T1	12		T2	5		T3	4
valid_sources[0x11]	6743	1			T1	19		T2	2		T3	2
valid_sources[0x12]	11434	1			T1	14		T2	9		T3	3
valid_sources[0x13]	12747	1			T1	11		T2	11		T5	2
valid_sources[0x14]	12170	1			T1	16		T2	13		T3	4
valid_sources[0x15]	6386	1			T1	5		T2	7		T3	3
valid_sources[0x16]	11433	1			T1	12		T2	5		T3	3
valid_sources[0x17]	11542	1			T1	16		T2	6		T3	3
valid_sources[0x18]	11305	1			T1	21		T2	6		T5	1
valid_sources[0x19]	8090	1			T1	4		T2	1		T3	4
valid_sources[0x1a]	9998	1			T1	28		T2	11		T7	27
valid_sources[0x1b]	11126	1			T1	18		T2	9		T3	5
valid_sources[0x1c]	6891	1			T1	5		T2	9		T3	7
valid_sources[0x1d]	7004	1			T1	15		T2	12		T3	2
valid_sources[0x1e]	7044	1			T1	16		T2	6		T3	2
valid_sources[0x1f]	6917	1			T1	14		T2	2		T5	1
valid_sources[0x20]	13762	1			T1	4		T2	4		T3	3
valid_sources[0x21]	12597	1			T1	6		T2	6		T5	1
valid_sources[0x22]	7318	1			T1	11		T2	5		T3	4
valid_sources[0x23]	6915	1			T1	9		T2	7		T3	3
valid_sources[0x24]	7244	1			T1	17		T2	1		T3	2
valid_sources[0x25]	6893	1			T1	7		T2	5		T3	2
valid_sources[0x26]	8094	1			T1	18		T2	12		T3	2
valid_sources[0x27]	11652	1			T1	9		T2	7		T3	3
valid_sources[0x28]	7232	1			T1	12		T2	4		T3	5
valid_sources[0x29]	7459	1			T1	14		T2	2		T3	6
valid_sources[0x2a]	12488	1			T1	7		T2	14		T3	5
valid_sources[0x2b]	8021	1			T1	9		T2	7		T3	3
valid_sources[0x2c]	6670	1			T1	12		T2	7		T3	1
valid_sources[0x2d]	7163	1			T1	8		T2	8		T3	1
valid_sources[0x2e]	7997	1			T1	8		T2	7		T3	2
valid_sources[0x2f]	6540	1			T1	9		T2	4		T3	1
valid_sources[0x30]	9719	1			T1	19		T2	1		T3	2
valid_sources[0x31]	7129	1			T1	8		T2	3		T3	8
valid_sources[0x32]	7361	1			T1	14		T2	8		T5	3
valid_sources[0x33]	7317	1			T1	10		T2	3		T3	4
valid_sources[0x34]	15012	1			T1	19		T2	26		T3	6
valid_sources[0x35]	13617	1			T1	20		T2	6		T3	6
valid_sources[0x36]	12278	1			T1	11		T2	5		T3	2
valid_sources[0x37]	9590	1			T1	9		T2	3		T3	1
valid_sources[0x38]	6938	1			T1	8		T2	9		T3	2
valid_sources[0x39]	6486	1			T1	7		T2	6		T3	10
valid_sources[0x3a]	6970	1			T1	17		T2	5		T3	1
valid_sources[0x3b]	6900	1			T1	19		T2	7		T3	4
valid_sources[0x3c]	6944	1			T1	12		T2	3		T3	4
valid_sources[0x3d]	6868	1			T1	16		T2	7		T3	7
valid_sources[0x3e]	6806	1			T1	10		T2	12		T3	7
valid_sources[0x3f]	7209	1			T1	13		T2	2		T5	1
valid_sources[0x40]	7200	1			T1	15		T2	3		T3	1
valid_sources[0x41]	7219	1			T1	10		T2	6		T3	3
valid_sources[0x42]	8608	1			T1	10		T2	14		T3	7
valid_sources[0x43]	12007	1			T1	13		T2	2		T3	3
valid_sources[0x44]	7732	1			T1	10		T2	4		T3	3
valid_sources[0x45]	15476	1			T1	8		T2	3		T3	6
valid_sources[0x46]	7326	1			T1	11		T2	11		T3	6
valid_sources[0x47]	7573	1			T1	8		T2	6		T3	2
valid_sources[0x48]	7251	1			T1	9		T2	4		T3	8
valid_sources[0x49]	14686	1			T1	15		T2	11		T3	1
valid_sources[0x4a]	7614	1			T1	8		T2	17		T3	4
valid_sources[0x4b]	6992	1			T1	10		T2	6		T7	35
valid_sources[0x4c]	11062	1			T1	9		T2	9		T3	7
valid_sources[0x4d]	7304	1			T1	13		T2	7		T5	1
valid_sources[0x4e]	7376	1			T1	10		T2	17		T3	3
valid_sources[0x4f]	7103	1			T1	7		T2	8		T3	4
valid_sources[0x50]	10818	1			T1	20		T2	10		T3	10
valid_sources[0x51]	7719	1			T1	12		T2	2		T3	8
valid_sources[0x52]	7055	1			T1	7		T2	6		T3	3
valid_sources[0x53]	14036	1			T1	7		T2	6		T3	7
valid_sources[0x54]	7027	1			T1	8		T2	5		T3	3
valid_sources[0x55]	6888	1			T1	14		T2	3		T3	6
valid_sources[0x56]	7294	1			T1	7		T3	2		T5	2
valid_sources[0x57]	9072	1			T1	11		T2	4		T3	4
valid_sources[0x58]	11464	1			T1	8		T2	17		T3	2
valid_sources[0x59]	6843	1			T1	10		T2	5		T3	1
valid_sources[0x5a]	7038	1			T1	14		T2	7		T3	4
valid_sources[0x5b]	6968	1			T1	15		T2	2		T3	4
valid_sources[0x5c]	9350	1			T1	2		T2	2		T3	1
valid_sources[0x5d]	8595	1			T1	12		T2	10		T3	3
valid_sources[0x5e]	8604	1			T1	13		T2	8		T5	2
valid_sources[0x5f]	6980	1			T1	14		T2	3		T3	6
valid_sources[0x60]	8184	1			T1	13		T2	13		T3	3
valid_sources[0x61]	11303	1			T1	18		T2	6		T3	4
valid_sources[0x62]	19905	1			T1	12		T2	5		T3	3
valid_sources[0x63]	7023	1			T1	7		T2	5		T3	5
valid_sources[0x64]	10165	1			T1	9		T2	2		T3	4
valid_sources[0x65]	8075	1			T1	11		T3	1		T5	2
valid_sources[0x66]	6989	1			T1	12		T2	23		T3	3
valid_sources[0x67]	7012	1			T1	15		T2	16		T3	7
valid_sources[0x68]	8204	1			T1	13		T2	2		T3	9
valid_sources[0x69]	8074	1			T1	14		T2	16		T3	3
valid_sources[0x6a]	6990	1			T1	9		T2	4		T3	2
valid_sources[0x6b]	7294	1			T1	14		T2	15		T3	6
valid_sources[0x6c]	9964	1			T1	8		T2	11		T3	6
valid_sources[0x6d]	7307	1			T1	12		T2	7		T3	3
valid_sources[0x6e]	11297	1			T1	11		T2	6		T3	10
valid_sources[0x6f]	7160	1			T1	7		T2	11		T3	12
valid_sources[0x70]	8569	1			T1	14		T2	8		T3	6
valid_sources[0x71]	12325	1			T1	9		T2	10		T3	4
valid_sources[0x72]	8926	1			T1	8		T2	18		T3	4
valid_sources[0x73]	6744	1			T1	11		T2	5		T3	4
valid_sources[0x74]	6614	1			T1	15		T2	10		T3	2
valid_sources[0x75]	7251	1			T1	8		T2	8		T5	1
valid_sources[0x76]	7247	1			T1	10		T2	7		T3	2
valid_sources[0x77]	7095	1			T1	6		T2	5		T7	34
valid_sources[0x78]	8365	1			T1	7		T2	2		T3	3
valid_sources[0x79]	9682	1			T1	4		T2	7		T3	2
valid_sources[0x7a]	7061	1			T1	11		T2	9		T3	4
valid_sources[0x7b]	7548	1			T1	18		T2	7		T3	9
valid_sources[0x7c]	7998	1			T1	15		T2	4		T3	5
valid_sources[0x7d]	10891	1			T1	9		T2	7		T3	2
valid_sources[0x7e]	9216	1			T1	8		T2	11		T5	3
valid_sources[0x7f]	6985	1			T1	14		T2	10		T3	12
valid_sources[0x80]	13975	1			T1	16		T2	4		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

998684

1

T1

1255

T4

1

T2

833

values[0x0]

all_enables

biggest_size

70471

1

T1

77

T4

1

T2

52

values[0x1]

all_enables

biggest_size

51355

1

T1

50

T2

38

T3

167