Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	26868	1			T1	23		T2	17		T3	148
auto[PWRUP]	110	1			T3	2		T24	3		T25	2
auto[ONEST_0]	62	1			T24	1		T21	1		T23	1
auto[ONEST_021]	16	1			T26	1		T208	1		T331	1
auto[ONEST_1]	70	1			T3	1		T25	1		T23	1
auto[ONEST_DONE]	10	1			T163	1		T332	1		T333	1
auto[LP_0]	123	1			T24	3		T25	2		T23	2
auto[LP_021]	34	1			T24	1		T25	1		T26	1
auto[LP_1]	123	1			T3	2		T24	2		T21	2
auto[LP_EVAL]	48	1			T26	1		T165	1		T30	5
auto[LP_SLP]	487	1			T3	4		T24	5		T21	6
auto[LP_PWRUP]	21	1			T27	1		T28	3		T334	1
auto[NP_0]	136	1			T3	1		T24	2		T21	2
auto[NP_021]	30	1			T21	1		T26	2		T27	2
auto[NP_1]	137	1			T21	1		T25	3		T23	2
auto[NP_EVAL]	30	1			T24	1		T186	1		T335	1
auto[NP_DONE]	1	1			T26	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T23

1

T333

1

T187

1

min

26416

1

T1

23

T2

17

T3

142

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26423	1			T1	23		T2	17		T3	142
pow[0x1]	6	1			T28	1		T335	1		T336	1
pow[0x2]	14	1			T3	1		T25	1		T26	1
pow[0x3]	44	1			T3	1		T25	2		T23	1
pow[0x4]	56	1			T3	1		T24	1		T23	2
pow[0x5]	120	1			T24	1		T21	2		T25	3
pow[0x6]	227	1			T3	2		T24	2		T21	3
pow[0x7]	456	1			T3	1		T24	8		T21	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

184

1

T3

1

T21

2

T25

3

min

25949

1

T1

23

T2

17

T3

136

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	25949	1			T1	23		T2	17		T3	136
pow[0x4]	1	1			T337	1		-	-		-	-
pow[0x5]	1	1			T338	1		-	-		-	-
pow[0x6]	2	1			T339	1		T340	1		-	-
pow[0x7]	1	1			T3	1		-	-		-	-
pow[0x8]	3	1			T38	1		T333	1		T339	1
pow[0x9]	8	1			T30	1		T341	1		T255	1
pow[0xa]	19	1			T163	1		T30	2		T27	2
pow[0xb]	35	1			T3	1		T25	1		T26	1
pow[0xc]	73	1			T3	2		T24	1		T21	1
pow[0xd]	140	1			T3	1		T24	4		T21	1
pow[0xe]	277	1			T3	3		T24	4		T21	2
pow[0xf]	542	1			T3	3		T24	6		T21	4