Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	100.00	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	0	45	100.00

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2219	1			T3	21		T5	4		T7	5
auto[PWRUP]	119	1			T3	2		T24	3		T21	2
auto[ONEST_0]	85	1			T3	2		T24	1		T29	1
auto[ONEST_021]	22	1			T15	1		T25	1		T30	1
auto[ONEST_1]	65	1			T24	1		T17	1		T21	1
auto[ONEST_DONE]	6	1			T165	1		T342	1		T343	1
auto[LP_0]	114	1			T3	1		T21	2		T163	2
auto[LP_021]	30	1			T26	2		T163	1		T59	1
auto[LP_1]	120	1			T3	3		T15	1		T24	1
auto[LP_EVAL]	46	1			T21	1		T22	1		T23	1
auto[LP_SLP]	469	1			T3	6		T24	6		T17	1
auto[LP_PWRUP]	36	1			T26	2		T28	1		T196	1
auto[NP_0]	219	1			T3	5		T24	2		T17	2
auto[NP_021]	29	1			T3	2		T29	1		T163	1
auto[NP_1]	237	1			T3	1		T15	1		T24	1
auto[NP_EVAL]	27	1			T29	2		T22	1		T165	1
auto[NP_DONE]	1	1			T278	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T23

1

T27

1

T341

1

min

1886

1

T3

8

T5

4

T7

5

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1894	1			T3	8		T5	4		T7	5
pow[0x1]	7	1			T165	1		T208	1		T187	1
pow[0x2]	19	1			T24	1		T342	1		T335	1
pow[0x3]	34	1			T3	1		T23	1		T30	2
pow[0x4]	63	1			T23	2		T26	1		T163	1
pow[0x5]	127	1			T3	3		T25	3		T26	4
pow[0x6]	245	1			T3	3		T24	4		T21	1
pow[0x7]	498	1			T3	9		T24	5		T21	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

210

1

T3

4

T24

2

T21

1

min

1306

1

T3

3

T5

4

T7

5

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1312	1			T3	3		T5	4		T7	5
pow[0x1]	22	1			T189	4		T74	1		T190	1
pow[0x2]	26	1			T17	1		T59	3		T188	2
pow[0x3]	47	1			T15	1		T17	1		T29	7
pow[0x4]	45	1			T229	3		T185	3		T257	2
pow[0x5]	1	1			T344	1		-	-		-	-
pow[0x6]	1	1			T128	1		-	-		-	-
pow[0x7]	3	1			T24	1		T339	1		T345	1
pow[0x8]	5	1			T28	1		T334	1		T331	1
pow[0x9]	9	1			T3	1		T25	1		T332	1
pow[0xa]	24	1			T24	1		T21	1		T196	1
pow[0xb]	28	1			T26	1		T163	2		T31	1
pow[0xc]	61	1			T3	1		T30	1		T31	3
pow[0xd]	140	1			T3	2		T23	1		T26	4
pow[0xe]	268	1			T3	7		T24	3		T21	3
pow[0xf]	531	1			T3	10		T24	9		T21	5