Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.70	99.67	98.31		100.00	95.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	97.92	100.00	96.84		100.00	92.77	100.00
u_adc_ctrl_intr	95.01	98.67	84.62			96.77	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		61	61	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	199	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	8	8
59	8	8
68	1	1
69	1	1
70	1	1
71	1	1
79	1	1
82	1	1
83	1	1
84	1	1
85	1	1
100	8	8
103	8	8
113	8	8
117	8	8
133	1	1
134	1	1
138	1	1
199	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	284	284	100.00
Logical	284	284	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T5,T15

 LINE       79
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T4,T2

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T7,T10,T12
1	Covered	T1,T4,T2

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T12
0	1	Covered	T7,T10,T12
1	0	Covered	T7,T10,T12

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T1,T8,T12
1	Covered	T1,T4,T2

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T12
0	1	Covered	T1,T8,T12
1	0	Covered	T1,T8,T12

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T4,T2

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T4,T2

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T1,T7,T12
1	Covered	T1,T4,T2

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T12
0	1	Covered	T1,T7,T12
1	0	Covered	T1,T7,T12

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T4,T2

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T4,T2

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T4,T2

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T4,T2

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T1,T12,T13
1	Covered	T1,T4,T2

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T13
0	1	Covered	T1,T12,T13
1	0	Covered	T1,T12,T13

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T1,T8,T12
1	Covered	T1,T4,T2

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T12
0	1	Covered	T1,T8,T12
1	0	Covered	T1,T8,T12

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T4,T2

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T4,T2

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T1,T7,T12
1	Covered	T1,T4,T2

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T12
0	1	Covered	T1,T7,T12
1	0	Covered	T1,T7,T12

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T4,T2

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T4,T2

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T4,T2

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T1,T2,T7
1	1	0	Covered	T1,T2,T7
1	1	1	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2

 LINE       113
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2

 LINE       113
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T2,T3

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T2,T7,T8
1	1	0	Covered	T1,T2,T7
1	1	1	Covered	T1,T2,T7

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T8
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T4,T2

 LINE       113
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T7,T8

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2

 LINE       113
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T2,T7

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T1,T2,T7
1	1	0	Covered	T1,T2,T7
1	1	1	Covered	T1,T2,T7

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2

 LINE       113
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T2,T7

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2

 LINE       113
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T2,T7

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T1,T2,T7
1	1	0	Covered	T1,T2,T7
1	1	1	Covered	T1,T2,T7

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2

 LINE       113
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T2,T7

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2

 LINE       113
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T2,T7

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T2,T10,T11
1	1	0	Covered	T2,T8,T10
1	1	1	Covered	T2,T8,T10

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T10
0	1	Covered	T2,T8,T10
1	0	Covered	T1,T4,T2

 LINE       113
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T10
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T8,T10

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T10
0	1	Covered	T2,T8,T10
1	0	Covered	T1,T4,T2

 LINE       113
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T10
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T8,T10

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T1,T2,T7
1	1	0	Covered	T1,T2,T7
1	1	1	Covered	T1,T2,T7

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2

 LINE       113
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T2,T7

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2

 LINE       113
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T2,T7

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T1,T2,T7
1	1	0	Covered	T1,T2,T7
1	1	1	Covered	T1,T2,T7

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2

 LINE       113
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T2,T7

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2

 LINE       113
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T2,T7

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T1,T2,T10
1	1	1	Covered	T1,T2,T10

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T10
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T4,T2

 LINE       113
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T2,T10

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T10
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T4,T2

 LINE       113
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T2,T10

 LINE       117
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       117
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       117
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       117
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       117
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T10
1	0	Covered	T1,T2,T7
1	1	Covered	T2,T8,T10

 LINE       117
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       117
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       117
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T10

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	79	3	3	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	79	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T5,T15
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T7,T10,T12

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T12,T13

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T8,T12

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T8,T12

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T7,T12

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T7,T12

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T2,T7

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	30828137	30534102	0	0
gen_filter_match[0].MatchCheck00_A	30828137	8927378	0	0
gen_filter_match[0].MatchCheck01_A	30828137	2540724	0	0
gen_filter_match[0].MatchCheck10_A	30828137	2149711	0	0
gen_filter_match[0].MatchCheck11_A	30828137	16916289	0	0
gen_filter_match[1].MatchCheck00_A	30828137	10250655	0	0
gen_filter_match[1].MatchCheck01_A	30828137	1148725	0	0
gen_filter_match[1].MatchCheck10_A	30828137	1229093	0	0
gen_filter_match[1].MatchCheck11_A	30828137	17905629	0	0
gen_filter_match[2].MatchCheck00_A	30828137	10610830	0	0
gen_filter_match[2].MatchCheck01_A	30828137	619120	0	0
gen_filter_match[2].MatchCheck10_A	30828137	630025	0	0
gen_filter_match[2].MatchCheck11_A	30828137	18674127	0	0
gen_filter_match[3].MatchCheck00_A	30828137	11157704	0	0
gen_filter_match[3].MatchCheck01_A	30828137	130766	0	0
gen_filter_match[3].MatchCheck10_A	30828137	168896	0	0
gen_filter_match[3].MatchCheck11_A	30828137	19076736	0	0
gen_filter_match[4].MatchCheck00_A	30828137	11819662	0	0
gen_filter_match[4].MatchCheck01_A	30828137	67176	0	0
gen_filter_match[4].MatchCheck10_A	30828137	61	0	0
gen_filter_match[4].MatchCheck11_A	30828137	18647203	0	0
gen_filter_match[5].MatchCheck00_A	30828137	11420228	0	0
gen_filter_match[5].MatchCheck01_A	30828137	5	0	0
gen_filter_match[5].MatchCheck10_A	30828137	130479	0	0
gen_filter_match[5].MatchCheck11_A	30828137	18983390	0	0
gen_filter_match[6].MatchCheck00_A	30828137	11804081	0	0
gen_filter_match[6].MatchCheck01_A	30828137	135553	0	0
gen_filter_match[6].MatchCheck10_A	30828137	63956	0	0
gen_filter_match[6].MatchCheck11_A	30828137	18530512	0	0
gen_filter_match[7].MatchCheck00_A	30828137	11049350	0	0
gen_filter_match[7].MatchCheck01_A	30828137	316969	0	0
gen_filter_match[7].MatchCheck10_A	30828137	137199	0	0
gen_filter_match[7].MatchCheck11_A	30828137	19030584	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	30534102	0	0
T1	100395	100344	0	0
T2	66337	66266	0	0
T3	21653	18239	0	0
T4	104	4	0	0
T5	3256	2918	0	0
T6	5264	5199	0	0
T7	137045	136586	0	0
T8	34500	34407	0	0
T9	8361	8294	0	0
T10	67379	67281	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	8927378	0	0
T1	100395	32675	0	0
T2	66337	4	0	0
T3	21653	18182	0	0
T4	104	4	0	0
T5	3256	2918	0	0
T6	5264	5199	0	0
T7	137045	39108	0	0
T8	34500	34407	0	0
T9	8361	8294	0	0
T10	67379	67281	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	2540724	0	0
T7	137045	64583	0	0
T8	34500	0	0	0
T9	8361	0	0	0
T10	67379	0	0	0
T11	31944	0	0	0
T12	98916	33619	0	0
T13	98528	32149	0	0
T14	65728	0	0	0
T15	1938	0	0	0
T16	0	33336	0	0
T25	0	32896	0	0
T29	0	19255	0	0
T53	0	32413	0	0
T56	0	32772	0	0
T58	100251	0	0	0
T67	0	34304	0	0
T115	0	32456	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	2149711	0	0
T1	100395	33255	0	0
T2	66337	0	0	0
T3	21653	0	0	0
T4	104	0	0	0
T5	3256	0	0	0
T6	5264	0	0	0
T7	137045	0	0	0
T8	34500	0	0	0
T9	8361	0	0	0
T10	67379	0	0	0
T13	0	34620	0	0
T14	0	32836	0	0
T51	0	1	0	0
T116	0	33200	0	0
T117	0	31882	0	0
T118	0	33034	0	0
T119	0	32582	0	0
T120	0	33269	0	0
T121	0	33507	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	16916289	0	0
T1	100395	34414	0	0
T2	66337	66262	0	0
T3	21653	57	0	0
T4	104	0	0	0
T5	3256	0	0	0
T6	5264	0	0	0
T7	137045	32895	0	0
T8	34500	0	0	0
T9	8361	0	0	0
T10	67379	0	0	0
T11	0	31876	0	0
T12	0	32405	0	0
T13	0	31699	0	0
T58	0	100175	0	0
T80	0	33036	0	0
T81	0	64856	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	10250655	0	0
T1	100395	65930	0	0
T2	66337	4	0	0
T3	21653	18239	0	0
T4	104	4	0	0
T5	3256	2918	0	0
T6	5264	5199	0	0
T7	137045	37561	0	0
T8	34500	3	0	0
T9	8361	8294	0	0
T10	67379	4	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	1148725	0	0
T1	100395	34414	0	0
T2	66337	0	0	0
T3	21653	0	0	0
T4	104	0	0	0
T5	3256	0	0	0
T6	5264	0	0	0
T7	137045	0	0	0
T8	34500	0	0	0
T9	8361	0	0	0
T10	67379	32927	0	0
T53	0	3	0	0
T56	0	31677	0	0
T66	0	32604	0	0
T68	0	31807	0	0
T122	0	2	0	0
T123	0	33133	0	0
T124	0	33294	0	0
T125	0	32179	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	1229093	0	0
T13	98528	31699	0	0
T14	65728	0	0	0
T15	1938	0	0	0
T18	33248	0	0	0
T53	0	1	0	0
T58	100251	0	0	0
T80	33135	0	0	0
T81	64913	0	0	0
T111	1212	0	0	0
T112	617	0	0	0
T120	0	32923	0	0
T122	65049	1	0	0
T126	0	32601	0	0
T127	0	1	0	0
T128	0	33594	0	0
T129	0	32024	0	0
T130	0	33595	0	0
T131	0	33471	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	17905629	0	0
T2	66337	66262	0	0
T3	21653	0	0	0
T5	3256	0	0	0
T6	5264	0	0	0
T7	137045	99025	0	0
T8	34500	34404	0	0
T9	8361	0	0	0
T10	67379	34350	0	0
T11	31944	31876	0	0
T12	98916	0	0	0
T14	0	32798	0	0
T15	0	856	0	0
T58	0	100175	0	0
T80	0	33036	0	0
T122	0	32776	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	10610830	0	0
T1	100395	33258	0	0
T2	66337	4	0	0
T3	21653	18239	0	0
T4	104	4	0	0
T5	3256	2918	0	0
T6	5264	5199	0	0
T7	137045	37561	0	0
T8	34500	34407	0	0
T9	8361	8294	0	0
T10	67379	67281	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	619120	0	0
T21	14090	0	0	0
T53	0	3	0	0
T108	35638	0	0	0
T117	65561	0	0	0
T132	66424	32999	0	0
T133	0	32296	0	0
T134	0	33102	0	0
T135	0	33240	0	0
T136	0	32848	0	0
T137	0	23165	0	0
T138	0	33915	0	0
T139	0	1	0	0
T140	0	32967	0	0
T141	33278	0	0	0
T142	1211	0	0	0
T143	724	0	0	0
T144	32460	0	0	0
T145	70	0	0	0
T146	32935	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	630025	0	0
T7	137045	2	0	0
T8	34500	0	0	0
T9	8361	0	0	0
T10	67379	0	0	0
T11	31944	0	0	0
T12	98916	0	0	0
T13	98528	0	0	0
T14	65728	0	0	0
T15	1938	0	0	0
T53	0	2	0	0
T58	100251	0	0	0
T122	0	1	0	0
T127	0	2	0	0
T128	0	2	0	0
T132	0	33362	0	0
T147	0	32055	0	0
T148	0	31960	0	0
T149	0	32274	0	0
T150	0	1	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	18674127	0	0
T1	100395	67086	0	0
T2	66337	66262	0	0
T3	21653	0	0	0
T4	104	0	0	0
T5	3256	0	0	0
T6	5264	0	0	0
T7	137045	99023	0	0
T8	34500	0	0	0
T9	8361	0	0	0
T10	67379	0	0	0
T11	0	31876	0	0
T12	0	33619	0	0
T13	0	31699	0	0
T14	0	65634	0	0
T15	0	856	0	0
T58	0	100175	0	0
T122	0	64991	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	11157704	0	0
T1	100395	67089	0	0
T2	66337	4	0	0
T3	21653	18239	0	0
T4	104	4	0	0
T5	3256	2918	0	0
T6	5264	5199	0	0
T7	137045	38849	0	0
T8	34500	34407	0	0
T9	8361	8294	0	0
T10	67379	67281	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	130766	0	0
T12	98916	32405	0	0
T13	98528	0	0	0
T14	65728	0	0	0
T15	1938	0	0	0
T18	33248	0	0	0
T58	100251	0	0	0
T80	33135	0	0	0
T81	64913	0	0	0
T112	617	0	0	0
T122	65049	0	0	0
T130	0	1	0	0
T134	0	1	0	0
T139	0	1	0	0
T151	0	32628	0	0
T152	0	33063	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	32664	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	168896	0	0
T7	137045	2	0	0
T8	34500	0	0	0
T9	8361	0	0	0
T10	67379	0	0	0
T11	31944	0	0	0
T12	98916	0	0	0
T13	98528	0	0	0
T14	65728	0	0	0
T15	1938	0	0	0
T53	0	2	0	0
T58	100251	0	0	0
T127	0	2	0	0
T128	0	2	0	0
T130	0	1	0	0
T150	0	1	0	0
T157	0	1	0	0
T158	0	32516	0	0
T159	0	1	0	0
T160	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	19076736	0	0
T1	100395	33255	0	0
T2	66337	66262	0	0
T3	21653	0	0	0
T4	104	0	0	0
T5	3256	0	0	0
T6	5264	0	0	0
T7	137045	97735	0	0
T8	34500	0	0	0
T9	8361	0	0	0
T10	67379	0	0	0
T11	0	31876	0	0
T12	0	66423	0	0
T13	0	66319	0	0
T14	0	32798	0	0
T15	0	856	0	0
T58	0	100175	0	0
T80	0	33036	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	11819662	0	0
T1	100395	100344	0	0
T2	66337	4	0	0
T3	21653	18239	0	0
T4	104	4	0	0
T5	3256	2918	0	0
T6	5264	5199	0	0
T7	137045	136586	0	0
T8	34500	3	0	0
T9	8361	8294	0	0
T10	67379	34354	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	67176	0	0
T45	1638	0	0	0
T53	98238	2	0	0
T54	915	0	0	0
T55	99870	0	0	0
T56	64502	0	0	0
T57	65158	0	0	0
T130	0	1	0	0
T139	0	1	0	0
T151	0	1	0	0
T152	0	33607	0	0
T154	0	1	0	0
T161	0	33562	0	0
T162	0	1	0	0
T163	20694	0	0	0
T164	6618	0	0	0
T165	8616	0	0	0
T166	33204	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	61	0	0
T43	73	0	0	0
T53	0	2	0	0
T66	0	1	0	0
T115	70823	0	0	0
T116	34332	0	0	0
T127	0	2	0	0
T128	0	1	0	0
T130	0	1	0	0
T132	66424	0	0	0
T141	33278	0	0	0
T142	1211	0	0	0
T143	724	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T157	100207	1	0	0
T159	0	1	0	0
T167	0	1	0	0
T168	64426	0	0	0
T169	1165	0	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	18647203	0	0
T2	66337	66262	0	0
T3	21653	0	0	0
T5	3256	0	0	0
T6	5264	0	0	0
T7	137045	0	0	0
T8	34500	34404	0	0
T9	8361	0	0	0
T10	67379	32927	0	0
T11	31944	31876	0	0
T12	98916	98828	0	0
T13	0	32149	0	0
T14	0	65634	0	0
T58	0	100175	0	0
T80	0	33036	0	0
T81	0	64856	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	11420228	0	0
T1	100395	3	0	0
T2	66337	4	0	0
T3	21653	18239	0	0
T4	104	4	0	0
T5	3256	2918	0	0
T6	5264	5199	0	0
T7	137045	72003	0	0
T8	34500	3	0	0
T9	8361	8294	0	0
T10	67379	4	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	5	0	0
T18	33248	0	0	0
T19	66116	0	0	0
T42	69	0	0	0
T80	33135	0	0	0
T81	64913	0	0	0
T111	1212	0	0	0
T112	617	0	0	0
T113	1159	0	0	0
T122	65049	2	0	0
T139	0	1	0	0
T153	0	1	0	0
T162	0	1	0	0
T170	34013	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	130479	0	0
T7	137045	2	0	0
T8	34500	0	0	0
T9	8361	0	0	0
T10	67379	0	0	0
T11	31944	0	0	0
T12	98916	0	0	0
T13	98528	0	0	0
T14	65728	0	0	0
T15	1938	0	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T58	100251	1	0	0
T66	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T157	0	1	0	0
T167	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	18983390	0	0
T1	100395	100341	0	0
T2	66337	66262	0	0
T3	21653	0	0	0
T4	104	0	0	0
T5	3256	0	0	0
T6	5264	0	0	0
T7	137045	64581	0	0
T8	34500	34404	0	0
T9	8361	0	0	0
T10	67379	67277	0	0
T11	0	31876	0	0
T12	0	66423	0	0
T13	0	66319	0	0
T14	0	32836	0	0
T15	0	856	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	11804081	0	0
T1	100395	3	0	0
T2	66337	4	0	0
T3	21653	18239	0	0
T4	104	4	0	0
T5	3256	2918	0	0
T6	5264	5199	0	0
T7	137045	71825	0	0
T8	34500	3	0	0
T9	8361	8294	0	0
T10	67379	4	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	135553	0	0
T21	14090	0	0	0
T22	4287	0	0	0
T53	0	1	0	0
T117	65561	33613	0	0
T118	33090	0	0	0
T120	0	1	0	0
T134	0	1	0	0
T146	32935	0	0	0
T151	0	1	0	0
T159	0	1	0	0
T161	0	34550	0	0
T171	0	1	0	0
T172	0	32877	0	0
T173	0	34506	0	0
T174	35876	0	0	0
T175	33189	0	0	0
T176	6517	0	0	0
T177	1158	0	0	0
T178	1086	0	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	63956	0	0
T7	137045	2	0	0
T8	34500	0	0	0
T9	8361	0	0	0
T10	67379	0	0	0
T11	31944	0	0	0
T12	98916	0	0	0
T13	98528	0	0	0
T14	65728	0	0	0
T15	1938	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T58	100251	1	0	0
T120	0	1	0	0
T122	0	1	0	0
T123	0	2	0	0
T157	0	1	0	0
T167	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	18530512	0	0
T1	100395	100341	0	0
T2	66337	66262	0	0
T3	21653	0	0	0
T4	104	0	0	0
T5	3256	0	0	0
T6	5264	0	0	0
T7	137045	64759	0	0
T8	34500	34404	0	0
T9	8361	0	0	0
T10	67379	67277	0	0
T11	0	31876	0	0
T12	0	66423	0	0
T13	0	98468	0	0
T14	0	32836	0	0
T15	0	856	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	11049350	0	0
T1	100395	33258	0	0
T2	66337	4	0	0
T3	21653	18239	0	0
T4	104	4	0	0
T5	3256	2918	0	0
T6	5264	5199	0	0
T7	137045	136586	0	0
T8	34500	34407	0	0
T9	8361	8294	0	0
T10	67379	4	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	316969	0	0
T29	48013	22496	0	0
T43	73	0	0	0
T56	0	1	0	0
T115	70823	0	0	0
T116	34332	0	0	0
T130	0	1	0	0
T132	66424	0	0	0
T141	33278	0	0	0
T152	0	2	0	0
T157	100207	0	0	0
T159	0	1	0	0
T168	64426	0	0	0
T169	1165	0	0	0
T179	0	32219	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	32947	0	0
T183	0	1	0	0
T184	7277	0	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	137199	0	0
T10	67379	34350	0	0
T11	31944	0	0	0
T12	98916	0	0	0
T13	98528	0	0	0
T14	65728	0	0	0
T15	1938	0	0	0
T51	0	1	0	0
T53	0	2	0	0
T58	100251	1	0	0
T65	0	1	0	0
T80	33135	0	0	0
T112	617	0	0	0
T122	65049	3	0	0
T123	0	1	0	0
T144	0	1	0	0
T157	0	1	0	0
T167	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30828137	19030584	0	0
T1	100395	67086	0	0
T2	66337	66262	0	0
T3	21653	0	0	0
T4	104	0	0	0
T5	3256	0	0	0
T6	5264	0	0	0
T7	137045	0	0	0
T8	34500	0	0	0
T9	8361	0	0	0
T10	67379	32927	0	0
T11	0	31876	0	0
T12	0	65209	0	0
T13	0	66319	0	0
T14	0	32798	0	0
T15	0	856	0	0
T58	0	100174	0	0
T122	0	32211	0	0