Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	6728	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2415	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2183	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2063	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2240	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2306	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2210	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2410	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2213	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2115	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2223	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2168	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2261	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2293	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2191	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2159	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2286	0	0
adc_en_ctl_rd_A	2147483647	1966	0	0
adc_fsm_rst_rd_A	2147483647	1835	0	0
adc_intr_ctl_rd_A	2147483647	2010	0	0
adc_lp_sample_ctl_rd_A	2147483647	1816	0	0
adc_pd_ctl_rd_A	2147483647	2082	0	0
adc_sample_ctl_rd_A	2147483647	1837	0	0
adc_wakeup_ctl_rd_A	2147483647	1820	0	0
intr_enable_rd_A	2147483647	2294	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6728	0	0
T17	418692	1	0	0
T29	500614	1	0	0
T38	0	3	0	0
T43	8907	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T75	0	1	0	0
T79	0	1	0	0
T115	354123	0	0	0
T116	766173	0	0	0
T132	324006	0	0	0
T137	0	1	0	0
T157	120249	0	0	0
T168	309240	0	0	0
T169	145795	0	0	0
T184	349354	0	0	0
T186	0	1	0	0
T187	0	1	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2415	0	0
T15	950454	29	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	15	0	0
T188	0	41	0	0
T189	0	12	0	0
T190	0	38	0	0
T191	0	11	0	0
T192	0	25	0	0
T193	0	11	0	0
T194	0	15	0	0
T195	0	28	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2183	0	0
T15	950454	23	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	23	0	0
T188	0	24	0	0
T189	0	32	0	0
T190	0	39	0	0
T191	0	18	0	0
T192	0	33	0	0
T193	0	8	0	0
T194	0	30	0	0
T195	0	20	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2063	0	0
T15	950454	28	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	25	0	0
T188	0	37	0	0
T189	0	31	0	0
T190	0	40	0	0
T191	0	17	0	0
T192	0	30	0	0
T193	0	17	0	0
T194	0	15	0	0
T195	0	20	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2240	0	0
T15	950454	22	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	28	0	0
T188	0	21	0	0
T189	0	22	0	0
T190	0	58	0	0
T191	0	17	0	0
T192	0	28	0	0
T193	0	14	0	0
T194	0	28	0	0
T195	0	6	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2306	0	0
T15	950454	11	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	34	0	0
T188	0	39	0	0
T189	0	14	0	0
T190	0	44	0	0
T191	0	17	0	0
T192	0	33	0	0
T193	0	22	0	0
T194	0	23	0	0
T195	0	14	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2210	0	0
T15	950454	20	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	19	0	0
T188	0	42	0	0
T189	0	35	0	0
T190	0	34	0	0
T191	0	11	0	0
T192	0	36	0	0
T193	0	18	0	0
T194	0	20	0	0
T195	0	10	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2410	0	0
T15	950454	22	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	37	0	0
T188	0	39	0	0
T189	0	19	0	0
T190	0	38	0	0
T191	0	28	0	0
T192	0	32	0	0
T193	0	18	0	0
T194	0	19	0	0
T195	0	15	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2213	0	0
T15	950454	31	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	38	0	0
T188	0	40	0	0
T189	0	26	0	0
T190	0	25	0	0
T191	0	30	0	0
T192	0	25	0	0
T193	0	12	0	0
T194	0	18	0	0
T195	0	15	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2115	0	0
T15	950454	17	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	21	0	0
T188	0	28	0	0
T189	0	14	0	0
T190	0	32	0	0
T191	0	7	0	0
T192	0	19	0	0
T193	0	14	0	0
T194	0	25	0	0
T195	0	10	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2223	0	0
T15	950454	18	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	23	0	0
T188	0	46	0	0
T189	0	29	0	0
T190	0	32	0	0
T191	0	18	0	0
T192	0	22	0	0
T193	0	20	0	0
T194	0	19	0	0
T195	0	30	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2168	0	0
T15	950454	28	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	33	0	0
T188	0	28	0	0
T189	0	17	0	0
T190	0	39	0	0
T191	0	22	0	0
T192	0	24	0	0
T193	0	11	0	0
T194	0	35	0	0
T195	0	21	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2261	0	0
T15	950454	22	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	25	0	0
T188	0	25	0	0
T189	0	27	0	0
T190	0	30	0	0
T191	0	18	0	0
T192	0	38	0	0
T193	0	13	0	0
T194	0	32	0	0
T195	0	15	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2293	0	0
T15	950454	17	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	23	0	0
T188	0	44	0	0
T189	0	21	0	0
T190	0	25	0	0
T191	0	19	0	0
T192	0	31	0	0
T193	0	4	0	0
T194	0	16	0	0
T195	0	20	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2191	0	0
T15	950454	28	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	34	0	0
T188	0	38	0	0
T189	0	26	0	0
T190	0	46	0	0
T191	0	11	0	0
T192	0	30	0	0
T193	0	4	0	0
T194	0	19	0	0
T195	0	16	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2159	0	0
T15	950454	21	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	17	0	0
T188	0	44	0	0
T189	0	22	0	0
T190	0	33	0	0
T191	0	16	0	0
T192	0	33	0	0
T193	0	13	0	0
T194	0	12	0	0
T195	0	24	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2286	0	0
T15	950454	21	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	30	0	0
T188	0	27	0	0
T189	0	36	0	0
T190	0	30	0	0
T191	0	20	0	0
T192	0	25	0	0
T193	0	18	0	0
T194	0	4	0	0
T195	0	23	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1966	0	0
T15	950454	18	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	14	0	0
T188	0	40	0	0
T189	0	25	0	0
T190	0	40	0	0
T191	0	13	0	0
T192	0	39	0	0
T193	0	7	0	0
T194	0	24	0	0
T195	0	16	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1835	0	0
T15	950454	24	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	28	0	0
T188	0	41	0	0
T189	0	40	0	0
T190	0	44	0	0
T191	0	18	0	0
T192	0	31	0	0
T193	0	11	0	0
T194	0	16	0	0
T195	0	18	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2010	0	0
T15	950454	22	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	30	0	0
T188	0	39	0	0
T189	0	34	0	0
T190	0	48	0	0
T191	0	17	0	0
T192	0	36	0	0
T193	0	11	0	0
T194	0	17	0	0
T195	0	21	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1816	0	0
T15	950454	25	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	38	0	0
T188	0	29	0	0
T189	0	12	0	0
T190	0	35	0	0
T191	0	20	0	0
T192	0	30	0	0
T193	0	23	0	0
T194	0	23	0	0
T195	0	14	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2082	0	0
T15	950454	14	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	41	0	0
T188	0	15	0	0
T189	0	14	0	0
T190	0	38	0	0
T191	0	18	0	0
T192	0	31	0	0
T193	0	16	0	0
T194	0	20	0	0
T195	0	19	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1837	0	0
T15	950454	10	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	31	0	0
T188	0	33	0	0
T189	0	19	0	0
T190	0	36	0	0
T191	0	20	0	0
T192	0	38	0	0
T193	0	9	0	0
T194	0	29	0	0
T195	0	22	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1820	0	0
T15	950454	15	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	50	0	0
T188	0	48	0	0
T189	0	23	0	0
T190	0	39	0	0
T191	0	12	0	0
T192	0	35	0	0
T193	0	18	0	0
T194	0	12	0	0
T195	0	21	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2294	0	0
T15	950454	53	0	0
T18	831237	0	0	0
T19	236632	0	0	0
T42	9514	0	0	0
T58	125315	0	0	0
T80	152423	0	0	0
T81	262897	0	0	0
T111	151584	0	0	0
T112	303498	0	0	0
T122	325255	0	0	0
T165	0	33	0	0
T188	0	32	0	0
T189	0	21	0	0
T190	0	56	0	0
T191	0	30	0	0
T192	0	39	0	0
T193	0	21	0	0
T196	0	16	0	0
T197	0	34	0	0