Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6929	1			T8	20		T10	20		T12	93
testmodes[AdcCtrlTestmodeNormal]	5472	1			T1	1		T7	1		T8	2
testmodes[AdcCtrlTestmodeLowpower]	5840	1			T1	11		T2	3		T3	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3727	1			T8	19		T10	19		T12	85
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1717	1			T12	6		T19	2		T15	15
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1375	1			T12	2		T15	2		T47	9
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1689	1			T8	1		T10	1		T12	6
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2002	1			T8	1		T9	2		T12	5
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1448	1			T1	1		T12	3		T15	3
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1403	1			T12	1		T15	3		T47	11
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1417	1			T1	1		T10	1		T12	4
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2771	1			T1	9		T2	2		T5	13