---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.adc_ctrl_csr_assert.TlulOOBAddrErr_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.BusySrcReqChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.SrcAckBusyChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.BusySrcReqChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.SrcAckBusyChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	34156488	0	0	912

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AdcKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.AlertsKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	2147483647	70	0	0
tb.dut.IntrKnown	0	0	2147483647	2147483647	0	0
tb.dut.TlOAReadyKnown	0	0	2147483647	2147483647	0	0
tb.dut.TlODValidKnown	0	0	2147483647	2147483647	0	0
tb.dut.WakeKnown	0	0	2147483647	2147483647	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_0_rd_A	0	0	2147483647	2672	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_1_rd_A	0	0	2147483647	2796	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_2_rd_A	0	0	2147483647	2778	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_3_rd_A	0	0	2147483647	2624	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_4_rd_A	0	0	2147483647	2662	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_5_rd_A	0	0	2147483647	2521	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_6_rd_A	0	0	2147483647	2453	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_7_rd_A	0	0	2147483647	2657	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_0_rd_A	0	0	2147483647	2742	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_1_rd_A	0	0	2147483647	2906	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_2_rd_A	0	0	2147483647	2580	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_3_rd_A	0	0	2147483647	2550	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_4_rd_A	0	0	2147483647	2527	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_5_rd_A	0	0	2147483647	2610	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_6_rd_A	0	0	2147483647	2511	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_7_rd_A	0	0	2147483647	2763	0	0
tb.dut.adc_ctrl_csr_assert.adc_en_ctl_rd_A	0	0	2147483647	2397	0	0
tb.dut.adc_ctrl_csr_assert.adc_fsm_rst_rd_A	0	0	2147483647	2002	0	0
tb.dut.adc_ctrl_csr_assert.adc_intr_ctl_rd_A	0	0	2147483647	2550	0	0
tb.dut.adc_ctrl_csr_assert.adc_lp_sample_ctl_rd_A	0	0	2147483647	2193	0	0
tb.dut.adc_ctrl_csr_assert.adc_pd_ctl_rd_A	0	0	2147483647	2307	0	0
tb.dut.adc_ctrl_csr_assert.adc_sample_ctl_rd_A	0	0	2147483647	2091	0	0
tb.dut.adc_ctrl_csr_assert.adc_wakeup_ctl_rd_A	0	0	2147483647	2060	0	0
tb.dut.adc_ctrl_csr_assert.intr_enable_rd_A	0	0	2147483647	2663	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	2147483647	32568928	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	2147483647	4239847	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
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tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
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tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
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tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
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tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
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tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
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tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	2147483647	16835325	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	2147483647	3272	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	2147483647	22600289	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	2147483647	3459276	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	2147483647	3092	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	2147483647	32569022	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	2147483647	4239906	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	2147483647	32569022	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	2147483647	4239906	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	2147483647	4239906	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	2147483647	4239906	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	2147483647	3060	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	2147483647	3464	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	912	912	0	0
tb.dut.u_adc_ctrl_core.MaxFilters_A	0	0	34073079	33758515	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck00_A	0	0	34073079	11084362	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck01_A	0	0	34073079	2447582	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck10_A	0	0	34073079	2320485	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck11_A	0	0	34073079	17906086	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck00_A	0	0	34073079	11331612	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck01_A	0	0	34073079	1450320	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck10_A	0	0	34073079	719395	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck11_A	0	0	34073079	20257188	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck00_A	0	0	34073079	12617787	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck01_A	0	0	34073079	542686	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck10_A	0	0	34073079	405117	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck11_A	0	0	34073079	20192925	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck00_A	0	0	34073079	13873625	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck01_A	0	0	34073079	360490	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck10_A	0	0	34073079	271184	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck11_A	0	0	34073079	19253216	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck00_A	0	0	34073079	12934475	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck01_A	0	0	34073079	11	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck10_A	0	0	34073079	107	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck11_A	0	0	34073079	20823922	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck00_A	0	0	34073079	13668309	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck01_A	0	0	34073079	33621	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck10_A	0	0	34073079	114	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck11_A	0	0	34073079	20056471	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck00_A	0	0	34073079	13279353	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck01_A	0	0	34073079	98117	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck10_A	0	0	34073079	102413	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck11_A	0	0	34073079	20278632	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck00_A	0	0	34073079	13602672	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck01_A	0	0	34073079	105868	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck10_A	0	0	34073079	187271	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck11_A	0	0	34073079	19862704	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.LpSampleCntCfg_M	0	0	30302812	30226549	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrMisMatch_A	0	0	30302812	159940	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrPwrDn_A	0	0	30302812	89070	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpSampleCntCfg_M	0	0	30302812	30226549	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmDebugOut_A	0	0	30302812	30226549	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmStateHwReset_A	0	0	1106	1106	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmStateSwReset_A	0	0	30302812	6231	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.LpSampleCntHwReset_A	0	0	1106	1106	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.LpSampleCntSwReset_A	0	0	30302812	6231	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.NpSampleCntHwReset_A	0	0	1106	1106	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.NpSampleCntSwReset_A	0	0	30302812	6231	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.PwrupTimerCntHwReset_A	0	0	1106	1106	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.PwrupTimerCntSwReset_A	0	0	30302812	6231	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.WakeupTimerCntHwReset_A	0	0	1106	1106	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.WakeupTimerCntSwReset_A	0	0	30302812	6231	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.i_adc_ctrl_intr_o.IntrTKind_A	0	0	747	747	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.SyncReqAckAckNeedsReq	0	0	2147483647	16598	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.SyncReqAckHoldReq	0	0	34073079	16596	0	0
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.DstPulseCheck_A	0	0	2147483647	6465	0	0
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.SrcPulseCheck_M	0	0	34073079	6470	0	0
tb.dut.u_reg.en2addrHit	0	0	2147483647	2356714	0	0
tb.dut.u_reg.reAfterRv	0	0	2147483647	2356714	0	0
tb.dut.u_reg.rePulse	0	0	2147483647	2069169	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.BusySrcReqChk_A	0	0	2147483647	2165018	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.SrcAckBusyChk_A	0	0	2147483647	2087	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2087	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	2088	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	1946	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2099	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.BusySrcReqChk_A	0	0	2147483647	2012024	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.SrcAckBusyChk_A	0	0	2147483647	1949	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1949	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	1950	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	1807	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1961	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.BusySrcReqChk_A	0	0	2147483647	2035923	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.SrcAckBusyChk_A	0	0	2147483647	1995	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1995	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	1995	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	1854	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2007	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.BusySrcReqChk_A	0	0	2147483647	1998603	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.SrcAckBusyChk_A	0	0	2147483647	1928	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1928	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	1929	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	1786	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1940	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.BusySrcReqChk_A	0	0	2147483647	2004451	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.SrcAckBusyChk_A	0	0	2147483647	1948	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1948	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	1949	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	1807	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1961	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.BusySrcReqChk_A	0	0	2147483647	1989633	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.SrcAckBusyChk_A	0	0	2147483647	1930	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1930	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	1931	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	1785	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1942	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.BusySrcReqChk_A	0	0	2147483647	2017513	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.SrcAckBusyChk_A	0	0	2147483647	1978	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1978	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	1979	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	1832	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1988	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.BusySrcReqChk_A	0	0	2147483647	2016100	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.SrcAckBusyChk_A	0	0	2147483647	1964	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1964	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	1965	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	1815	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1975	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.BusySrcReqChk_A	0	0	2147483647	2131817	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.SrcAckBusyChk_A	0	0	2147483647	2108	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2108	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	2109	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	1963	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2121	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.BusySrcReqChk_A	0	0	2147483647	2005788	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.SrcAckBusyChk_A	0	0	2147483647	1974	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1974	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	1975	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	1833	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1985	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.BusySrcReqChk_A	0	0	2147483647	2000322	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.SrcAckBusyChk_A	0	0	2147483647	1981	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1981	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	1982	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	1836	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1991	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.BusySrcReqChk_A	0	0	2147483647	1990826	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.SrcAckBusyChk_A	0	0	2147483647	1962	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1962	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	1963	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	1826	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1975	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.BusySrcReqChk_A	0	0	2147483647	2017306	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.SrcAckBusyChk_A	0	0	2147483647	1979	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1979	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	1979	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	1833	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1991	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.BusySrcReqChk_A	0	0	2147483647	1993288	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.SrcAckBusyChk_A	0	0	2147483647	1974	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1974	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	1975	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	1832	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1986	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.BusySrcReqChk_A	0	0	2147483647	1958165	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.SrcAckBusyChk_A	0	0	2147483647	1948	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1948	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	1948	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	1807	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1958	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.BusySrcReqChk_A	0	0	2147483647	2012321	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.SrcAckBusyChk_A	0	0	2147483647	1991	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1991	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	1992	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	1845	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2004	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	34156488	622666	0	912
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	34156488	622829	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	622837	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	34156488	622555	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	34156488	607473	0	912
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	34156488	614965	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	614970	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	34156488	604952	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	35008352	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	38508	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	38508	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	38524	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	38356	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	38563	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.BusySrcReqChk_A	0	0	2147483647	19072291	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.SrcAckBusyChk_A	0	0	2147483647	20128	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	20128	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	20129	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	19982	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	20139	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.BusySrcReqChk_A	0	0	2147483647	92115	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.SrcAckBusyChk_A	0	0	2147483647	94	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	34156488	3149411	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	3149541	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	34156488	1639056	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	88	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	406	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	13428068	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	14409	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	14409	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	14410	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	14241	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	14448	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	16220427	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	18199	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	18199	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	18200	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	18049	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	18212	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	13468025	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	14388	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	14388	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	14389	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	14217	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	14425	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	1520545	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	1428	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1428	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34156488	1429	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	1292	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1441	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	912	912	0	0
tb.dut.u_reg.u_filter_status_cdc.BusySrcReqChk_A	0	0	2147483647	59522434	0	0
tb.dut.u_reg.u_filter_status_cdc.DstReqKnown_A	0	0	34156488	33805286	0	0
tb.dut.u_reg.u_filter_status_cdc.SrcAckBusyChk_A	0	0	2147483647	65129	0	0
tb.dut.u_reg.u_filter_status_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	34156488	14758	0	912
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	34156488	14819	0	0
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	79948	0	0
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	34156488	79061	0	0
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34156488	64983	0	0
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	65141	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	912	912	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	912	912	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	912	912	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	912	912	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	912	912	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	912	912	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	912	912	0	0
tb.dut.u_reg.wePulse	0	0	2147483647	287545	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	34156488	622666	0	912
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	34156488	607473	0	912
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	34156488	0	0	912
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	34156488	14758	0	912

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2147483647	1103629	1103629	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2147483647	4571	4571	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2147483647	11571	11571	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2147483647	6820	6820	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2147483647	11120	11120	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2147483647	5446	5446	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2147483647	5195	5195	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2147483647	2364	2364	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2147483647	6147	6147	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2147483647	1221227	1221227	842

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2147483647	1103629	1103629	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2147483647	4571	4571	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2147483647	11571	11571	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2147483647	6820	6820	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2147483647	11120	11120	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2147483647	5446	5446	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2147483647	5195	5195	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2147483647	2364	2364	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2147483647	6147	6147	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2147483647	1221227	1221227	842