Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

21

T2

35

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22873

1

T1

21

T2

35

T3

17

auto[ADC_CTRL_FILTER_COND_OUT]

3448

1

T10

13

T15

7

T55

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20782

1

T1

21

T3

17

T5

14

auto[1]

5539

1

T2

35

T6

27

T7

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22273

1

T1

16

T2

35

T3

11

auto[1]

4048

1

T1

5

T3

6

T7

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	3	1			T251	3		-	-		-	-
values[0]	34	1			T156	11		T189	1		T90	1
values[1]	581	1			T109	17		T208	6		T180	1
values[2]	624	1			T1	1		T15	3		T18	12
values[3]	563	1			T155	21		T51	13		T159	15
values[4]	586	1			T1	9		T10	13		T47	5
values[5]	803	1			T12	15		T15	1		T156	5
values[6]	844	1			T12	8		T55	15		T155	22
values[7]	891	1			T8	2		T48	6		T168	10
values[8]	2741	1			T2	35		T6	27		T7	8
values[9]	1331	1			T3	17		T11	14		T15	6
minimum	17320	1			T1	11		T5	14		T8	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	764	1			T156	11		T109	17		T159	1
values[1]	541	1			T1	1		T15	3		T18	12
values[2]	598	1			T10	13		T47	5		T16	2
values[3]	787	1			T1	9		T166	1		T168	10
values[4]	721	1			T12	23		T15	1		T156	5
values[5]	840	1			T55	15		T155	22		T115	1
values[6]	2953	1			T2	35		T6	27		T7	8
values[7]	674	1			T11	14		T16	7		T158	2
values[8]	850	1			T3	17		T15	2		T55	26
values[9]	272	1			T15	4		T159	10		T160	13
minimum	17321	1			T1	11		T5	14		T8	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

4032

1

T1

4

T2

32

T3

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T176	19		T252	14		T181	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T156	1		T109	9		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	1		T18	1		T155	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T15	2		T168	15		T53	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T47	4		T159	1		T224	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T10	1		T16	1		T253	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	5		T166	1		T168	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T112	1		T52	10		T172	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	13		T15	1		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T109	8		T254	1		T176	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T155	10		T115	1		T170	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T55	8		T162	1		T179	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1542	1			T2	35		T6	27		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T48	5		T217	13		T173	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	14		T16	2		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T158	1		T168	10		T109	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T3	11		T15	2		T55	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T17	11		T157	2		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T160	1		T187	16		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T15	3		T159	1		T186	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17182	1			T1	10		T5	14		T8	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T176	20		T107	1		T256	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T156	10		T109	8		T208	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T18	11		T155	10		T51	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T15	1		T53	6		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T47	1		T159	14		T173	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T10	12		T16	1		T253	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	4		T49	5		T203	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T112	9		T52	7		T172	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	10		T156	4		T214	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T109	14		T254	6		T176	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T155	12		T170	8		T54	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T55	7		T179	13		T125	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T7	7		T9	27		T57	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T48	1		T217	15		T173	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T16	5		T224	9		T257	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T109	12		T253	12		T163	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	6		T55	10		T110	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T17	15		T157	13		T163	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T160	12		T187	1		T258	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T15	1		T159	9		T186	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T251	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T189	1		T259	10		T260	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T156	1		T90	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T176	5		T252	14		T261	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T109	9		T208	3		T180	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	1		T18	1		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	2		T168	15		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T155	11		T51	6		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T161	14		T209	16		T181	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	5		T47	4		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T10	1		T16	1		T112	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	8		T15	1		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T109	8		T170	13		T254	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T12	5		T155	10		T170	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T55	8		T162	1		T179	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T8	2		T115	1		T171	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T48	5		T168	10		T217	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1486	1			T2	35		T6	27		T7	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T109	14		T171	11		T253	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	399	1			T3	11		T11	14		T15	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T15	3		T17	11		T157	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T260	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T156	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T176	9		T107	1		T256	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T109	8		T208	3		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T18	11		T173	10		T176	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T15	1		T53	6		T164	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T155	10		T51	7		T159	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T20	3		T85	2		T21	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	4		T47	1		T203	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T10	12		T16	1		T112	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	7		T156	4		T49	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T109	14		T170	17		T254	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	3		T155	12		T170	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T55	7		T179	13		T36	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T214	2		T262	9		T129	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T48	1		T217	15		T173	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	912	1			T7	7		T9	27		T57	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T109	12		T253	12		T188	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	6		T55	10		T16	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T15	1		T17	15		T157	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T176	22		T252	1		T181	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T156	11		T109	9		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	1		T18	12		T155	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T15	3		T168	1		T53	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T47	4		T159	15		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	13		T16	2		T253	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	5		T166	1		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T112	10		T52	13		T172	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	14		T15	1		T156	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T109	15		T254	7		T176	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T155	13		T115	1		T170	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T55	8		T162	1		T179	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T2	3		T6	2		T7	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T48	4		T217	16		T173	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	1		T16	6		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T158	1		T168	1		T109	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T3	7		T15	2		T55	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T17	16		T157	15		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T160	13		T187	2		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T15	3		T159	10		T186	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17321	1			T1	11		T5	14		T8	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T176	17		T252	13		T126	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T109	8		T208	2		T164	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T155	10		T51	2		T161	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T168	14		T53	3		T161	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T47	1		T224	5		T263	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T253	4		T20	3		T21	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	4		T168	9		T49	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T52	4		T172	4		T170	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	9		T264	11		T265	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T109	7		T176	12		T251	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T155	9		T170	8		T54	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T55	7		T179	17		T86	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T2	32		T6	25		T167	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T48	2		T217	12		T173	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T11	13		T16	1		T224	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T168	9		T109	13		T171	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	10		T55	15		T110	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T17	10		T163	6		T187	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T187	15		T266	12		T267	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T15	1		T268	11		T269	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T251	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T189	1		T259	1		T260	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T156	11		T90	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T176	10		T252	1		T261	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T109	9		T208	4		T180	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	1		T18	12		T173	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T15	3		T168	1		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T155	11		T51	11		T159	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T161	2		T209	1		T181	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	5		T47	4		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	13		T16	2		T112	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	9		T15	1		T156	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T109	15		T170	18		T254	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T12	5		T155	13		T170	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T55	8		T162	1		T179	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T8	2		T115	1		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T48	4		T168	1		T217	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T2	3		T6	2		T7	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T109	13		T171	1		T253	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T3	7		T11	1		T15	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	378	1			T15	3		T17	16		T157	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T251	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T259	9		T260	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T176	4		T252	13		T256	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T109	8		T208	2		T164	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T176	13		T164	7		T93	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T168	14		T53	3		T265	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T155	10		T51	2		T224	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T161	12		T209	15		T20	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T1	4		T47	1		T168	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T52	4		T172	4		T253	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	6		T49	3		T270	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T109	7		T170	12		T176	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	3		T155	9		T170	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T55	7		T179	17		T36	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T171	6		T262	10		T129	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T48	2		T168	9		T217	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1161	1			T2	32		T6	25		T167	30
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T109	13		T171	10		T253	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T3	10		T11	13		T55	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T15	1		T17	10		T171	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

auto[0]

4032

1

T1

4

T2

32

T3

10

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

21

T2

35

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23095

1

T1

12

T2

35

T3

17

auto[ADC_CTRL_FILTER_COND_OUT]

3226

1

T1

9

T11

14

T12

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20117

1

T1

20

T5

14

T8

22

auto[1]

6204

1

T1

1

T2

35

T3

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22273

1

T1

16

T2

35

T3

11

auto[1]

4048

1

T1

5

T3

6

T7

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	34	1			T156	11		T171	11		T186	11
values[0]	34	1			T271	14		T272	20		-	-
values[1]	835	1			T55	15		T157	12		T158	1
values[2]	696	1			T16	2		T155	43		T217	28
values[3]	710	1			T8	2		T158	1		T48	6
values[4]	825	1			T12	8		T55	26		T16	7
values[5]	2953	1			T2	35		T6	27		T7	8
values[6]	543	1			T3	17		T47	5		T158	1
values[7]	644	1			T1	1		T18	12		T159	11
values[8]	539	1			T1	9		T10	13		T156	5
values[9]	1188	1			T15	8		T168	25		T49	13
minimum	17320	1			T1	11		T5	14		T8	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1076	1			T55	15		T157	12		T158	1
values[1]	809	1			T16	2		T155	22		T217	28
values[2]	684	1			T16	7		T158	1		T48	6
values[3]	2915	1			T2	35		T6	27		T7	8
values[4]	687	1			T11	14		T12	15		T47	5
values[5]	569	1			T3	17		T15	2		T18	12
values[6]	689	1			T1	10		T168	10		T270	8
values[7]	550	1			T10	13		T15	3		T156	5
values[8]	728	1			T15	5		T156	11		T168	10
values[9]	294	1			T253	25		T170	17		T214	3
minimum	17320	1			T1	11		T5	14		T8	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

4032

1

T1

4

T2

32

T3

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T55	8		T157	1		T155	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T158	1		T166	1		T109	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T16	1		T217	13		T224	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T155	10		T160	1		T270	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T16	2		T158	1		T48	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T52	10		T173	1		T198	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1636	1			T2	35		T6	27		T7	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	5		T55	16		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	8		T47	4		T17	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	14		T208	3		T163	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	11		T109	14		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T15	2		T18	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	1		T270	8		T202	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	5		T168	10		T176	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T10	1		T15	2		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T51	6		T162	1		T188	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T15	1		T156	1		T110	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T15	3		T168	10		T49	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T253	13		T170	9		T214	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T252	14		T21	4		T102	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T55	7		T157	11		T155	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T109	14		T110	10		T172	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T16	1		T217	15		T179	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T155	12		T160	12		T254	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T16	5		T48	1		T112	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T52	7		T173	10		T35	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T7	7		T9	27		T57	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T12	3		T55	10		T164	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	7		T47	1		T17	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T208	3		T163	14		T257	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T3	6		T109	12		T159	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T18	11		T20	3		T127	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T273	11		T36	4		T85	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T1	4		T176	11		T179	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T10	12		T15	1		T156	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T51	7		T188	2		T182	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T156	10		T110	2		T159	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T15	1		T49	5		T173	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T253	12		T170	8		T214	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T21	3		T102	7		T67	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T156	1		T274	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T171	11		T186	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T271	7		T272	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T55	8		T157	1		T176	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T158	1		T166	1		T109	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T16	1		T155	11		T217	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T155	10		T253	5		T275	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T8	2		T158	1		T48	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T52	10		T160	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T16	2		T161	4		T170	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T12	5		T55	16		T198	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1617	1			T2	35		T6	27		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	14		T15	2		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	11		T47	4		T109	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T158	1		T171	13		T208	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	1		T159	1		T270	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T18	1		T159	1		T179	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T10	1		T156	1		T50	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	5		T168	10		T173	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	370	1			T15	3		T168	15		T110	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T15	3		T168	10		T49	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T156	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T186	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T271	7		T272	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T55	7		T157	11		T176	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T109	14		T110	10		T172	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T16	1		T155	10		T217	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T155	12		T253	4		T275	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T48	1		T112	9		T187	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T52	7		T160	12		T173	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T16	5		T170	2		T203	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	3		T55	10		T218	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1031	1			T7	7		T9	27		T12	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T164	9		T257	10		T118	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	6		T47	1		T109	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T208	3		T163	14		T276	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T159	9		T163	6		T176	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T18	11		T179	3		T20	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	12		T156	4		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T1	4		T173	14		T188	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T15	1		T110	2		T159	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T15	1		T49	5		T51	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1