Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

21

T2

35

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22734

1

T1

21

T2

35

T3

17

auto[ADC_CTRL_FILTER_COND_OUT]

3587

1

T12

8

T15

4

T18

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20592

1

T1

20

T3

17

T5

14

auto[1]

5729

1

T1

1

T2

35

T6

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22273

1

T1

16

T2

35

T3

11

auto[1]

4048

1

T1

5

T3

6

T7

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T342	6		T233	2		T271	2
values[0]	50	1			T315	1		T118	3		T256	27
values[1]	833	1			T155	21		T168	20		T115	1
values[2]	640	1			T1	1		T8	2		T15	6
values[3]	639	1			T12	15		T110	14		T159	15
values[4]	2910	1			T1	9		T2	35		T6	27
values[5]	926	1			T157	12		T49	13		T109	43
values[6]	651	1			T15	1		T166	1		T112	10
values[7]	521	1			T15	3		T16	7		T156	11
values[8]	743	1			T3	17		T10	13		T11	14
values[9]	1074	1			T55	15		T156	5		T158	1
minimum	17320	1			T1	11		T5	14		T8	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	954	1			T1	1		T157	3		T155	21
values[1]	703	1			T8	2		T15	6		T110	14
values[2]	673	1			T12	15		T18	12		T158	1
values[3]	3018	1			T1	9		T2	35		T6	27
values[4]	800	1			T15	1		T157	12		T49	13
values[5]	708	1			T156	11		T166	1		T110	23
values[6]	513	1			T3	17		T15	3		T55	26
values[7]	729	1			T10	13		T11	14		T16	2
values[8]	693	1			T55	15		T156	5		T158	1
values[9]	200	1			T52	17		T161	4		T162	1
minimum	17330	1			T1	11		T5	14		T8	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

4032

1

T1

4

T2

32

T3

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	1		T157	1		T155	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T115	1		T173	15		T253	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T8	2		T15	2		T171	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T15	3		T110	12		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T12	8		T214	1		T164	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T18	1		T158	1		T53	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1553	1			T1	5		T2	35		T6	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T12	5		T17	11		T171	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T15	1		T157	1		T49	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T109	14		T159	1		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T156	1		T166	1		T110	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T51	6		T159	1		T161	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	11		T15	2		T55	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T158	1		T155	10		T208	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T10	1		T11	14		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T48	5		T224	18		T188	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T55	8		T158	1		T170	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T156	1		T202	1		T163	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T52	10		T161	4		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T233	1		T343	2		T332	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T168	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T157	2		T155	10		T109	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T173	14		T253	12		T305	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T214	4		T186	8		T263	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T15	1		T110	2		T159	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T12	7		T214	2		T164	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T18	11		T53	6		T54	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T1	4		T7	7		T9	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	3		T17	15		T253	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T157	11		T49	5		T109	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T109	12		T203	1		T164	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T156	10		T110	10		T112	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T51	7		T159	9		T173	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T3	6		T15	1		T55	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T155	12		T208	3		T254	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T10	12		T16	1		T172	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T48	1		T224	9		T188	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T55	7		T170	17		T188	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T156	4		T163	6		T179	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T52	7		T164	9		T102	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T233	1		T343	1		T332	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T342	6		T271	2		T344	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T233	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T315	1		T118	1		T345	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T256	12		T346	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T155	11		T168	10		T264	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T168	10		T115	1		T173	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	1		T8	2		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T15	3		T273	1		T347	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T12	8		T214	1		T164	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T110	12		T159	1		T53	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1506	1			T1	5		T2	35		T6	27
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T12	5		T18	1		T17	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T157	1		T49	8		T109	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T109	14		T159	1		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T15	1		T166	1		T112	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T51	6		T162	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	2		T16	2		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T158	1		T155	10		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T3	11		T10	1		T11	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T224	18		T208	3		T209	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T55	8		T158	1		T52	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T156	1		T48	5		T202	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T344	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T233	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T118	2		T345	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T256	15		T346	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T155	10		T264	17		T179	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T173	14		T253	12		T305	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T157	2		T109	14		T214	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T15	1		T273	11		T128	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T12	7		T214	2		T164	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T110	2		T159	14		T53	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	940	1			T1	4		T7	7		T9	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	3		T18	11		T17	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T157	11		T49	5		T109	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T109	12		T253	4		T203	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T112	9		T170	8		T262	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T51	7		T173	10		T179	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T15	1		T16	5		T156	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T155	12		T159	9		T187	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	6		T10	12		T55	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T224	9		T208	3		T188	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T55	7		T52	7		T170	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T156	4		T48	1		T163	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T1	1		T157	3		T155	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T115	1		T173	15		T253	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T8	2		T15	2		T171	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T15	3		T110	3		T159	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T12	9		T214	3		T164	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T18	12		T158	1		T53	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T1	5		T2	3		T6	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	5		T17	16		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T15	1		T157	12		T49	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T109	13		T159	1		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T156	11		T166	1		T110	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T51	11		T159	10		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T3	7		T15	3		T55	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T158	1		T155	13		T208	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T10	13		T11	1		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T48	4		T224	11		T188	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T55	8		T158	1		T170	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T156	5		T202	1		T163	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T52	13		T161	1		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T233	2		T343	3		T332	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T168	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T155	10		T168	9		T109	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T173	14		T253	12		T305	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T171	6		T263	1		T86	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T15	1		T110	11		T308	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T12	6		T164	7		T278	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T53	3		T54	4		T176	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T1	4		T2	32		T6	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	3		T17	10		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T49	3		T109	8		T161	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T109	13		T198	5		T252	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T110	12		T217	12		T170	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T51	2		T161	9		T179	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T3	10		T55	15		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T155	9		T208	2		T209	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	13		T168	14		T172	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T48	2		T224	16		T176	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T55	7		T170	12		T86	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T163	6		T179	17		T187	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T52	4		T161	3		T164	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T332	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T168	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T342	1		T271	1		T344	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T233	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T315	1		T118	3		T345	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T256	16		T346	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T155	11		T168	1		T264	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T168	1		T115	1		T173	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T1	1		T8	2		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T15	3		T273	12		T347	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	9		T214	3		T164	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T110	3		T159	15		T53	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T1	5		T2	3		T6	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	5		T18	12		T17	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T157	12		T49	10		T109	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T109	13		T159	1		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	1		T166	1		T112	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T51	11		T162	1		T173	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T15	3		T16	6		T156	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T158	1		T155	13		T159	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	7		T10	13		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T224	11		T208	4		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T55	8		T158	1		T52	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T156	5		T48	4		T202	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T342	5		T271	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T345	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T256	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T155	10		T168	9		T264	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T168	9		T173	14		T253	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T109	7		T171	6		T263	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T15	1		T347	9		T348	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T12	6		T164	7		T278	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T110	11		T53	3		T54	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1178	1			T1	4		T2	32		T6	25
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T12	3		T17	10		T171	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T49	3		T109	8		T161	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T109	13		T253	4		T257	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T170	8		T270	7		T262	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T51	2		T198	5		T179	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T16	1		T110	12		T171	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T155	9		T161	9		T187	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	10		T11	13		T55	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T224	16		T208	2		T209	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T55	7		T52	4		T161	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T48	2		T163	6		T176	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

auto[0]

4032

1

T1

4

T2

32

T3

10