Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

21

T2

35

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23239

1

T1

20

T2

35

T5

14

auto[ADC_CTRL_FILTER_COND_OUT]

3082

1

T1

1

T3

17

T15

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20421

1

T1

21

T5

14

T8

22

auto[1]

5900

1

T2

35

T3

17

T6

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22273

1

T1

16

T2

35

T3

11

auto[1]

4048

1

T1

5

T3

6

T7

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	24	1			T156	11		T232	5		T335	8
values[0]	85	1			T168	10		T264	25		T265	10
values[1]	744	1			T11	14		T110	23		T162	1
values[2]	2770	1			T2	35		T6	27		T7	8
values[3]	636	1			T1	1		T15	1		T157	3
values[4]	605	1			T15	3		T168	10		T109	22
values[5]	721	1			T8	2		T16	2		T156	5
values[6]	840	1			T1	9		T12	8		T55	15
values[7]	847	1			T47	5		T158	2		T168	15
values[8]	609	1			T10	13		T16	7		T158	1
values[9]	1120	1			T3	17		T15	6		T17	26
minimum	17320	1			T1	11		T5	14		T8	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	914	1			T11	14		T166	1		T168	10
values[1]	2907	1			T1	1		T2	35		T6	27
values[2]	510	1			T15	1		T168	10		T109	26
values[3]	722	1			T15	3		T156	5		T155	22
values[4]	764	1			T8	2		T16	2		T161	10
values[5]	816	1			T1	9		T12	8		T55	15
values[6]	815	1			T47	5		T157	12		T158	1
values[7]	508	1			T10	13		T15	4		T16	7
values[8]	815	1			T3	17		T156	11		T49	13
values[9]	229	1			T15	2		T17	26		T188	3
minimum	17321	1			T1	11		T5	14		T8	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

4032

1

T1

4

T2

32

T3

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T11	14		T166	1		T168	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T110	13		T162	1		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1605	1			T2	35		T6	27		T7	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	1		T18	1		T159	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T168	10		T115	1		T224	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T15	1		T109	14		T171	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T15	2		T155	10		T109	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T156	1		T50	2		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T8	2		T16	1		T173	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T161	10		T174	1		T181	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T1	5		T12	5		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T55	8		T168	15		T171	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T47	4		T157	1		T155	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T158	1		T48	5		T52	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	1		T158	1		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T15	3		T16	2		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T110	12		T161	4		T214	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	11		T156	1		T49	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T15	2		T17	11		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T274	1		T266	13		T349	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T181	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T160	12		T170	2		T54	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T110	10		T264	4		T308	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T7	7		T9	27		T12	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T18	11		T159	14		T173	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T53	6		T176	11		T186	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T109	12		T172	8		T36	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T15	1		T155	12		T109	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T156	4		T50	1		T276	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T16	1		T173	14		T203	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T275	3		T276	12		T310	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T1	4		T12	3		T208	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T55	7		T179	17		T36	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T47	1		T157	11		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T48	1		T52	7		T170	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T10	12		T214	6		T256	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	1		T16	5		T112	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T110	2		T214	2		T164	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	6		T156	10		T49	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T17	15		T188	2		T304	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T349	12		T350	12		T312	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T232	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T156	1		T335	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T168	10		T264	12		T227	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T265	10		T258	1		T344	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	14		T174	1		T163	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T110	13		T162	1		T180	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1580	1			T2	35		T6	27		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T18	1		T159	1		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T157	1		T51	6		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	1		T15	1		T109	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T15	2		T168	10		T109	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T36	4		T276	1		T310	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T8	2		T16	1		T155	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T156	1		T50	2		T161	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	5		T12	5		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T55	8		T161	15		T198	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T47	4		T158	1		T208	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T158	1		T168	15		T52	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T10	1		T158	1		T155	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T16	2		T48	5		T176	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	363	1			T15	2		T17	11		T110	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T3	11		T15	3		T49	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T232	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T156	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T264	13		T351	2		T352	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T258	6		T344	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T163	14		T273	11		T127	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T110	10		T264	4		T308	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	963	1			T7	7		T9	27		T12	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T18	11		T173	10		T164	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T157	2		T51	7		T253	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T109	12		T159	14		T172	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T15	1		T109	14		T53	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T36	4		T276	8		T310	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T16	1		T155	12		T224	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T156	4		T50	1		T275	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	4		T12	3		T157	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T55	7		T179	17		T41	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T47	1		T208	3		T188	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T52	7		T170	8		T305	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T10	12		T155	10		T109	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T16	5		T48	1		T176	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T17	15		T110	2		T214	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T3	6		T15	1		T49	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T11	1		T166	1		T168	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T110	11		T162	1		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T2	3		T6	2		T7	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	1		T18	12		T159	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T168	1		T115	1		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T15	1		T109	13		T171	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T15	3		T155	13		T109	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T156	5		T50	2		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T8	2		T16	2		T173	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T161	1		T174	1		T181	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T1	5		T12	5		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T55	8		T168	1		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T47	4		T157	12		T155	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T158	1		T48	4		T52	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T10	13		T158	1		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T15	3		T16	6		T112	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T110	3		T161	1		T214	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	7		T156	11		T49	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T15	2		T17	16		T188	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T274	1		T266	1		T349	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T181	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	13		T168	9		T170	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T110	12		T264	11		T265	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T2	32		T6	25		T12	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T164	3		T265	2		T238	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T168	9		T224	5		T53	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T109	13		T171	10		T172	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T155	9		T109	7		T171	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T50	1		T86	3		T218	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T173	14		T262	11		T85	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T161	9		T275	3		T310	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	4		T12	3		T208	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T55	7		T168	14		T171	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T47	1		T155	10		T109	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T48	2		T52	4		T170	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T252	13		T256	11		T285	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T15	1		T16	1		T278	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T110	11		T161	3		T164	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	10		T49	3		T187	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T17	10		T86	5		T294	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T266	12		T350	13		T326	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T232	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T156	11		T335	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T168	1		T264	14		T227	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T265	1		T258	7		T344	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	1		T174	1		T163	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T110	11		T162	1		T180	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T2	3		T6	2		T7	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T18	12		T159	1		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T157	3		T51	11		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	1		T15	1		T109	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T15	3		T168	1		T109	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T36	5		T276	9		T310	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	2		T16	2		T155	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T156	5		T50	2		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T1	5		T12	5		T157	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T55	8		T161	1		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T47	4		T158	1		T208	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T158	1		T168	1		T52	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	13		T158	1		T155	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T16	6		T48	4		T176	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T15	2		T17	16		T110	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T3	7		T15	3		T49	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T232	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T335	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T168	9		T264	11		T351	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T265	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	13		T163	11		T219	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T110	12		T264	11		T89	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T2	32		T6	25		T12	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T164	3		T232	15		T280	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T51	2		T253	12		T270	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T109	13		T171	10		T172	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T168	9		T109	7		T171	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T36	3		T310	10		T218	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T155	9		T224	11		T262	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T50	1		T161	9		T275	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	4		T12	3		T173	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T55	7		T161	14		T198	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T47	1		T208	2		T176	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T168	14		T52	4		T171	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T155	10		T109	8		T217	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T16	1		T48	2		T176	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T17	10		T110	11		T161	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	10		T15	1		T49	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

auto[0]

4032

1

T1

4

T2

32

T3

10