Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

21

T2

35

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22618

1

T1

21

T2

35

T5

14

auto[ADC_CTRL_FILTER_COND_OUT]

3703

1

T3

17

T10

13

T11

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20672

1

T1

12

T5

14

T8

24

auto[1]

5649

1

T1

9

T2

35

T3

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22273

1

T1

16

T2

35

T3

11

auto[1]

4048

1

T1

5

T3

6

T7

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	316	1			T8	2		T18	12		T158	1
values[0]	25	1			T279	14		T269	10		T353	1
values[1]	706	1			T1	1		T12	15		T168	10
values[2]	670	1			T15	5		T158	1		T168	15
values[3]	529	1			T156	11		T49	13		T110	14
values[4]	730	1			T17	26		T155	21		T168	10
values[5]	2999	1			T2	35		T6	27		T7	8
values[6]	577	1			T1	9		T12	8		T47	5
values[7]	772	1			T3	17		T15	4		T55	15
values[8]	627	1			T11	14		T15	1		T16	2
values[9]	1050	1			T10	13		T55	26		T16	7
minimum	17320	1			T1	11		T5	14		T8	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	779	1			T12	15		T115	1		T173	29
values[1]	595	1			T15	5		T158	1		T168	15
values[2]	605	1			T156	11		T168	10		T49	13
values[3]	2936	1			T2	35		T6	27		T7	8
values[4]	744	1			T109	26		T110	23		T217	28
values[5]	749	1			T1	9		T3	17		T12	8
values[6]	547	1			T11	14		T15	5		T55	15
values[7]	852	1			T55	26		T16	2		T157	15
values[8]	911	1			T8	2		T10	13		T18	12
values[9]	141	1			T171	7		T296	9		T354	36
minimum	17462	1			T1	12		T5	14		T8	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

4032

1

T1

4

T2

32

T3

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T12	8		T173	15		T209	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T115	1		T338	1		T257	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	2		T158	1		T168	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T15	2		T159	1		T172	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T49	8		T109	9		T170	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T156	1		T168	10		T110	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1554	1			T2	35		T6	27		T7	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T155	11		T224	6		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T110	13		T217	13		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T109	14		T173	1		T54	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	5		T12	5		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T3	11		T47	4		T161	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T15	1		T158	1		T253	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	14		T15	3		T55	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T16	1		T157	1		T48	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T55	16		T157	1		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T8	2		T158	1		T155	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	1		T18	1		T16	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T171	7		T296	3		T319	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T354	20		T297	14		T355	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17229	1			T1	11		T5	14		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T168	10		T292	13		T279	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	7		T173	14		T164	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T257	5		T275	9		T36	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T15	1		T53	6		T257	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T159	14		T172	8		T188	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T49	5		T109	8		T170	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T156	10		T110	2		T179	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T7	7		T9	27		T17	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T155	10		T160	12		T208	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T110	10		T217	15		T159	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T109	12		T173	10		T54	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	4		T12	3		T156	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	6		T47	1		T253	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T253	4		T214	2		T203	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T15	1		T55	7		T112	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T16	1		T157	2		T48	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T55	10		T157	11		T176	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T155	12		T109	14		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	12		T18	11		T16	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T296	6		T301	15		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T354	16		T297	12		T345	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	1		T8	2		T10	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T297	2		T356	13		T357	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T8	2		T158	1		T50	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T18	1		T171	13		T202	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T269	10		T353	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T279	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	1		T12	8		T173	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T168	10		T115	1		T338	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T15	2		T158	1		T168	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	2		T159	1		T172	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T49	8		T254	1		T257	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T156	1		T110	12		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T17	11		T109	9		T52	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T155	11		T168	10		T224	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1530	1			T2	35		T6	27		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T109	14		T173	1		T54	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T1	5		T12	5		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T47	4		T161	15		T186	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T158	1		T214	1		T203	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T3	11		T15	3		T55	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T15	1		T16	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	14		T157	1		T162	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T155	10		T48	5		T109	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T10	1		T55	16		T16	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T50	1		T218	10		T296	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T18	11		T187	7		T354	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T12	7		T173	14		T164	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T257	5		T275	9		T36	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T15	1		T53	6		T257	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T159	14		T172	8		T188	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T49	5		T254	6		T257	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T156	10		T110	2		T264	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T17	15		T109	8		T52	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T155	10		T160	12		T208	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	972	1			T7	7		T9	27		T57	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T109	12		T173	10		T54	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T1	4		T12	3		T156	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T47	1		T186	8		T36	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T214	2		T203	1		T305	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	6		T15	1		T55	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T16	1		T157	2		T51	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T157	11		T176	11		T186	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T155	12		T48	1		T109	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T10	12		T55	10		T16	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	9		T173	15		T209	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T115	1		T338	1		T257	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	3		T158	1		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	2		T159	15		T172	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T49	10		T109	9		T170	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T156	11		T168	1		T110	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T2	3		T6	2		T7	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T155	11		T224	1		T160	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T110	11		T217	16		T159	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T109	13		T173	11		T54	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	5		T12	5		T156	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	7		T47	4		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T158	1		T253	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	1		T15	3		T55	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T16	2		T157	3		T48	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T55	11		T157	12		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T8	2		T158	1		T155	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T10	13		T18	12		T16	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T171	1		T296	7		T319	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T354	17		T297	13		T355	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17332	1			T1	12		T5	14		T8	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T168	1		T292	1		T279	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	6		T173	14		T209	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T257	2		T275	8		T36	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T168	14		T53	3		T257	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T172	4		T164	3		T264	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T49	3		T109	8		T170	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T168	9		T110	11		T179	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T2	32		T6	25		T17	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T155	10		T224	5		T208	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T110	12		T217	12		T308	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T109	13		T54	4		T278	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	4		T12	3		T161	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	10		T47	1		T161	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T253	4		T305	9		T265	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	13		T15	1		T55	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T48	2		T51	2		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T55	15		T270	11		T176	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T155	9		T109	7		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T16	1		T171	12		T187	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T171	6		T296	2		T319	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T354	19		T297	13		T345	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T269	24		T267	4		T303	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T168	9		T292	12		T279	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T8	2		T158	1		T50	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T18	12		T171	1		T202	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T269	1		T353	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T279	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	1		T12	9		T173	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T168	1		T115	1		T338	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	3		T158	1		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T15	2		T159	15		T172	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T49	10		T254	7		T257	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T156	11		T110	3		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T17	16		T109	9		T52	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T155	11		T168	1		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T2	3		T6	2		T7	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T109	13		T173	11		T54	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	5		T12	5		T156	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T47	4		T161	1		T186	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T158	1		T214	3		T203	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T3	7		T15	3		T55	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T15	1		T16	2		T157	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	1		T157	12		T162	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T155	13		T48	4		T109	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T10	13		T55	11		T16	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T50	1		T89	2		T90	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T171	12		T187	10		T354	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T269	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T279	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	6		T173	14		T209	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T168	9		T257	2		T275	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T168	14		T53	3		T257	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T172	4		T164	3		T179	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T49	3		T257	13		T262	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T110	11		T264	11		T284	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T17	10		T109	8		T52	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T155	10		T168	9		T224	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T2	32		T6	25		T167	30
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T109	13		T54	4		T278	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T1	4		T12	3		T170	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T47	1		T161	14		T36	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T305	9		T85	7		T256	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	10		T15	1		T55	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T51	2		T171	10		T161	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T11	13		T270	11		T176	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T155	9		T48	2		T109	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T55	15		T16	1		T20	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

auto[0]

4032

1

T1

4

T2

32

T3

10