Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

21

T2

35

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20514

1

T1

21

T5

14

T8

22

auto[ADC_CTRL_FILTER_COND_OUT]

5807

1

T2

35

T3

17

T6

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20572

1

T1

12

T3

17

T5

14

auto[1]

5749

1

T1

9

T2

35

T6

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22273

1

T1

16

T2

35

T3

11

auto[1]

4048

1

T1

5

T3

6

T7

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	85	1			T55	26		T274	15		T266	13
values[0]	83	1			T15	2		T349	13		T314	8
values[1]	574	1			T1	9		T12	8		T16	9
values[2]	709	1			T55	15		T157	12		T171	13
values[3]	743	1			T18	12		T110	14		T115	1
values[4]	792	1			T1	1		T11	14		T12	15
values[5]	754	1			T10	13		T17	26		T158	2
values[6]	838	1			T3	17		T155	22		T166	1
values[7]	594	1			T8	2		T15	5		T109	22
values[8]	539	1			T168	10		T109	26		T159	10
values[9]	3290	1			T2	35		T6	27		T7	8
minimum	17320	1			T1	11		T5	14		T8	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	901	1			T1	9		T12	8		T55	15
values[1]	2810	1			T2	35		T6	27		T7	8
values[2]	1004	1			T11	14		T12	15		T18	12
values[3]	647	1			T1	1		T47	5		T156	5
values[4]	713	1			T10	13		T17	26		T158	1
values[5]	732	1			T3	17		T158	1		T155	22
values[6]	634	1			T8	2		T15	5		T109	26
values[7]	599	1			T168	10		T51	13		T159	10
values[8]	751	1			T15	3		T55	26		T158	1
values[9]	198	1			T266	13		T351	9		T251	3
minimum	17332	1			T1	11		T5	14		T8	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

4032

1

T1

4

T2

32

T3

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T1	5		T156	1		T50	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T12	5		T55	8		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T170	9		T179	18		T275	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1553	1			T2	35		T6	27		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T12	8		T18	1		T254	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T11	14		T109	9		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	1		T157	1		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T47	4		T156	1		T110	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T158	1		T49	8		T171	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	1		T17	11		T48	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T170	6		T174	1		T164	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	11		T158	1		T155	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T15	3		T109	14		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	2		T15	1		T112	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T168	10		T51	6		T53	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T159	1		T214	1		T164	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	2		T55	16		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T155	11		T168	15		T162	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T251	3		T287	8		T339	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T266	13		T351	5		T336	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17186	1			T1	10		T5	14		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T15	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T1	4		T156	10		T50	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	3		T55	7		T16	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T170	8		T179	13		T275	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	956	1			T7	7		T9	27		T57	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T12	7		T18	11		T254	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T109	8		T188	10		T176	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T157	2		T172	8		T253	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T47	1		T156	4		T110	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T49	5		T159	14		T214	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T10	12		T17	15		T48	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T170	2		T164	9		T262	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	6		T155	12		T109	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T15	1		T109	12		T224	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T112	9		T305	10		T275	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T51	7		T53	6		T254	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T159	9		T214	2		T164	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T15	1		T55	10		T52	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T155	10		T186	21		T36	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T287	9		T339	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T351	4		T336	13		T24	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	1		T8	2		T10	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T55	16		T287	8		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T274	1		T266	13		T24	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T349	1		T271	12		T358	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T15	2		T314	1		T335	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	5		T156	1		T50	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	5		T16	3		T168	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T171	13		T264	12		T179	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T55	8		T157	1		T209	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T18	1		T170	9		T254	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T110	12		T115	1		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T1	1		T12	8		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	14		T47	4		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T158	1		T49	8		T171	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T10	1		T17	11		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T115	1		T159	1		T224	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	11		T155	10		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T15	3		T161	15		T174	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	2		T15	1		T109	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T168	10		T109	14		T224	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T159	1		T214	1		T315	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T15	2		T158	1		T51	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1713	1			T2	35		T6	27		T7	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T55	10		T287	9		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T274	14		T24	1		T359	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T349	12		T271	12		T281	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T314	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T1	4		T156	10		T50	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	3		T16	6		T170	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T264	13		T179	13		T125	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T55	7		T157	11		T54	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T18	11		T170	8		T254	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T110	2		T176	21		T263	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	7		T157	2		T172	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T47	1		T156	4		T109	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T49	5		T253	12		T214	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T10	12		T17	15		T48	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T159	14		T170	2		T164	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	6		T155	12		T110	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T15	1		T164	9		T85	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T109	14		T112	9		T275	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T109	12		T224	9		T20	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T159	9		T214	2		T275	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T15	1		T51	7		T52	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1099	1			T7	7		T9	27		T57	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	5		T156	11		T50	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	5		T55	8		T16	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T170	9		T179	14		T275	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1289	1			T2	3		T6	2		T7	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T12	9		T18	12		T254	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T11	1		T109	9		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	1		T157	3		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T47	4		T156	5		T110	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T158	1		T49	10		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T10	13		T17	16		T48	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T170	3		T174	1		T164	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T3	7		T158	1		T155	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T15	3		T109	13		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	2		T15	1		T112	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T168	1		T51	11		T53	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T159	10		T214	3		T164	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T15	3		T55	11		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T155	11		T168	1		T162	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T251	1		T287	10		T339	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T266	1		T351	6		T336	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17326	1			T1	11		T5	14		T8	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T15	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	4		T50	1		T171	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	3		T55	7		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T170	8		T179	17		T275	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1220	1			T2	32		T6	25		T167	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	6		T179	23		T86	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	13		T109	8		T176	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T172	4		T253	16		T198	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T47	1		T110	11		T161	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T49	3		T171	10		T224	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T17	10		T48	2		T171	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T170	5		T164	3		T262	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	10		T155	9		T109	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T15	1		T109	13		T224	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T305	9		T275	3		T36	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T168	9		T51	2		T53	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T164	7		T187	15		T265	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T55	15		T52	4		T270	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T155	10		T168	14		T36	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T251	2		T287	7		T339	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T266	12		T351	3		T24	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T312	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T55	11		T287	10		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T274	15		T266	1		T24	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T349	13		T271	13		T358	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T15	2		T314	8		T335	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T1	5		T156	11		T50	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	5		T16	8		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T171	1		T264	14		T179	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T55	8		T157	12		T209	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T18	12		T170	9		T254	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T110	3		T115	1		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	1		T12	9		T157	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T11	1		T47	4		T156	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T158	1		T49	10		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T10	13		T17	16		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T115	1		T159	15		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T3	7		T155	13		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T15	3		T161	1		T174	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	2		T15	1		T109	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T168	1		T109	13		T224	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T159	10		T214	3		T315	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T15	3		T158	1		T51	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1465	1			T2	3		T6	2		T7	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T55	15		T287	7		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T266	12		T24	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T271	11		T358	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T335	3		T360	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	4		T50	1		T161	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	3		T16	1		T168	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T171	12		T264	11		T179	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T55	7		T209	15		T54	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T170	8		T179	23		T275	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T110	11		T176	16		T263	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	6		T172	4		T253	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	13		T47	1		T109	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T49	3		T171	10		T253	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	10		T48	2		T161	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T224	5		T170	5		T164	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	10		T155	9		T110	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T15	1		T161	14		T85	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T109	7		T275	8		T310	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T168	9		T109	13		T224	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T265	9		T275	3		T35	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T51	2		T52	4		T53	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1347	1			T2	32		T6	25		T155	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

auto[0]

4032

1

T1

4

T2

32

T3

10