Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

21

T2

35

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23307

1

T1

20

T2

35

T5

14

auto[ADC_CTRL_FILTER_COND_OUT]

3014

1

T1

1

T3

17

T15

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20422

1

T1

21

T5

14

T8

22

auto[1]

5899

1

T2

35

T3

17

T6

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22273

1

T1

16

T2

35

T3

11

auto[1]

4048

1

T1

5

T3

6

T7

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	312	1			T3	17		T15	2		T49	13
values[0]	35	1			T168	10		T265	10		T227	1
values[1]	800	1			T11	14		T110	23		T160	13
values[2]	2744	1			T2	35		T6	27		T7	8
values[3]	658	1			T1	1		T15	1		T157	3
values[4]	603	1			T15	3		T168	10		T109	22
values[5]	764	1			T8	2		T16	2		T156	5
values[6]	792	1			T1	9		T12	8		T55	15
values[7]	833	1			T47	5		T157	12		T158	1
values[8]	622	1			T10	13		T16	7		T158	1
values[9]	838	1			T15	4		T17	26		T156	11
minimum	17320	1			T1	11		T5	14		T8	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	615	1			T166	1		T110	23		T160	13
values[1]	2872	1			T2	35		T6	27		T7	8
values[2]	594	1			T1	1		T15	1		T168	10
values[3]	658	1			T15	3		T156	5		T155	22
values[4]	720	1			T8	2		T16	2		T50	3
values[5]	879	1			T1	9		T12	8		T55	15
values[6]	796	1			T47	5		T157	12		T155	21
values[7]	624	1			T10	13		T15	4		T16	7
values[8]	794	1			T3	17		T15	2		T156	11
values[9]	156	1			T17	26		T349	13		T185	1
minimum	17613	1			T1	11		T5	14		T8	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

4032

1

T1

4

T2

32

T3

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T166	1		T160	1		T170	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T110	13		T180	1		T202	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1591	1			T2	35		T6	27		T7	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T18	1		T159	2		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T168	10		T109	8		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	1		T15	1		T109	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T15	2		T155	10		T171	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T156	1		T37	3		T86	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T8	2		T16	1		T173	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T50	2		T161	10		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T1	5		T12	5		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T55	8		T158	1		T168	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T47	4		T157	1		T155	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T48	5		T52	10		T270	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	1		T158	1		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T15	3		T16	2		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T15	2		T110	12		T161	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	11		T156	1		T49	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T17	11		T271	2		T325	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T349	1		T185	1		T343	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17264	1			T1	10		T5	14		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T162	1		T181	1		T308	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T160	12		T170	2		T54	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T110	10		T264	4		T258	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T7	7		T9	27		T12	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T18	11		T159	14		T173	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T109	14		T53	6		T176	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T109	12		T172	8		T36	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T15	1		T155	12		T224	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T156	4		T276	8		T310	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T16	1		T173	14		T203	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T50	1		T275	3		T36	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	4		T12	3		T208	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T55	7		T170	8		T179	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T47	1		T157	11		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T48	1		T52	7		T176	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T10	12		T214	6		T256	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T15	1		T16	5		T182	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T110	2		T214	2		T188	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	6		T156	10		T49	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T17	15		T325	12		T339	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T349	12		T350	12		T312	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	1		T8	2		T10	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T308	12		T286	6		T361	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T15	2		T275	9		T232	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T3	11		T49	8		T349	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T168	10		T227	1		T351	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T265	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	14		T160	1		T170	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T110	13		T162	1		T180	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1567	1			T2	35		T6	27		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T18	1		T159	1		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T157	1		T51	6		T224	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	1		T15	1		T109	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T15	2		T168	10		T109	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T36	4		T276	1		T310	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T8	2		T16	1		T155	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T156	1		T50	2		T161	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	5		T12	5		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T55	8		T161	15		T179	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T47	4		T157	1		T208	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T158	1		T168	15		T52	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T10	1		T158	1		T155	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T16	2		T48	5		T176	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T17	11		T110	12		T161	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T15	3		T156	1		T112	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T275	9		T232	2		T296	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T3	6		T49	5		T349	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T351	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T160	12		T170	2		T163	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T110	10		T308	12		T258	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	950	1			T7	7		T9	27		T12	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T18	11		T173	10		T164	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T157	2		T51	7		T253	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T109	12		T159	14		T172	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T15	1		T109	14		T53	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T36	4		T276	8		T310	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T16	1		T155	12		T224	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T156	4		T50	1		T275	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	4		T12	3		T173	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T55	7		T179	17		T41	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T47	1		T157	11		T208	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T52	7		T170	8		T305	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T10	12		T155	10		T109	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T16	5		T48	1		T176	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T17	15		T110	2		T214	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T15	1		T156	10		T112	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T166	1		T160	13		T170	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T110	11		T180	1		T202	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T2	3		T6	2		T7	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T18	12		T159	16		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T168	1		T109	15		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	1		T15	1		T109	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T15	3		T155	13		T171	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T156	5		T37	3		T86	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T8	2		T16	2		T173	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T50	2		T161	1		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T1	5		T12	5		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T55	8		T158	1		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T47	4		T157	12		T155	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T48	4		T52	13		T270	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	13		T158	1		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T15	3		T16	6		T182	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T15	2		T110	3		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	7		T156	11		T49	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T17	16		T271	1		T325	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T349	13		T185	1		T343	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17383	1			T1	11		T5	14		T8	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T162	1		T181	1		T308	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T170	5		T54	4		T163	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T110	12		T264	11		T265	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T2	32		T6	25		T12	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T164	3		T265	2		T279	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T168	9		T109	7		T224	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T109	13		T171	10		T172	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T155	9		T171	12		T224	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T86	3		T310	10		T218	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T173	14		T262	11		T277	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T50	1		T161	9		T275	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	4		T12	3		T208	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T55	7		T168	14		T171	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T47	1		T155	10		T109	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T48	2		T52	4		T270	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T252	13		T256	11		T232	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T15	1		T16	1		T278	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T110	11		T161	3		T164	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	10		T49	3		T187	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T17	10		T271	1		T325	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T350	13		T326	14		T312	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T11	13		T168	9		T351	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T308	13		T286	5		T361	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T15	2		T275	10		T232	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T3	7		T49	10		T349	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T168	1		T227	1		T351	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T265	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T11	1		T160	13		T170	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T110	11		T162	1		T180	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T2	3		T6	2		T7	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T18	12		T159	1		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T157	3		T51	11		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	1		T15	1		T109	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T15	3		T168	1		T109	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T36	5		T276	9		T310	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T8	2		T16	2		T155	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T156	5		T50	2		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T1	5		T12	5		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T55	8		T161	1		T179	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T47	4		T157	12		T208	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T158	1		T168	1		T52	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T10	13		T158	1		T155	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T16	6		T48	4		T176	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T17	16		T110	3		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	3		T156	11		T112	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T275	8		T232	2		T296	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T3	10		T49	3		T233	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T168	9		T351	3		T362	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T265	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	13		T170	5		T163	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T110	12		T89	10		T308	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T2	32		T6	25		T12	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T164	3		T264	11		T232	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T51	2		T224	5		T253	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T109	13		T171	10		T172	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T168	9		T109	7		T171	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T36	3		T310	10		T218	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T155	9		T224	11		T262	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T50	1		T161	9		T275	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	4		T12	3		T173	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T55	7		T161	14		T179	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T47	1		T208	2		T176	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T168	14		T52	4		T171	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T155	10		T109	8		T217	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T16	1		T48	2		T176	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T17	10		T110	11		T161	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T15	1		T187	10		T266	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

auto[0]

4032

1

T1

4

T2

32

T3

10