Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

21

T2

35

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22699

1

T1

21

T2

35

T5

14

auto[ADC_CTRL_FILTER_COND_OUT]

3622

1

T3

17

T12

8

T15

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20620

1

T1

20

T3

17

T5

14

auto[1]

5701

1

T1

1

T2

35

T6

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22273

1

T1

16

T2

35

T3

11

auto[1]

4048

1

T1

5

T3

6

T7

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	292	1			T55	15		T170	30		T188	3
values[0]	34	1			T315	1		T256	27		T345	5
values[1]	823	1			T1	1		T155	21		T168	20
values[2]	635	1			T8	2		T15	6		T157	3
values[3]	701	1			T12	15		T158	1		T159	15
values[4]	2929	1			T1	9		T2	35		T6	27
values[5]	837	1			T15	1		T157	12		T49	13
values[6]	650	1			T166	1		T112	10		T51	13
values[7]	543	1			T15	3		T16	7		T156	11
values[8]	750	1			T3	17		T10	13		T11	14
values[9]	807	1			T156	5		T158	1		T48	6
minimum	17320	1			T1	11		T5	14		T8	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	695	1			T1	1		T157	3		T115	1
values[1]	677	1			T8	2		T15	6		T109	22
values[2]	647	1			T12	15		T18	12		T158	1
values[3]	3077	1			T1	9		T2	35		T6	27
values[4]	763	1			T15	1		T157	12		T49	13
values[5]	682	1			T156	11		T158	1		T166	1
values[6]	541	1			T3	17		T15	3		T55	26
values[7]	759	1			T10	13		T11	14		T16	2
values[8]	780	1			T55	15		T156	5		T158	1
values[9]	107	1			T164	13		T294	11		T102	14
minimum	17593	1			T1	11		T5	14		T8	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

4032

1

T1

4

T2

32

T3

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	1		T157	1		T315	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T115	1		T173	15		T305	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	2		T15	2		T109	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T15	3		T110	12		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T12	8		T214	1		T164	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T18	1		T158	1		T53	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1569	1			T1	5		T2	35		T6	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T12	5		T17	11		T171	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T15	1		T157	1		T49	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T109	14		T159	1		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T156	1		T166	1		T110	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T158	1		T51	6		T217	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T15	2		T55	16		T16	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	11		T155	10		T161	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T10	1		T11	14		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T48	5		T224	18		T208	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T55	8		T158	1		T52	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T156	1		T202	1		T163	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T164	4		T294	11		T102	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T343	2		T332	14		T304	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17265	1			T1	10		T5	14		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T168	10		T253	13		T36	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T157	2		T85	5		T23	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T173	14		T305	10		T41	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T109	14		T214	4		T186	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T15	1		T110	2		T159	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T12	7		T214	2		T164	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T18	11		T53	6		T54	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T1	4		T7	7		T9	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	3		T17	15		T253	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T157	11		T49	5		T109	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T109	12		T203	1		T164	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T156	10		T110	10		T112	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T51	7		T217	15		T159	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T15	1		T55	10		T16	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	6		T155	12		T254	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T10	12		T16	1		T172	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T48	1		T224	9		T208	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T55	7		T52	7		T170	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T156	4		T163	6		T179	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T164	9		T102	7		T364	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T343	1		T332	13		T304	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	1		T8	2		T10	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T253	12		T36	8		T128	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T55	8		T170	13		T188	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T238	10		T232	3		T294	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T315	1		T345	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T256	12		T365	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	1		T155	11		T168	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T168	10		T115	1		T173	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	2		T15	2		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T15	3		T110	12		T273	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T12	8		T214	1		T164	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T158	1		T159	1		T53	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T1	5		T2	35		T6	27
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T12	5		T18	1		T17	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T15	1		T157	1		T49	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T109	14		T159	1		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T166	1		T112	1		T170	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T51	6		T162	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T15	2		T16	2		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T158	1		T155	10		T217	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T10	1		T11	14		T55	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	11		T224	18		T208	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T158	1		T52	10		T161	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T156	1		T48	5		T202	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T55	7		T170	17		T188	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T238	10		T232	2		T343	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T345	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T256	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T155	10		T264	17		T179	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T173	14		T253	12		T305	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T157	2		T109	14		T214	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T15	1		T110	2		T273	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T12	7		T214	2		T164	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T159	14		T53	6		T54	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T1	4		T7	7		T9	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	3		T18	11		T17	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T157	11		T49	5		T109	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T109	12		T203	1		T164	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T112	9		T170	8		T262	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T51	7		T173	10		T179	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T15	1		T16	5		T156	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T155	12		T217	15		T159	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T10	12		T55	10		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	6		T224	9		T208	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T52	7		T164	9		T262	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T156	4		T48	1		T163	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	1		T157	3		T315	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T115	1		T173	15		T305	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T8	2		T15	2		T109	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T15	3		T110	3		T159	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T12	9		T214	3		T164	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T18	12		T158	1		T53	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T1	5		T2	3		T6	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	5		T17	16		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T15	1		T157	12		T49	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T109	13		T159	1		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T156	11		T166	1		T110	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T158	1		T51	11		T217	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T15	3		T55	11		T16	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	7		T155	13		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T10	13		T11	1		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T48	4		T224	11		T208	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T55	8		T158	1		T52	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T156	5		T202	1		T163	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T164	10		T294	1		T102	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T343	3		T332	14		T304	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17397	1			T1	11		T5	14		T8	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T168	1		T253	13		T36	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T85	2		T23	2		T256	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T173	14		T305	9		T265	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T109	7		T171	6		T263	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T15	1		T110	11		T308	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T12	6		T164	7		T278	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T53	3		T54	4		T176	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T1	4		T2	32		T6	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T12	3		T17	10		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T49	3		T109	8		T270	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T109	13		T198	5		T257	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T110	12		T170	8		T270	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T51	2		T217	12		T179	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T55	15		T16	1		T171	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T3	10		T155	9		T161	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	13		T168	14		T172	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T48	2		T224	16		T208	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T55	7		T52	4		T161	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T163	6		T179	17		T187	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T164	3		T294	10		T102	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T332	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T155	10		T168	9		T264	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T168	9		T253	12		T36	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T55	8		T170	18		T188	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T238	11		T232	3		T294	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T315	1		T345	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T256	16		T365	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T1	1		T155	11		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T168	1		T115	1		T173	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T8	2		T15	2		T157	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T15	3		T110	3		T273	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	9		T214	3		T164	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T158	1		T159	15		T53	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T1	5		T2	3		T6	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	5		T18	12		T17	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T15	1		T157	12		T49	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T109	13		T159	1		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T166	1		T112	10		T170	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T51	11		T162	1		T173	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T15	3		T16	6		T156	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T158	1		T155	13		T217	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T10	13		T11	1		T55	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	7		T224	11		T208	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T158	1		T52	13		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T156	5		T48	4		T202	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T55	7		T170	12		T294	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T238	9		T232	2		T294	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T345	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T256	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T155	10		T168	9		T264	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T168	9		T173	14		T253	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T109	7		T171	6		T263	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T15	1		T110	11		T347	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T12	6		T164	7		T278	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T53	3		T54	4		T176	25
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T1	4		T2	32		T6	25
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T12	3		T17	10		T171	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T49	3		T109	8		T161	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T109	13		T198	5		T257	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T170	8		T270	7		T262	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T51	2		T179	13		T252	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T16	1		T110	12		T171	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T155	9		T217	12		T161	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	13		T55	15		T168	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	10		T224	16		T208	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T52	4		T161	3		T164	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T48	2		T163	6		T176	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

auto[0]

4032

1

T1

4

T2

32

T3

10