Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T55	8		T157	12		T155	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T158	1		T166	1		T109	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T16	2		T217	16		T224	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T155	13		T160	13		T270	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T16	6		T158	1		T48	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T52	13		T173	11		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T2	3		T6	2		T7	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	5		T55	11		T164	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T12	9		T47	4		T17	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	1		T208	4		T163	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	7		T109	13		T159	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T15	2		T18	12		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T1	1		T270	1		T202	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	5		T168	1		T176	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T10	13		T15	3		T156	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T51	11		T162	1		T188	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T15	1		T156	11		T110	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	3		T168	1		T49	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T253	13		T170	9		T214	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T252	1		T21	6		T102	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T55	7		T155	10		T176	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T109	7		T110	12		T172	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T217	12		T224	5		T179	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T155	9		T270	11		T262	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T16	1		T48	2		T161	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T52	4		T198	5		T35	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T2	32		T6	25		T167	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	3		T55	15		T277	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	6		T47	1		T17	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T11	13		T208	2		T163	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	10		T109	13		T209	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T171	12		T20	3		T89	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T270	7		T36	3		T85	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T1	4		T168	9		T176	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T168	14		T50	1		T161	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T51	2		T278	3		T279	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T110	11		T53	3		T170	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T15	1		T168	9		T49	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T253	12		T170	8		T264	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T252	13		T21	1		T102	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T156	11		T274	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T171	1		T186	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T271	8		T272	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T55	8		T157	12		T176	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T158	1		T166	1		T109	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T16	2		T155	11		T217	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T155	13		T253	5		T275	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	2		T158	1		T48	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T52	13		T160	13		T173	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T16	6		T161	1		T170	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	5		T55	11		T198	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T2	3		T6	2		T7	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	1		T15	2		T164	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	7		T47	4		T109	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T158	1		T171	1		T208	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T1	1		T159	10		T270	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T18	12		T159	1		T179	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T10	13		T156	5		T50	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	5		T168	1		T173	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	382	1			T15	4		T168	1		T110	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T15	3		T168	1		T49	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T171	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T271	6		T272	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T55	7		T176	4		T265	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T109	7		T110	12		T172	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T155	10		T217	12		T179	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T155	9		T253	4		T275	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T48	2		T224	5		T161	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T52	4		T270	11		T262	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T16	1		T161	3		T170	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T12	3		T55	15		T198	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T2	32		T6	25		T12	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	13		T257	13		T280	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	10		T47	1		T109	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T171	12		T208	2		T163	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T270	7		T163	6		T176	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T179	10		T20	3		T238	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T50	1		T161	14		T265	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T1	4		T168	9		T173	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T168	14		T110	11		T53	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T15	1		T168	9		T49	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

auto[0]

4032

1

T1

4

T2

32

T3

10