Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

21

T2

35

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23034

1

T1

20

T2

35

T3

17

auto[ADC_CTRL_FILTER_COND_OUT]

3287

1

T1

1

T11

14

T15

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20029

1

T1

21

T5

14

T8

24

auto[1]

6292

1

T2

35

T3

17

T6

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22273

1

T1

16

T2

35

T3

11

auto[1]

4048

1

T1

5

T3

6

T7

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	502	1			T8	2		T12	2		T15	12
values[0]	24	1			T281	1		T282	16		T283	7
values[1]	688	1			T157	12		T155	21		T166	1
values[2]	2968	1			T2	35		T6	27		T7	8
values[3]	674	1			T16	7		T156	11		T168	10
values[4]	729	1			T12	23		T158	1		T171	11
values[5]	762	1			T1	1		T11	14		T55	26
values[6]	644	1			T110	14		T224	21		T161	10
values[7]	594	1			T15	4		T47	5		T168	10
values[8]	634	1			T1	9		T15	3		T16	2
values[9]	1269	1			T3	17		T15	2		T156	5
minimum	16833	1			T1	11		T5	14		T8	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	821	1			T15	1		T18	12		T55	15
values[1]	2984	1			T2	35		T6	27		T7	8
values[2]	800	1			T12	15		T16	7		T158	1
values[3]	677	1			T110	23		T171	11		T159	10
values[4]	688	1			T1	1		T12	8		T17	26
values[5]	647	1			T11	14		T47	5		T55	26
values[6]	585	1			T15	4		T16	2		T155	22
values[7]	572	1			T15	5		T109	17		T112	10
values[8]	1053	1			T1	9		T3	17		T156	5
values[9]	134	1			T8	2		T284	11		T116	12
minimum	17360	1			T1	11		T5	14		T8	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

4032

1

T1

4

T2

32

T3

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T15	1		T55	8		T224	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T18	1		T155	11		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1606	1			T2	35		T6	27		T7	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T157	2		T158	1		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	8		T16	2		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T50	2		T171	7		T172	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T110	13		T171	11		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T160	1		T275	4		T85	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T12	5		T17	11		T109	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T1	1		T168	15		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T47	4		T109	8		T110	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	14		T55	16		T161	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T155	10		T170	13		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T15	3		T16	1		T168	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T15	2		T115	1		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T15	2		T109	9		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T1	5		T3	11		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T158	1		T48	5		T52	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T8	2		T116	12		T285	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T284	11		T185	1		T286	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T287	10		T281	1		T196	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T55	7		T214	4		T188	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T18	11		T155	10		T51	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T7	7		T9	27		T10	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T157	13		T214	2		T264	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	7		T16	5		T85	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T50	1		T172	8		T170	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T110	10		T159	9		T254	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T160	12		T275	3		T85	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T12	3		T17	15		T109	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T163	14		T186	18		T288	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T47	1		T109	14		T110	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T55	10		T170	8		T164	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T155	12		T170	17		T186	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T15	1		T16	1		T49	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T15	1		T203	1		T264	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T109	8		T112	9		T173	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T1	4		T3	6		T156	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T48	1		T52	7		T217	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T285	18		T289	1		T290	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T286	6		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T287	11		T281	11		T196	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	489	1			T8	2		T12	2		T15	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T291	1		T286	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T281	1		T282	16		T283	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T224	6		T214	1		T188	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T157	1		T155	11		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1589	1			T2	35		T6	27		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T18	1		T157	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T16	2		T156	1		T168	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T50	2		T171	7		T172	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	13		T158	1		T171	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T160	1		T170	6		T36	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T17	11		T109	14		T110	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	1		T11	14		T55	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T110	12		T224	12		T198	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T161	10		T162	1		T170	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T47	4		T109	8		T186	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T15	3		T168	10		T49	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	5		T15	2		T155	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T16	1		T109	9		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T3	11		T156	1		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T15	2		T158	1		T48	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16694	1			T1	10		T5	14		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T286	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T214	4		T188	2		T176	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T157	11		T155	10		T51	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T7	7		T9	27		T10	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T18	11		T157	2		T214	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T16	5		T156	10		T159	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T50	1		T172	8		T214	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	10		T254	15		T263	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T160	12		T170	2		T36	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T17	15		T109	12		T110	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T55	10		T186	8		T275	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T110	2		T224	9		T36	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T170	8		T163	14		T186	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T47	1		T109	14		T186	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T15	1		T49	5		T159	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T1	4		T15	1		T155	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T16	1		T109	8		T173	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T3	6		T156	4		T53	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T48	1		T112	9		T52	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T15	1		T55	8		T224	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T18	12		T155	11		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T2	3		T6	2		T7	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T157	15		T158	1		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	9		T16	6		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T50	2		T171	1		T172	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T110	11		T171	1		T159	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T160	13		T275	4		T85	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T12	5		T17	16		T109	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	1		T168	1		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T47	4		T109	15		T110	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	1		T55	11		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T155	13		T170	18		T186	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T15	3		T16	2		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T15	3		T115	1		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T15	2		T109	9		T112	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T1	5		T3	7		T156	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T158	1		T48	4		T52	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T8	2		T116	1		T285	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T284	1		T185	1		T286	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T287	12		T281	12		T196	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T55	7		T224	5		T176	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T155	10		T51	2		T161	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T2	32		T6	25		T167	30
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T264	11		T179	10		T85	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T12	6		T16	1		T168	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T50	1		T171	6		T172	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T110	12		T171	10		T164	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T275	3		T85	2		T292	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T12	3		T17	10		T109	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T168	14		T163	11		T101	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T47	1		T109	7		T110	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	13		T55	15		T161	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T155	9		T170	12		T262	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T15	1		T168	9		T49	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T264	11		T179	17		T257	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T109	8		T270	7		T278	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T1	4		T3	10		T53	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T48	2		T52	4		T217	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T116	11		T285	14		T289	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T284	10		T286	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T287	9		T196	2		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	489	1			T8	2		T12	2		T15	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T291	1		T286	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T281	1		T282	1		T283	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T224	1		T214	5		T188	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T157	12		T155	11		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T2	3		T6	2		T7	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T18	12		T157	3		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T16	6		T156	11		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T50	2		T171	1		T172	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T12	14		T158	1		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T160	13		T170	3		T36	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T17	16		T109	13		T110	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T1	1		T11	1		T55	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T110	3		T224	10		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T161	1		T162	1		T170	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T47	4		T109	15		T186	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	3		T168	1		T49	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	5		T15	3		T155	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T16	2		T109	9		T173	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	390	1			T3	7		T156	5		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T15	2		T158	1		T48	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16833	1			T1	11		T5	14		T8	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T286	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T282	15		T283	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T224	5		T176	4		T265	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T155	10		T51	2		T161	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T2	32		T6	25		T55	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T179	10		T275	8		T85	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T16	1		T168	9		T253	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T50	1		T171	6		T172	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	9		T171	10		T161	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T170	5		T36	3		T85	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T17	10		T109	13		T110	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T11	13		T55	15		T168	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T110	11		T224	11		T198	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T161	9		T170	8		T163	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T47	1		T109	7		T264	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T15	1		T168	9		T49	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	4		T155	9		T173	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T109	8		T278	3		T89	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T3	10		T53	3		T208	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T48	2		T52	4		T217	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

auto[0]

4032

1

T1

4

T2

32

T3

10