Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

21

T2

35

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22618

1

T1

20

T2

35

T5

14

auto[ADC_CTRL_FILTER_COND_OUT]

3703

1

T1

1

T3

17

T12

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20496

1

T1

11

T5

14

T8

24

auto[1]

5825

1

T1

10

T2

35

T3

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22273

1

T1

16

T2

35

T3

11

auto[1]

4048

1

T1

5

T3

6

T7

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T293	1		T220	1		-	-
values[0]	83	1			T279	14		T285	33		T294	11
values[1]	605	1			T1	1		T12	15		T168	10
values[2]	756	1			T15	5		T158	1		T168	15
values[3]	466	1			T156	11		T49	13		T110	14
values[4]	802	1			T17	26		T155	21		T168	10
values[5]	2927	1			T2	35		T6	27		T7	8
values[6]	616	1			T1	9		T12	8		T47	5
values[7]	762	1			T3	17		T15	4		T55	15
values[8]	618	1			T11	14		T15	1		T16	2
values[9]	1364	1			T8	2		T10	13		T18	12
minimum	17320	1			T1	11		T5	14		T8	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	897	1			T1	1		T12	15		T168	10
values[1]	606	1			T15	2		T158	1		T168	15
values[2]	587	1			T15	3		T156	11		T168	10
values[3]	2904	1			T2	35		T6	27		T7	8
values[4]	741	1			T109	26		T217	28		T173	11
values[5]	792	1			T1	9		T12	8		T47	5
values[6]	557	1			T3	17		T11	14		T15	5
values[7]	812	1			T16	2		T157	3		T48	6
values[8]	896	1			T8	2		T10	13		T18	12
values[9]	184	1			T171	7		T89	3		T295	1
minimum	17345	1			T1	11		T5	14		T8	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

4032

1

T1

4

T2

32

T3

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T12	8		T115	1		T209	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T1	1		T168	10		T173	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T158	1		T168	15		T172	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T15	2		T159	1		T188	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T15	2		T49	8		T109	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T156	1		T168	10		T110	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1554	1			T2	35		T6	27		T7	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T155	11		T159	1		T224	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T109	14		T217	13		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T54	10		T186	1		T278	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	5		T158	1		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T12	5		T47	4		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	14		T15	1		T253	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	11		T15	3		T55	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T157	1		T48	5		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T16	1		T270	12		T176	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T8	2		T10	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T18	1		T55	16		T16	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T171	7		T89	3		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T296	3		T297	14		T298	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T228	1		T299	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T12	7		T164	13		T179	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T173	14		T257	5		T275	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T172	8		T53	6		T257	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T159	14		T188	2		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T15	1		T49	5		T109	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T156	10		T110	2		T160	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T7	7		T9	27		T17	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T155	10		T159	9		T208	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T109	12		T217	15		T173	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T54	6		T186	8		T278	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T1	4		T262	9		T288	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	3		T47	1		T156	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T253	4		T214	2		T203	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	6		T15	1		T55	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T157	2		T48	1		T51	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T16	1		T176	11		T186	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T10	12		T155	12		T109	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T18	11		T55	10		T16	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T300	3		T301	15		T289	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T296	6		T297	12		T298	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T228	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T293	1		T220	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T294	11		T302	1		T269	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T279	14		T285	15		T303	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	8		T115	1		T164	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	1		T168	10		T173	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T15	2		T158	1		T168	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T15	2		T159	1		T164	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T49	8		T163	12		T254	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T156	1		T110	12		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T17	11		T109	9		T52	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T155	11		T168	10		T224	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T2	35		T6	27		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T159	1		T164	1		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T1	5		T115	1		T161	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	5		T47	4		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T158	1		T214	1		T203	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	11		T15	3		T55	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	14		T15	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T16	1		T162	2		T270	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T8	2		T10	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	407	1			T18	1		T55	16		T16	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T304	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T285	18		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T12	7		T164	13		T179	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T173	14		T257	5		T275	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T15	1		T172	8		T53	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T159	14		T164	9		T179	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T49	5		T163	14		T254	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T156	10		T110	2		T188	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T17	15		T109	8		T52	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T155	10		T160	12		T208	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	996	1			T7	7		T9	27		T57	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T159	9		T164	9		T186	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T1	4		T170	17		T262	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	3		T47	1		T156	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T214	2		T203	1		T305	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	6		T15	1		T55	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T157	2		T51	7		T253	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T16	1		T176	11		T186	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T10	12		T155	12		T48	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T18	11		T55	10		T16	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	9		T115	1		T209	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T1	1		T168	1		T173	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T158	1		T168	1		T172	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T15	2		T159	15		T188	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T15	3		T49	10		T109	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T156	11		T168	1		T110	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T2	3		T6	2		T7	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T155	11		T159	10		T224	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T109	13		T217	16		T173	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T54	12		T186	9		T278	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	5		T158	1		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T12	5		T47	4		T156	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	1		T15	1		T253	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	7		T15	3		T55	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T157	3		T48	4		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T16	2		T270	1		T176	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T8	2		T10	13		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T18	12		T55	11		T16	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T171	1		T89	1		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T296	7		T297	13		T298	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T228	13		T299	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	6		T209	15		T164	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T168	9		T173	14		T257	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T168	14		T172	4		T53	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T164	3		T264	11		T179	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T49	3		T109	8		T170	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T168	9		T110	11		T179	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T2	32		T6	25		T17	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T155	10		T224	5		T208	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T109	13		T217	12		T170	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T54	4		T278	3		T86	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T1	4		T161	23		T270	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T12	3		T47	1		T253	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T11	13		T253	4		T305	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T3	10		T15	1		T55	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T48	2		T51	2		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T270	11		T176	13		T284	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T155	9		T109	7		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T55	15		T16	1		T171	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T171	6		T89	2		T300	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T296	2		T297	13		T298	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T299	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T293	1		T220	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T294	1		T302	1		T269	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T279	1		T285	19		T303	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	9		T115	1		T164	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	1		T168	1		T173	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	3		T158	1		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T15	2		T159	15		T164	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T49	10		T163	15		T254	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T156	11		T110	3		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T17	16		T109	9		T52	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T155	11		T168	1		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T2	3		T6	2		T7	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T159	10		T164	10		T186	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	5		T115	1		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	5		T47	4		T156	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T158	1		T214	3		T203	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T3	7		T15	3		T55	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T15	1		T157	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T16	2		T162	2		T270	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	368	1			T8	2		T10	13		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	403	1			T18	12		T55	11		T16	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T294	10		T269	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T279	13		T285	14		T303	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T12	6		T164	7		T179	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T168	9		T173	14		T257	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T168	14		T172	4		T53	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T164	3		T179	13		T265	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T49	3		T163	11		T257	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T110	11		T264	11		T284	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T17	10		T109	8		T52	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T155	10		T168	9		T224	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T2	32		T6	25		T167	30
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T278	3		T86	5		T306	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T1	4		T161	14		T170	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	3		T47	1		T54	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T305	9		T256	11		T232	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	10		T15	1		T55	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T11	13		T51	2		T171	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T270	11		T176	13		T187	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T155	9		T48	2		T109	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T55	15		T16	1		T171	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

auto[0]

4032

1

T1

4

T2

32

T3

10