Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

21

T2

35

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22769

1

T1

20

T2

35

T3

17

auto[ADC_CTRL_FILTER_COND_OUT]

3552

1

T1

1

T11

14

T15

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19785

1

T1

21

T5

14

T8

24

auto[1]

6536

1

T2

35

T3

17

T6

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22273

1

T1

16

T2

35

T3

11

auto[1]

4048

1

T1

5

T3

6

T7

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	790	1			T8	2		T12	2		T15	12
values[0]	8	1			T307	8		-	-		-	-
values[1]	586	1			T155	21		T166	1		T224	6
values[2]	3108	1			T2	35		T6	27		T7	8
values[3]	711	1			T12	15		T16	7		T168	10
values[4]	706	1			T158	1		T171	11		T159	10
values[5]	695	1			T1	1		T12	8		T17	26
values[6]	706	1			T11	14		T55	26		T109	22
values[7]	576	1			T15	4		T47	5		T168	10
values[8]	622	1			T1	9		T15	3		T16	2
values[9]	980	1			T3	17		T15	2		T156	5
minimum	16833	1			T1	11		T5	14		T8	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	665	1			T18	12		T55	15		T155	21
values[1]	3043	1			T2	35		T6	27		T7	8
values[2]	794	1			T12	15		T16	7		T158	1
values[3]	651	1			T110	23		T171	11		T159	10
values[4]	722	1			T1	1		T12	8		T17	26
values[5]	629	1			T11	14		T47	5		T55	26
values[6]	557	1			T15	4		T16	2		T155	22
values[7]	628	1			T15	5		T109	17		T112	10
values[8]	1019	1			T1	9		T3	17		T156	5
values[9]	146	1			T8	2		T174	1		T284	11
minimum	17467	1			T1	11		T5	14		T8	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

4032

1

T1

4

T2

32

T3

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T188	1		T176	5		T164	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T18	1		T55	8		T155	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1548	1			T2	35		T6	27		T7	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T158	1		T162	1		T253	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	8		T16	2		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T172	5		T170	6		T275	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T110	13		T159	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T171	11		T262	11		T85	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T12	5		T109	14		T171	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	1		T17	11		T168	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T47	4		T109	8		T224	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T11	14		T55	16		T110	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T15	3		T168	10		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T16	1		T155	10		T49	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T15	2		T109	9		T115	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T15	2		T112	1		T173	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	5		T3	11		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T158	1		T48	5		T52	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T8	2		T174	1		T116	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T284	11		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17222	1			T1	10		T5	14		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T228	1		T285	12		T307	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T188	2		T176	9		T164	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T18	11		T55	7		T155	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T7	7		T9	27		T10	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T253	4		T214	2		T264	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	7		T16	5		T50	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T172	8		T170	2		T275	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T110	10		T159	9		T160	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T262	9		T85	2		T308	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	3		T109	12		T186	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T17	15		T253	12		T163	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T47	1		T109	14		T224	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T55	10		T110	2		T170	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T15	1		T159	14		T170	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T16	1		T155	12		T49	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T15	1		T109	8		T173	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T112	9		T173	10		T179	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	4		T3	6		T156	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T48	1		T52	7		T217	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T285	18		T309	12		T286	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	1		T8	2		T10	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T228	12		T285	5		T307	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	549	1			T8	2		T12	2		T15	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T217	13		T176	13		T284	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T307	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T224	6		T188	1		T176	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T155	11		T166	1		T161	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T2	35		T6	27		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T18	1		T55	8		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	8		T16	2		T168	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T172	5		T253	5		T170	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T158	1		T159	1		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T171	11		T262	11		T36	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	5		T109	14		T110	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T1	1		T17	11		T168	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T109	8		T224	12		T198	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	14		T55	16		T110	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	3		T47	4		T168	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T49	8		T270	20		T164	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	5		T15	2		T109	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T16	1		T155	10		T112	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T3	11		T156	1		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T15	2		T158	1		T48	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16694	1			T1	10		T5	14		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T285	18		T286	6		T195	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T217	15		T176	12		T42	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T307	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T188	2		T176	9		T164	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T155	10		T214	4		T254	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T7	7		T9	27		T10	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T18	11		T55	7		T51	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	7		T16	5		T50	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T172	8		T253	4		T170	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T159	9		T160	12		T263	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T262	9		T36	4		T85	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	3		T109	12		T110	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T17	15		T253	12		T254	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T109	14		T224	9		T305	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T55	10		T110	2		T170	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T47	1		T159	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T49	5		T164	9		T238	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T1	4		T15	1		T109	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T16	1		T155	12		T112	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	6		T156	4		T53	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T48	1		T52	7		T187	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T188	3		T176	10		T164	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T18	12		T55	8		T155	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T2	3		T6	2		T7	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T158	1		T162	1		T253	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	9		T16	6		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T172	9		T170	3		T275	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T110	11		T159	10		T160	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T171	1		T262	10		T85	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	5		T109	13		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	1		T17	16		T168	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T47	4		T109	15		T224	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	1		T55	11		T110	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	3		T168	1		T159	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T16	2		T155	13		T49	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	3		T109	9		T115	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T15	2		T112	10		T173	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T1	5		T3	7		T156	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T158	1		T48	4		T52	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T8	2		T174	1		T116	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T284	1		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17340	1			T1	11		T5	14		T8	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T228	13		T285	6		T307	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T176	4		T35	6		T310	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T55	7		T155	10		T51	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T2	32		T6	25		T167	30
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T253	4		T264	11		T179	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	6		T16	1		T168	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T172	4		T170	5		T275	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T110	12		T164	7		T263	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T171	10		T262	10		T85	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	3		T109	13		T171	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T17	10		T168	14		T253	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T47	1		T109	7		T224	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	13		T55	15		T110	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T15	1		T168	9		T170	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T155	9		T49	3		T270	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T109	8		T173	14		T264	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T179	17		T278	3		T311	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	4		T3	10		T53	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T48	2		T52	4		T217	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T116	11		T285	14		T309	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T284	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T224	5		T265	2		T275	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T285	11		T307	2		T282	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	575	1			T8	2		T12	2		T15	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T217	16		T176	13		T284	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T307	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T224	1		T188	3		T176	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T155	11		T166	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T2	3		T6	2		T7	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T18	12		T55	8		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	9		T16	6		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T172	9		T253	5		T170	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T158	1		T159	10		T160	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T171	1		T262	10		T36	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	5		T109	13		T110	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	1		T17	16		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T109	15		T224	10		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	1		T55	11		T110	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T15	3		T47	4		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T49	10		T270	2		T164	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T1	5		T15	3		T109	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T16	2		T155	13		T112	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T3	7		T156	5		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T15	2		T158	1		T48	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16833	1			T1	11		T5	14		T8	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T285	14		T286	5		T312	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T217	12		T176	12		T284	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T307	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T224	5		T176	4		T265	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T155	10		T161	14		T187	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T2	32		T6	25		T167	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T55	7		T51	2		T264	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	6		T16	1		T168	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T172	4		T253	4		T170	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T161	3		T263	1		T93	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T171	10		T262	10		T36	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	3		T109	13		T110	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T17	10		T168	14		T253	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T109	7		T224	11		T198	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	13		T55	15		T110	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T15	1		T47	1		T168	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T49	3		T270	18		T164	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	4		T109	8		T173	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T155	9		T179	17		T262	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	10		T53	3		T208	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T48	2		T52	4		T187	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

auto[0]

4032

1

T1

4

T2

32

T3

10