Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

21

T2

35

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22842

1

T1

21

T2

35

T3

17

auto[ADC_CTRL_FILTER_COND_OUT]

3479

1

T11

14

T12

15

T15

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20295

1

T1

20

T3

17

T5

14

auto[1]

6026

1

T1

1

T2

35

T6

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22273

1

T1

16

T2

35

T3

11

auto[1]

4048

1

T1

5

T3

6

T7

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	47	1			T187	18		T313	22		T314	7
values[0]	40	1			T155	21		T85	5		T116	12
values[1]	669	1			T15	2		T156	5		T171	11
values[2]	745	1			T17	26		T157	3		T168	15
values[3]	740	1			T47	5		T55	15		T16	2
values[4]	558	1			T16	7		T157	12		T158	1
values[5]	621	1			T3	17		T55	26		T156	11
values[6]	678	1			T8	2		T158	1		T109	26
values[7]	678	1			T1	9		T12	8		T49	13
values[8]	754	1			T1	1		T11	14		T12	15
values[9]	3471	1			T2	35		T6	27		T7	8
minimum	17320	1			T1	11		T5	14		T8	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	889	1			T15	2		T17	26		T156	5
values[1]	647	1			T47	5		T157	3		T168	10
values[2]	720	1			T55	15		T16	2		T157	12
values[3]	614	1			T16	7		T158	1		T155	22
values[4]	716	1			T3	17		T55	26		T156	11
values[5]	533	1			T1	9		T8	2		T158	1
values[6]	2925	1			T1	1		T2	35		T6	27
values[7]	822	1			T11	14		T12	15		T158	1
values[8]	923	1			T15	5		T109	17		T50	3
values[9]	211	1			T10	13		T15	3		T18	12
minimum	17321	1			T1	11		T5	14		T8	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

4032

1

T1

4

T2

32

T3

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T15	2		T17	11		T156	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T168	15		T171	11		T170	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T208	3		T54	10		T265	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T47	4		T157	1		T168	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T16	1		T159	1		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T55	8		T157	1		T254	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T16	2		T158	1		T155	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T161	15		T315	1		T36	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	11		T55	16		T48	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T156	1		T166	1		T51	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	5		T8	2		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T158	1		T109	14		T110	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1600	1			T1	1		T2	35		T6	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T49	8		T110	12		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T224	12		T161	4		T173	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T11	14		T12	8		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T15	3		T109	9		T50	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T15	1		T159	1		T172	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T10	1		T18	1		T316	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T15	2		T224	6		T174	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T317	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T17	15		T156	4		T155	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T170	10		T214	2		T186	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T208	3		T54	6		T228	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T47	1		T157	2		T112	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T16	1		T257	5		T275	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T55	7		T157	11		T254	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T16	5		T155	12		T179	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T36	4		T218	10		T128	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	6		T55	10		T48	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T156	10		T51	7		T164	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T1	4		T188	2		T257	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T109	12		T110	10		T179	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1039	1			T7	7		T9	27		T12	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T49	5		T110	2		T176	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T224	9		T173	14		T186	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T12	7		T52	7		T159	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T15	1		T109	8		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T159	9		T172	8		T163	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T10	12		T18	11		T316	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T15	1		T187	7		T257	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T314	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T187	11		T313	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T155	11		T85	3		T318	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T116	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	2		T156	1		T53	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T171	11		T170	15		T214	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T17	11		T54	10		T174	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T157	1		T168	15		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T16	1		T159	1		T208	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T47	4		T55	8		T168	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T16	2		T158	1		T48	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T157	1		T254	1		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	11		T55	16		T155	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T156	1		T166	1		T51	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T8	2		T257	7		T36	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T158	1		T109	14		T110	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	5		T12	5		T109	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T49	8		T110	12		T115	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T1	1		T168	10		T161	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	14		T12	8		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1652	1			T2	35		T6	27		T7	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T15	3		T159	1		T224	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T314	6		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T187	7		T313	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T155	10		T85	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T156	4		T53	6		T214	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T170	10		T214	2		T186	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T17	15		T54	6		T20	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T157	2		T112	9		T186	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T16	1		T208	3		T275	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T47	1		T55	7		T254	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T16	5		T48	1		T179	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T157	11		T254	6		T182	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	6		T55	10		T155	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T156	10		T51	7		T264	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T257	6		T36	6		T310	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T109	12		T110	10		T164	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	4		T12	3		T109	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T49	5		T110	2		T176	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T173	14		T186	13		T275	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	7		T52	7		T159	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1139	1			T7	7		T9	27		T10	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T15	1		T159	9		T172	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T15	2		T17	16		T156	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T168	1		T171	1		T170	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T208	4		T54	12		T265	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T47	4		T157	3		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T16	2		T159	1		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T55	8		T157	12		T254	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T16	6		T158	1		T155	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T161	1		T315	1		T36	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	7		T55	11		T48	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T156	11		T166	1		T51	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	5		T8	2		T188	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T158	1		T109	13		T110	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T1	1		T2	3		T6	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T49	10		T110	3		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T224	10		T161	1		T173	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T11	1		T12	9		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T15	3		T109	9		T50	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T15	1		T159	10		T172	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T10	13		T18	12		T316	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T15	3		T224	1		T174	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T317	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T17	10		T155	10		T53	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T168	14		T171	10		T170	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T208	2		T54	4		T265	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T47	1		T168	9		T198	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T257	2		T275	3		T86	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T55	7		T252	13		T262	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T16	1		T155	9		T179	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T161	14		T36	3		T218	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	10		T55	15		T48	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T51	2		T270	7		T164	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T1	4		T257	6		T36	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T109	13		T110	12		T161	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T2	32		T6	25		T12	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T49	3		T110	11		T171	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T224	11		T161	3		T173	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	13		T12	6		T52	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T15	1		T109	8		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T172	4		T209	15		T163	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T238	9		T319	16		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T224	5		T187	10		T257	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T314	7		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T187	8		T313	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T155	11		T85	3		T318	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T116	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T15	2		T156	5		T53	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T171	1		T170	12		T214	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T17	16		T54	12		T174	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T157	3		T168	1		T112	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T16	2		T159	1		T208	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T47	4		T55	8		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T16	6		T158	1		T48	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T157	12		T254	7		T182	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	7		T55	11		T155	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T156	11		T166	1		T51	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	2		T257	7		T36	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T158	1		T109	13		T110	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T1	5		T12	5		T109	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T49	10		T110	3		T115	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	1		T168	1		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	1		T12	9		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1487	1			T2	3		T6	2		T7	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	395	1			T15	4		T159	10		T224	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T187	10		T313	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T155	10		T85	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T116	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T53	3		T187	15		T89	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T171	10		T170	13		T85	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T17	10		T54	4		T20	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T168	14		T198	5		T262	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T208	2		T265	9		T275	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T47	1		T55	7		T168	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T16	1		T48	2		T179	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T36	3		T311	1		T279	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	10		T55	15		T155	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T51	2		T161	14		T264	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T257	6		T36	6		T310	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T109	13		T110	12		T161	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	4		T12	3		T109	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T49	3		T110	11		T176	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T168	9		T161	3		T173	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	13		T12	6		T52	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T2	32		T6	25		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T224	5		T172	4		T209	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

auto[0]

4032

1

T1

4

T2

32

T3

10